WO2012065301A1

WO2012065301A1 - Field programmable gate array (fpga) and fast multi-protocol label switching (mpls) operation administration and maintenance (oam) protection switching method

Info

Publication number: WO2012065301A1
Application number: PCT/CN2010/078818
Authority: WO
Inventors: Tony Gao
Original assignee: Telefonaktiebolaget L M Ericsson (Publ)
Priority date: 2010-11-17
Filing date: 2010-11-17
Publication date: 2012-05-24

Abstract

A Field Programmable Gate Array (FPGA) which communicates with a CPU and a switch chip for fast Multi-Protocol Label Switching (MPLS) Operation Administration and Maintenance (OAM) protection switching is provided. The FPGA comprises a link checking unit for checking whether or not a line is available; an instruction generating unit for generating, when the line checking unit determines that the line is not available at this time, a switchover instruction for the switch chip to modify switch table in the switch chip; a switch chip communicating unit for transmitting the switchover instruction generated by the instruction generating unit to the switch chip; and a processor communicating unit for transmitting current link information to the CPU, the current link information being generated based on the switchover instruction generated by the instruction generating unit. A fast MPLS OAM protection switching method implemented by means of the FPGA is also provided.

Description

FPGA AND FAST MPLS OAM PROTECTION SWITCHING METHOD

FIELD OF THE INVENTION

The invention relates to Multi-Protocol Label Switching (MPLS) networks, and more particularly, to a method and device for implementing fast MPLS Operation, Administration and Maintenance (OAM) protection switching.

BACKGROUND OF THE INVENTION

In MPLS networks, the OAM functions are defined and provided as including: defect detection, defect information notification, defect localization/isolation, survivability techniques, and performance management. Without these capabilities, it is impossible to provide "carrier-class" services.

One of the most important aspects of all these above capabilities is survivability techniques. Without survivability, service restoration cannot be reached on the order of a few milliseconds (~ms).

In fact, MPLS OAM provides a set of check mechanism separately for the MPLS user layer (which is independent of other network layers and provides the state information of LSP for users), provides abundant Label Switched Path (LSP) diagnosis interfaces for network management and maintenance personnel, and provides reference for network performance detection and user charging. While providing above functions as a check tool, MPLS OAM has also a complete protection switching mechanism and shall switch over user data within 50 ms after MPLS layer detects defects to minimize the loss of user data.

Protection switching is one mechanism of survivability techniques. Protection switching implies that both routing and resources are pre-calculated and allocated to a dedicated protection LSP prior to failure. Protection switching therefore offers a strong assurance of being able to re-obtain the required network resources post failure.

Due to more and more LSPs to be supported (up to many thousands), switching performance becomes critical to protection switching. The efficiency of switchover is a key point for OAM. Fig. 1 is a schematic diagram for illustrating protection switching operation within a provider's network (MPLS network). As shown in Fig. 1 , a physical link

(working LSP) is established between Provider Edge (PE) router PE-A and PE router PE-B through Provider (P) router P-1 for communications between

Customer Edge (CE) router CE-A and CE router CE-B. As this communication link is a vulnerable physical link, an LSP tunnel is set up through the provider's network to provide a backup for the vulnerable physical link. The LSP tunnel provides a parallel virtual link (protection LSP) between PE router PE-A and PE router PE-B through another P router P-2. When the working LSP fails, the upstream node switches traffic from the physical link (working LSP) to the virtual link (protection LSP), so that data continues to flow between PE routers PE-A and PE-B (and thus between CE routers CE-A and CE-B) with minimal disruption.

Fig. 2 is a schematic diagram for showing the communications among a switch chip 210 in a router, FPGA 220 and CPU 230 according to the prior arts. FPGA 220 takes part role of OAM function, and transmits and receives OAM packets. CPU 230 performs link status setup and maintenance. CPU 230 can also transmit and receive OAM packets, but if the amount of paths (LSPs) to be supported is very large, it is too hard for CPU 230 because its competence of packet processing is not powerful enough. Switch chip (also referred to as "Network Processor (NP)") 210 fulfills packet switching. FPGA transmits and receives OAM packets to and from switch chip 210. There is a switch table stored in switch chip 210. For example, Table 1 shows an example of the switch table. According to Table 1 , a packet from a link labeled '100' will be switched to a link labeled '116'; and a packet from a link labeled '200' will be switched to a link labeled '239'. That is, the links labeled '116' and '239' are now the working LSPs. Also, Table 1 shows the protection LSPs as a link labeled '105' and a link labeled '228'.

Table 1

When FPGA 220 cannot receive remote packets or receive an alarm packet from remote endpoint (Step 1 ), FPGA 220 will notice CPU 230 by an interrupt to perform protection switching (Step 2), then CPU 230 will transmit switchover messages to switch chip 210 (Step 3) to make switch chip 210 modify its switch table (e.g., Table 1 ) in which the main and backup indication will be changed, For example, Table 2 shows an example of the changed switch table

corresponding to Table . At this time, according to Table 2, a packet from the link labeled ' 00' will be switched to the link labeled Ί 05; and a packet from the link labeled '200' will be switched to a link labeled '228. That is, the links labeled '116' and '239' are now changed into the working LSPs, whereas the links labeled ' 05' and '228' are now changed into the protection LSPs.

Table 2

Traditionally, it is usual to implement protection switching by software instructions. Software protocol stack modifies forwarding table, disables working LSP and enables backup LSP, and makes backup OAM session active. This makes it harder to recover quickly, for example to hit the recovery goal of 50 ms.

However, local repair relies on the speed of processor and how many tasks to be handled. This can be slow which is unacceptable for many MPLS applications. With respect to the example shown in Fig. 2, there is a bottle neck that is the CPU 230's process speed. CPU 230 cannot process so many packets in time if too many paths (LSPs) are in fault status in the same time, and the efficiency of switchover will be debased. Further, even though one LSP switching can meet the requirement, it is still a great challenge when large amounts of defects occur.

SUMMARY OF THE INVENTION

To solve the above problems, a solution is proposed in the present invention to implementing fast MPLS OAM protection switching, especially, by using FPGA.

According to the first aspect of the invention, there is provided an FPGA which communicates with a CPU and a switch chip for fast MPLS OAM protection switching, the FPGA comprising: a link checking unit for checking whether or not a line is available; an instruction generating unit for generating, when the line checking unit determines that the line is not available at this time, a switchover instruction for the switch chip to modify switch table in the switch chip; a switch chip communicating unit for transmitting the switchover instruction generated by the instruction generating unit to the switch chip; and a processor communicating unit for transmitting current link information to the CPU, the current link

information being generated based on the switchover instruction generated by the instruction generating unit. The invention also provides a fast MPLS OAM protection switching method implemented by means of the inventive FPGA.

Preferably, when it finds that no packet can be received in a predetermined number of periods, the link checking unit determines that the line is not available.

Preferably, when it receives a remote defect indication packet, the link checking unit determines that the line is not available.

Preferably, the switchover instruction makes the switch chip exchange

corresponding active and inactive indications for the line in the switch table.

Preferably, the current link information is a switchover message that indicates which path should be active now. Preferably, the switch chip communicating unit also communicates with the switch chip to transmit and receive OAM packets to and from the switch chip.

Preferably, the processor communicating unit also communicates with the CPU to transmit and receive OAM packets to and from the CPU.

According to a second aspect of the present invention, there is also provided a fast MPLS OAM protection switching method, comprising: checking by an FPGA whether or not a line is available; generating by the FPGA, when it is determined that the line is not available at this time, a switchover instruction for a switch chip to modify switch table in the switch chip; transmitting by the FPGA the generated switchover instruction to the switch chip; and transmitting by the FPGA current link information to a CPU, the current link information being generated based on the generated switchover instruction.

Preferably, when it finds that no packet can be received in a predetermined number of periods, the FPGA determines that the line is not available.

Preferably, when it receives a remote defect indication packet, the FPGA determines that the line is not available. Preferably, the switchover instruction makes the switch chip exchange

corresponding active and inactive indications for the line in the switch table.

Preferably, the current link information is a switchover message that indicates which path should be active now.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will be clearer from the following detailed description about the non-limited embodiments of the present invention taken in conjunction with the accompanied drawings, in which:

Fig. 1 is a schematic diagram for illustrating protection switching operation within a provider's network (MPLS network).

Fig. 2 is a schematic diagram for showing the communications among a switch chip 210 in a router, FPGA 220 and CPU 230 according to the prior arts.

Fig. 3 is a schematic diagram for illustrating operation principles of the present invention.

Fig. 4 is a schematic diagram for showing the communications among a switch chip 410 in a router, FPGA 420 and CPU 430 according to the present invention. Fig. 5 is a schematic diagram for illustrating the structure of FPGA 420 according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereunder, the present invention will be described in accordance with the drawings. In the following description, some particular embodiments are used for the purpose of description only, which shall not be understood as any limitation to the present invention but the examples thereof. While it may blur the understanding of the present invention, the conventional structure or construction will be omitted.

Protection switching can be classified into two kinds:

■ * physical layer protection; and

^ logic layer (includes virtual circuit) protection.

Physical layer protection is prepared for physical defect. For example, if primary line card has physical damage, the traffic should be switched over to backup line card. Logic layer protection makes sense when the physical equipment works well but the virtual link is not available. When physical layer protection switching occurs, the primary line card need to notice the backup line card that defect occurred, and make the LSP in the backup line card active. Normally, the notice procedure will be completed as follows. If there is a direct path between the primary line card and the backup line card, FPGA on the primary line card will send a notice message to the backup line card directly. If there is no direct path between the primary line card and the backup line card, the FPGA on the primary card will send a message to a switch on the main board, and the message will then be transmitted to the backup line card indirectly. Then, the traffic will pass by the backup line card. When logic layer protection switching occurred, the physical port works well, it is only necessary to switch over to the backup virtual channel. The switching occurred in the primary line card itself.

The main concern with protection switching both physical layer protection switching and logic layer protection switching is the efficiency of switching. The error must be detected and reported to repair point. The backup LSP must be prepared, and finally data must be transferred from the working LSP to the backup LSP. The traditional approach for switching as described in Background of The

Invention consists in that the primary path detects defects and reports to CPU 230, then protocol stack changes the state of working path from active to inactive and changes the state of backup path from inactive to active via software instruction. This is a great challenge for CPU 230 to perform this task. The intrinsic disadvantage is that it is not real time. The process is linear not parallel. So it is hard to perform large amounts of LSPs switching over fast. It costs much time for one LSP's switch over, e.g., about several milliseconds (ms). When physical layer switch over occurs, large amounts of traffic need to be switch over to the backup line card, and large amounts of interrupts are reported to CPU 230, it is hard to be processed by CPU 230 in time, after all there are also other tasks to be processed by CPU 230 at the same time.

Fig. 3 is a schematic diagram for illustrating operation principles of the present invention. In the present invention, the inventor considers the great strongpoint for FPGA to perform protection switch. FPGA can do parallel process, if defect is detected (for example, no cv/ffd packets received over 3 periods), as shown in Fig. 3, FPGA can do switching by itself. FPGA will switch the state of LSPs in own line card when link layer defect occurs. Also, FPGA will send a packet

(containing LSPs state to be changed) to backup line card to accomplishment switching, and as discussed above, the amount of switching will be very large in this case. The process will last only several ten cycles to several hundreds of cycles. It is a great strongpoint of FPGA. For example, if FPGA is Xilinx V6 chip, the main clock runs at 200MHz, and sending a message costs 200 cycles, the above process will cost only about 1 /s (~1//s). This is a great advantage than CPU as CPU will cost several milliseconds (ms) to send a switchover message. Because the time cost to detect fault is the same for FPGA and CPU (which time is relevant to the detect mechanism), for example, the detect multi-periods is 3, and the transmission rate of connectivity packets is 3.3 ms, then the fault detection time cost is at least 10 ms. Assuming a typical protection switching requirement of 50 ms, there is only 40 ms or less left for performing switchover. Therefore, the FPGA's //s -level message sending time cost is much more advantageous than the CPU's ms-level message sending time cost.

Fig. 4 is a schematic diagram for showing the communications among a switch chip 4 0 in a router, FPGA 420 and CPU 430 according to the present invention.

According to Fig. 4, when FPGA 420 cannot receive remote packets or receive an alarm packet from remote endpoint (Step 1 ), FPGA 420 will notice CPU 430 to change link status but CPU 430 will not perform switchover, then instead, FPGA 420 will transmit switchover instructions to switch chip 410 to make switch chip 420 to modify its switch table (e.g., Table 1 ) in which the active and inactive indications will be exchanged. For example, Table 2 shows an example of the changed switch table corresponding to Table 1.

Because the efficiency of FPGA 420 to send packets is very high, the time to accomplish switchover will be much shorter and much fewer packet will be lost.

Fig. 5 is a schematic diagram for illustrating the structure of FPGA 420 according to the present invention.

As shown in Fig. 5, FPGA 420 includes a link checking unit 4210, an instruction generating unit 4220, a switch chip communicating unit 4230 and a processor communicating unit 4240.

The link checking unit 4210 checks whether or not the line is available. For example, when it finds that no packet can be received in a predetermined number of periods (e.g., 3 periods), the link checking unit 4210 determines that the line is not available. Otherwise, the link checking unit 4210 determines that the line is still available. Additionally/alternatively, when it receives a remote defect indication packet, the link checking unit 4210 may directly determines that the line is not available. Otherwise, the link checking unit 4210 determines that the line is still available.

The instruction generating unit 4220 generates, when the line checking unit 4210 determines that a line is not available at this time, a switchover instruction for the switch chip 410 to modify switch table in the switch chip 410 in which the active and inactive indications for the line will be exchanged.

The switch chip communicating unit 4230 communicates with the switch chip 410 to transmit and receive OAM packets to and from the switch chip 410.

Additionally, the switch chip communicating unit 4230 also transmits the switchover instruction generated by the instruction generating unit 4220 to the switch chip 410.

The processor communicating unit 4240 communicates with the CPU 430 to transmit and receive OAM packets to and from the CPU 430. Additionally, the processor communicating unit 4240 also transmits current link information to the CPU 430. The current link information may be a switchover message that indicates which path should be active now. The active path is decided by a fact that the switchover is from primary path to backup path or from backup path to primary path. The current link information is generated based on the switchover instruction generated by the instruction generating unit 4220.

The foregoing description gives only the preferred embodiments of the present invention and is not intended to limit the present invention in any way. Thus, any modification, substitution, improvement or like made within the spirit and principle of the present invention should be encompassed by the scope of the present invention.

Claims

What is claimed is:

1 . An FPGA which communicates with a CPU and a switch chip for fast MPLS OAM protection switching, the FPGA comprising:

a link checking unit for checking whether or not a line is available;

an instruction generating unit for generating, when the line checking unit determines that the line is not available at this time, a switchover instruction for the switch chip to modify switch table in the switch chip;

a switch chip communicating unit for transmitting the switchover instruction generated by the instruction generating unit to the switch chip; and a processor communicating unit for transmitting current link information to the CPU, the current link information being generated based on the switchover instruction generated by the instruction generating unit.

2. The FPGA according to claim 1 , wherein when it finds that no packet can be received in a predetermined number of periods, the link checking unit determines that the line is not available.

3. The FPGA according to claim 1 or 2, wherein when it receives a remote defect indication packet, the link checking unit determines that the line is not available.

4. The FPGA according to any one of claims 1 - 3, wherein the switchover instruction makes the switch chip exchange corresponding active and inactive indications for the line in the switch table.

5. The FPGA according to any one of claims 1 - 4, wherein the current link information is a switchover message that indicates which path should be active now.

6. The FPGA according to any one of claims 1 - 5, wherein the switch chip communicating unit also communicates with the switch chip to transmit and receive OAM packets to and from the switch chip.

7. The FPGA according to any one of claims 1 - 6, wherein the processor communicating unit also communicates with the CPU to transmit and receive OAM packets to and from the CPU.

8. A fast MPLS OAM protection switching method, comprising:

checking by an FPGA whether or not a line is available;

generating by the FPGA, when it is determined that the line is not available at this time, a switchover instruction for a switch chip to modify switch table in the switch chip;

transmitting by the FPGA the generated switchover instruction to the switch chip; and

transmitting by the FPGA current link information to a CPU, the current link information being generated based on the generated switchover instruction.

9. The fast MPLS OAM protection switching method according to claim 8, wherein when it finds that no packet can be received in a predetermined number of periods, the FPGA determines that the line is not available.

10. The fast MPLS OAM protection switching method according to claim 8 or 9, wherein when it receives a remote defect indication packet, the FPGA determines that the line is not available.

11 . The fast MPLS OAM protection switching method according to any one of claims 8 - 10, wherein the switchover instruction makes the switch chip exchange corresponding active and inactive indications for the line in the switch table. 2. The fast MPLS OAM protection switching method according to any one of claims 8 - 11 , wherein the current link information is a switchover message that indicates which path should be active now.