CN112825065A - Data processing circuit, apparatus and method - Google Patents
Data processing circuit, apparatus and method Download PDFInfo
- Publication number
- CN112825065A CN112825065A CN201911148502.8A CN201911148502A CN112825065A CN 112825065 A CN112825065 A CN 112825065A CN 201911148502 A CN201911148502 A CN 201911148502A CN 112825065 A CN112825065 A CN 112825065A
- Authority
- CN
- China
- Prior art keywords
- data
- packet header
- source
- destination
- network
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title abstract description 14
- 238000003672 processing method Methods 0.000 claims abstract description 9
- 230000003139 buffering effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 17
- 230000006870 function Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000004590 computer program Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The embodiment of the disclosure discloses a data processing circuit, a data processing device and a data processing method. Wherein the data processing circuit comprises: the device comprises a data input interface, a packet header generating circuit, a data buffer memory, a data generating circuit and a data output interface; the data input interface generates a data control signal and a target packet header conforming to a target network data format from a source packet header of an original data packet received from a source network; the data generating circuit takes the source data out of the data buffer memory according to the data control signal and generates target data conforming to the target network data format; and the data output interface sends the destination packet header and the destination data to the destination network. By the method, the technical problems of complex forwarding circuit, high power consumption and large delay in data forwarding between two networks in the prior art are solved.
Description
Technical Field
The present disclosure relates to the field of data processing, and in particular, to a data processing circuit, apparatus, and method.
Background
With the development of science and technology, the human society is rapidly entering the intelligent era. The chip is a fundamental stone of data processing and fundamentally determines the capability of people for processing data. From the application field, the chip mainly has two routes: one is a general chip route, such as a CPU (Central Processing Unit), which provides great flexibility but is less computationally efficient in Processing domain-specific algorithms; the other is a special chip route, such as TPU (Tensor Processing Unit), which can exert higher effective computing power in some specific fields, but has poorer or even no Processing capability in the more versatile and versatile fields. Because the data of the intelligent era is various and huge in quantity, the chip is required to have extremely high flexibility, can process algorithms in different fields and in different days, has extremely high processing capacity, and can rapidly process extremely large and sharply increased data volume.
In the existing chip, only data interaction between buses (buses) which realize a plurality of different protocols is generally realized, and format conversion of a data packet is performed through a Bridge (Bridge). Fig. 1 is a schematic diagram showing that data packets are forwarded between buses in the prior art through a bridge structure, where bus 1 and bus 2 use different protocols, for example, bus 1 is an SPI (serial Peripheral interface) bus, bus 2 is an AXI (advanced eXtensible interface) bus, and the two buses are interconnected through the bridge structure, and if data is transmitted from bus 1 to bus 2, the bridge is required to unpack the data packets on bus 1 according to the SPI protocol, and then pack the data according to the format of the AXI protocol and transmit the data to bus 2. Generally, the bridge needs to implement all protocol parsing, and has complex circuit, high cost and high power consumption, and because a complete unpacking and packing process is required, the time delay is large when the data packet is transmitted.
Disclosure of Invention
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
In order to solve the technical problems of complex circuit, high cost, high power consumption and large delay when a bridge forwards data in the prior art, the embodiment of the disclosure provides the following technical scheme:
in a first aspect, an embodiment of the present disclosure provides a data processing circuit, configured to process data sent from a source network to a destination network, where the data processing circuit includes:
the device comprises a data input interface, a packet header generating circuit, a data buffer memory, a data generating circuit and a data output interface;
the data input interface sends a source packet header of an original data packet received from a source network to the packet header generating circuit;
the data input interface sends source data of the original data packet received from a source network to the data buffer memory;
the packet header generating circuit generates a data control signal and a target packet header according with a target network data format according to the source packet header;
the data generating circuit takes the source data out of the data buffer memory according to the data control signal and generates target data conforming to the target network data format;
and the data output interface sends the destination packet header and the destination data to the destination network.
Further, the source network and the destination network use the same protocol and different bit widths.
Furthermore, the number of the data generating circuits and the number of the data output interfaces are multiple, and different data generating circuits and different data output interfaces correspond to different destination networks.
Further, the packet header generating circuit includes:
the device comprises a packet header parser, a packet header latch circuit and a latch signal generator;
the packet header generating circuit generates a data control signal and a destination packet header conforming to a destination network data format according to the source packet header, and includes:
the packet header analyzer generates a destination network selection signal according to the source packet header;
the latch signal generator generates a latch signal according to the destination network selection signal;
the packet header latch circuit latches the source packet header according to the latch signal and modifies control information in the source packet header according to the bit width of the destination network to generate the destination packet header.
Further, the data generating circuit fetches the source data from the data buffer memory according to the data control signal, and generates destination data conforming to the destination network data format, including:
the data generating circuit latches the source data read from the data buffer memory according to the latch signal;
and the data generation circuit converts the latched source data into target data according to the bit width of the target network.
Further, the packet header generating circuit further includes: a packet header buffer memory for buffering a source packet header of an original data packet received from the data input interface;
the packet header parser further comprises a packet header input interface and a parser start signal receiving interface, wherein the packet header input interface is connected to the packet header buffer memory, the parser start signal receiving interface is connected to the packet header buffer memory and the data buffer memory through a first logic circuit, and the first logic circuit generates the parser start signal when both the packet header buffer memory and the data buffer memory receive data.
Further, the latch signal generator comprises a latch signal starting interface, a latch signal output interface, a counter and a second logic circuit, wherein the latch signal starting interface is connected with the packet header parser, and the latch signal output interface is connected with the packet header latch circuit and the data generation circuit; the latch signal generator generates the latch signal according to the destination network selection signal, and includes:
the counter starts an input interface through a latch signal to receive the target network selection signal and generate a counting signal;
the second logic circuit generates a latch signal according to the destination network selection signal and the count signal.
In a second aspect, an embodiment of the present disclosure provides a data processing apparatus, including:
a plurality of data processing circuits as claimed in any one of the first aspects.
In a third aspect, an embodiment of the present disclosure provides a data processing method for processing data sent from a source network to a destination network, including:
receiving a raw data packet from the source network, the raw data packet comprising a source packet header and source data;
generating a data control signal and a target packet header according with a target network data format according to the source packet header;
generating target data in accordance with the target network data format according to the data control signal and the source data;
and sending the destination packet header and the destination data to the destination network.
In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including: a memory for storing computer readable instructions; and one or more processors configured to execute the computer-readable instructions, such that the processors when executed implement the data processing method of any of the third aspects.
In a fifth aspect, the disclosed embodiments provide a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute the data processing method of any one of the foregoing third aspects.
In a sixth aspect, the present disclosure provides a computer program product, wherein: comprising computer instructions which, when executed by a computing device, may perform the data processing method of any of the preceding third aspects.
In a seventh aspect, an embodiment of the present disclosure provides a chip, which includes the data processing apparatus described in the second aspect.
In an eighth aspect, an embodiment of the present disclosure provides a computing device, including the chip in the seventh aspect.
The embodiment of the disclosure discloses a data processing circuit, a data processing device and a data processing method. Wherein the data processing circuit comprises: the device comprises a data input interface, a packet header generating circuit, a data buffer memory, a data generating circuit and a data output interface; the data input interface generates a data control signal and a target packet header conforming to a target network data format from a source packet header of an original data packet received from a source network; the data generating circuit takes the source data out of the data buffer memory according to the data control signal and generates target data conforming to the target network data format; and the data output interface sends the destination packet header and the destination data to the destination network. By the method, the technical problems of complex forwarding circuit, high power consumption and large delay in data forwarding between two networks in the prior art are solved.
The foregoing is a summary of the present disclosure, and for the purposes of promoting a clear understanding of the technical means of the present disclosure, the present disclosure may be embodied in other specific forms without departing from the spirit or essential attributes thereof.
Drawings
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that elements and features are not necessarily drawn to scale.
Fig. 1 is a schematic diagram of packet forwarding between buses through a bridge structure in the prior art;
fig. 2 is a schematic diagram of an application scenario of a data processing circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic data processing flow diagram of a data processing apparatus according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a data processing circuit according to an embodiment of the disclosure;
FIG. 6 is a detailed structural diagram of a data processing circuit according to an embodiment of the disclosure;
fig. 7 is a schematic diagram of a generation process of destination data according to an embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.
The names of messages or information exchanged between devices in the embodiments of the present disclosure are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
Fig. 2 is a schematic view of an application scenario of a data processing circuit in an embodiment of the present disclosure. Shown in fig. 2 is a chip including the data processing circuit of the present disclosure. The chip comprises a plurality of processing cores, the plurality of processing cores are divided into a plurality of processing core groups, each processing core group shares one network on chip, all networks on chip use the same protocol, but the data bit width is different, each processing core sharing one network on chip can be either homogeneous or heterogeneous, but the data bit width of the data transmitted by the processing cores is the same. The networks on chip supporting different data bit widths are connected through a data processing device PS (package station) for forwarding data between the networks on chip.
As shown in FIG. 2, KM_CNMThe method comprises the steps of representing a processing core on a chip, wherein M represents the number of a packet in which the processing core is located, namely the number of a network on a chip, and NM (wherein M represents the number of N, namely the Mth N) represents the number of the processing core in the packet, and the processing core can be uniquely located through M and NM. NoCMRepresenting a network on chip, where M represents the number of the network on chip.
Fig. 3 is a schematic diagram illustrating a data processing flow of the data processing apparatus according to the embodiment of the disclosure. As shown in fig. 3, the input of the data processing device PS is connected to each network on chip NoC, the output of the data processing device PS is also connected to each network on chip NoC, and one network on chip is connected to other networks on chip through an internal structure, as shown in fig. 3, a fully connected network is shown, that is, each network on chip is connected to each other network on chip through the data processing device.
Fig. 4 is a schematic structural diagram of a data processing apparatus in an embodiment of the present disclosure. As shown in fig. 4, the data processing apparatus includes a plurality of data processing circuits, a plurality of networks on chip are interconnected by the plurality of data processing circuits in the data processing apparatus, and an example in fig. 4 is that 3 networks on chip are interconnected by 3 data processing circuits of the data processing apparatus, each network on chip being interconnected by the plurality of data processing circuitsThe network corresponding to a fixed data processing circuit, wherein the NoC1Has a data bit width of 16 bits, NoC2Has a data bit width of 32 bits, NoC3Has a data bit width of 64 bits, NoC1Can be converted into data with a bit width of 32 bits by the data processing circuit PG1 of the PS and forwarded to the NoC2Or may be converted into data with a bit width of 64 bits and forwarded to the NoC3. Data transmission between other networks is similar to the above manner, and is not described in detail.
Fig. 5 is a schematic structural diagram of a data processing circuit according to an embodiment of the disclosure. As shown in fig. 5, the data processing circuit 500 includes: a data input interface 501, a packet header generating circuit 502, a data buffer memory 503, a data generating circuit 504, and a data output interface 505; wherein the data input interface 501 is to be slave to a source network NoC1Received original data packet P1Source header H of (1)1To the packet header generation circuit 502; the data input interface 501 is to be slave to a source network NoC1The received original data packet P1Source data D of1To the data buffer 503; the packet header generating circuit generates the packet header according to the source packet header H1Generating data control signals L [1:0 ]]And destination packet header H conforming to destination network data format2Or H3(ii) a The data generation circuit 504 generates the data control signal L [1:0 ]]Fetching the source data D from the data buffer memory1And generating destination data D conforming to the destination network data format2Or D3(ii) a The data output interface 505 sends the destination packet header H to the destination packet header H2Or H3And the destination data D2Or D3To the destination network NoC2Or NoC3。
It is to be understood that, although the data processing circuit shown in fig. 5 includes two data generating circuits and two data output interfaces, in practical applications, the number of the data generating circuits 504 and the data output interfaces 505 corresponds to the number of destination networks, and if the number of destination networks to be connected by the source network is T, the number of the data generating circuits and the data output interfaces is set to T.
Fig. 6 is a detailed structural schematic diagram of a data processing circuit according to an embodiment of the disclosure. Since the structures of the data processing circuits are substantially the same, a description is given in fig. 6 taking a data processing circuit including one data generating circuit 504 as an example. The block diagram shown in fig. 6 corresponds to the specific bit-widths in the above example, i.e., fig. 6 shows a NoC with a bit-width of 16 bits1To 32bit wide NoC2Structure of data processing circuit for transmitting data.
Specifically, as shown in fig. 6, the packet header generating circuit 502 further includes: a packet header parser 601, a packet header latch circuit 602, and a latch signal generator 603; the packet header generating circuit 502 generates a data control signal and a destination packet header conforming to a destination network data format according to the source packet header, and includes: the packet header parser 601 generates a destination network selection signal according to the source packet header; the latch signal generator 603 generates a latch signal according to the destination network selection signal; the packet header latch circuit 602 latches the source packet header according to the latch signal and modifies control information in the source packet header according to the bit width of the destination network to generate the destination packet header. The following table is an exemplary format of the source packet header:
| Ctrl_bit(4bit) | ID_NoC(2bit) | ID_Core(10bit) | Addr_Mem(16bit) |
the control information bit Ctrl _ bit in the source packet header is 4 bits, where the upper two bits indicate how many data packets are in total, and the lower two bits indicate the effective number of bytes in the data packets. The destination address comprises 28 bits, wherein the upper 2 bits represent the ID number of the network on chip, the next 10 bits represent the ID number of the processing core, and the last 16 bits are the storage address of the data.
After receiving the source packet header, the packet header parser 601 parses 2-bit data corresponding to the ID _ NoC, for example, ID _ NoC [0 ]]1 denotes the destination network as NoC2，ID_NoC[1]1 denotes the destination network as NoC3In this example, the ID _ NoC [0 ]]1, or, the ID _ NoC [1 ]]0 denotes the destination network as NoC2. The packet header parser generates a destination network selection signal EN _ NoC according to the source packet header2The latch signal generator receives the EN _ NoC2Then, a latch signal L _ DL is generated, and the packet header latch circuit 602 further includes a packet header latch signal receiving interface for receiving the latch signal to latch the source packet header.
The header generation circuit stores the source header into the header latch circuit after receiving the source header, the header latch circuit latches the source header after receiving the latch signal L _ DL, and the source header received again during the latching period is not latched. The packet header latch circuit modifies control information in the source packet header according to the bit width of the destination network to generate a destination packet header, and since the bit width of the destination network is preset information, the packet header generation circuit can modify control information Ctrl _ bit in the source packet header according to the bit width of the destination network after resolving the ID of the destination network to generate the destination packet header.
Further, the packet header generating circuit 502 further includes: a packet header buffer memory 604 for buffering a source packet header of an original data packet received from the data input interface; the packet header parser further comprises a packet header input interface and a parser start signal receiving interface, wherein the packet header input interface is connected to the packet header buffer memory, the parser start signal receiving interface is connected to the packet header buffer memory and the data buffer memory through a first logic circuit 605, and when both the packet header buffer memory and the data buffer memory receive data, the first logic circuit 605 generates the parser start signal.
As shown in fig. 6, the source packet header is buffered in the packet header buffer memory 604 after being input from the data input interface, and the packet header parser includes two input interfaces and a plurality of output interfaces, wherein one of the input interfaces is a packet header input interface and is connected to the packet header buffer memory; the other input interface is a resolver start signal receiving interface and is connected with the output interface of the first logic circuit 605; the first logic 605 further comprises two input interfaces respectively connected to the header buffer 604 and the data buffer 503, and the first logic 605 generates the parser start signal when there is data in both the header buffer and the data buffer.
Further, the first logic circuit 605 is an and gate circuit, as shown in fig. 6, after the header buffer memory 604 and the data buffer memory 503 receive the source header and the source data of the original data packet, nEH signals and nED signals are generated, respectively, both of which are high level and are input to two input interfaces of the first logic circuit 605, the first logic circuit 605 is an and gate, so that the output signal EN is high level, and the EN signal is the parser start signal, which is input to the parser start signal receiving interface, so that the header parser parses the source header received from the header input interface.
Further, the latch signal generator 603 includes a latch signal enable interface, a latch signal output interface, a counter 606 and a second logic circuit 607, wherein the latch signal enable interface is connected to the packet header parser, and the latch signal output interface is respectively connected to the packet header latch circuit 602 and the data generation circuit; the latch signal generator generates the latch signal according to the destination network selection signal, and includes: the counter 606 receives the destination network selection signal through a latch signal start interface to generate a count signal; the second logic circuit 607 generates a latch signal according to the destination network selection signal and the count signal.
Specifically, as shown in fig. 6, the latch signal generator 603 includes a latch signal generation start interface, which is connected to the output interface of the packet header parser and is used to receive the destination network selection signal sent by the packet header parser, and if the packet header parser parses that the destination network is the network corresponding to the latch signal generator 603, the latch signal generator is triggered to generate the latch signal by setting the corresponding output interface to a high level. After receiving the destination network selection signal, the counter generates a count signal at each clock according to the preset setting, and since the destination network is NoC2, and the data bit width 32bit of NoC2 is twice the data bit width 16bit of NoC1, in the example shown in fig. 6, the counter needs to count two numbers, which generates the signal C in the first clock cycle0Generating the signal C in the second clock cycle1The counter is then reset. The inputs of the second logic circuit are respectively input with the counting signal of the counter and the destination network selection signal, and when both signals are high level, a latch signal is output, and an example of the second logic circuit is an and gate circuit, as shown in fig. 6, since the counter needs to count two numbers, the second logic circuit includes two and gate circuits therein to generate a latch signal L _ DL in a first clock cycle and a latch signal L _ DH in a second clock cycle, where the latch signal L _ DL is used to latch the source packet header in the packet header latch, and in this example, the source packet header is latched for two clock cycles.
Further, the packet header generating circuit 502 further includes: a third logic circuit 608, two input interfaces of the third logic circuit 608 are respectively connected to the data buffer 503 and the packet header parser 601, and an output interface of the third logic circuit is connected to the data buffer 503 and the packet header buffer 604; when a source packet header and source data are received in the data buffer 503 and the packet header buffer 604, respectively, and the packet header parser 601 outputs a destination network selection signal, the third logic 608 outputs a read signal to the data buffer 503 and the packet header buffer 604 to make the data buffer 503 and the packet header buffer 604 readable.
As shown in fig. 6, the third logic circuit is an and gate circuit, and the inputs of the and gate circuit are nED representing the received data in the data buffer memory and the destination network selection signal EN _ NoC respectively2When nED and EN _ NoC2Both are high, the output Rd of the third logic circuit is high, and the Rd signal is output to the data buffer memory 503 and the header buffer memory 604, so that the data buffer memory 503 and the header buffer memory 604 can be read.
Further, the data generating circuit 504 fetches the source data from the data buffer 503 according to the data control signal, and generates destination data conforming to the destination network data format, including: the data generation circuit 504 latches the source data read from the data buffer memory 503 according to the latch signal; the data generating circuit 504 converts the latched source data into destination data according to the bit width of the destination network. Specifically, in the example shown in fig. 6, the NoC1Is a network with 16bit width, the NoC2For a network with a 32-bit width, the data generating circuit needs to combine two 16-bit source data into one 32-bit destination data, and therefore in this example, the data generating circuit includes two latches, D _ L for latching the lower 16 bits of the 32-bit data, and D _ H for latching the upper 16 bits of the 32-bit data. The data generating circuit reads source data from the data buffer memory in a clock cycle in which an Rd signal is effective, reads out one source data from the data buffer memory in a first clock cycle, and latches the source data in the lower 16 bits of the data latch; reading out another source data from the data buffer memory in the second clock cycle, and latching the source data in the high 16 bits of the data latch, wherein the 32-bit data latched in the data latch is NoC2Of the data in one data packet.
In the example shown in fig. 7, the destination data is generated by storing the source data D1 in the data buffer memory, and in two clock cycles, two 16-bit source data are read into the data latches to form 32-bit destination data D2. It is to be understood that, although the above example shows that data is transmitted from a 16-bit-wide network to a 32-bit-wide network, data may actually be transmitted from a network with any bit width to another network with any bit width, and at this time, only the bit width of the data latch and the reading or sending manner of the source data need to be set in advance. The foregoing examples are by way of example only and are not to be construed as limiting the present disclosure.
When data is transmitted from a network with small bit width to a network with large bit width, the packet header generating circuit generates a target packet header by modifying the control information bit of the source packet header. In this case, the storage address in the destination packet header does not need to be modified, and only the storage address in the first source packet header needs to be used to store the lower data in the destination data, and the higher data only needs to be stored sequentially. In one example, the upper two bits of the control information bits of the source packet header represent the total source data number, and the information is as follows:
the lower two bits of the control information bits of the source packet header represent valid byte information in the source data, and the information is as follows:
| Ctrl_bit[1] | Ctrl_bit[0] | |
| 0 | 0 | |
| 0 | 1 | Low byte effective |
| 1 | 0 | High byte effective |
| 1 | 1 | All 2 bytes are valid |
Meanwhile, two higher bits of the control information bits of the destination packet header are the total destination data number, and the information is as follows:
| Ctrl_bit[3] | Ctrl_bit[2] | |
| 0 | 0 | Continuously transmit 4 |
| 0 | 1 | Transmitting only 1 |
| 1 | 0 | Continuously transmit 2 |
| 1 | 1 | Continuously transmit 3 bags |
The lower two bits of the control information bits of the destination header indicate valid byte information in the destination data, and the information is as follows:
| Ctrl_bit[1] | Ctrl_bit[0] | |
| 0 | 0 | |
| 0 | 1 | Low 1 byte valid |
| 1 | 0 | Low 2 bytes effective |
| 1 | 1 | All 4 bytes are valid |
As in the above example, the source network is a network with a bit width of 16 bits, the destination network is a network with a bit width of 32 bits, and if the control information bit in the source packet header indicates that two pieces of source data are continuously transmitted and all bytes in each piece of source data are valid, that is, Ctrl _ bit is '1011', the control information bit in the destination packet header is Ctrl _ bit is '0111', which indicates that only one piece of destination data is present and all 4 bytes in the packet are valid and all need to be transmitted; after the second latch signal, the destination data and the destination header are transmitted.
It can be understood that, when data is transmitted from a network with a large bit width to a network with a small bit width, the packet header generating circuit generates the destination packet header by modifying the control information bit and the storage address of the source packet header. For transmitting data from a large-bit-width network to a small-bit-width network, source data needs to be divided into multiple parts for transmission, for example, data is transmitted from a 32-bit-width network to a 16-bit-width network, and 32-bit source data needs to be divided into two 16-bit destination data, so that in addition to the need for modifying control information bits, a storage address in a destination header needs to be calculated, for a first destination header, the storage address does not need to be modified, the previous storage address is directly used for storing the 16-bit destination data, and for another destination header, an offset of 16 bits is added on the basis of the storage address of the source header to calculate a storage address in a second destination header so as to store the other 16-bit destination data.
It can be understood that, when data is transmitted from a large-bit-width network to a small-bit-width network, the data latch circuit in the data generating circuit has the same bit width as the large-bit-width network, for example, data is transmitted from a 32-bit-width network to a 16-bit-width network, the data latch circuit in the data generating circuit is 32 bits, and reads source data in the data buffer memory into the data latch circuit at one time, and then outputs a 16-bit destination data in each cycle, and at the same time, the packet header generating circuit outputs a corresponding destination packet header.
The embodiment of the present disclosure further provides a data processing method, which includes: receiving a raw data packet from the source network, the raw data packet comprising a source packet header and source data; generating a data control signal and a target packet header according with a target network data format according to the source packet header; generating target data in accordance with the target network data format according to the data control signal and the source data; and sending the destination packet header and the destination data to the destination network.
An embodiment of the present disclosure further provides a data processing apparatus, including: a plurality of data processing circuits as described in any of the above embodiments.
The embodiment of the present disclosure further provides a chip, which includes a plurality of processing core groups, and an on-chip network connected to each processing core group, where the plurality of on-chip networks are connected through the data processing apparatus described in the above embodiment.
The embodiment of the present disclosure provides a computer program product, wherein: comprising computer instructions which, when executed by a computing device, may perform the data processing method of any of the preceding embodiments.
The embodiment of the present disclosure provides a computing device, which is characterized by comprising the chip in any one of the foregoing embodiments.
The flowchart and block diagrams in the figures of the present disclosure illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present disclosure may be implemented by software or hardware. Where the name of an element does not in some cases constitute a limitation on the element itself.
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), systems on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and the like.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Claims (10)
1. A data processing circuit for processing data transmitted from a source network to a destination network, comprising:
the device comprises a data input interface, a packet header generating circuit, a data buffer memory, a data generating circuit and a data output interface;
the data input interface sends a source packet header of an original data packet received from a source network to the packet header generating circuit;
the data input interface sends source data of the original data packet received from a source network to the data buffer memory;
the packet header generating circuit generates a data control signal and a target packet header according with a target network data format according to the source packet header;
the data generating circuit takes the source data out of the data buffer memory according to the data control signal and generates target data conforming to the target network data format;
and the data output interface sends the destination packet header and the destination data to the destination network.
2. A data processing circuit according to claim 1, wherein the source network and the destination network use the same protocol, different bit widths.
3. A data processing circuit according to claim 1 or 2, wherein the data generating circuit and the data output interface are plural, different data generating circuits and data output interfaces corresponding to different destination networks.
4. A data processing circuit according to any of claims 1 to 3, wherein the packet header generating circuit comprises:
the device comprises a packet header parser, a packet header latch circuit and a latch signal generator;
the packet header generating circuit generates a data control signal and a destination packet header conforming to a destination network data format according to the source packet header, and includes:
the packet header analyzer generates a destination network selection signal according to the source packet header;
the latch signal generator generates a latch signal according to the destination network selection signal;
the packet header latch circuit latches the source packet header according to the latch signal and modifies control information in the source packet header according to bit width of a destination network to generate the destination packet header.
5. The data processing circuit of claim 4, wherein the data generation circuit fetches the source data from the data buffer memory according to the data control signal and generates destination data conforming to the destination network data format, comprising:
the data generating circuit latches the source data read from the data buffer memory according to the latch signal;
and the data generation circuit converts the latched source data into the target data according to the bit width of the target network.
6. The data processing circuit of any of claims 1-5, wherein the packet header generation circuit further comprises: a packet header buffer memory for buffering a source packet header of an original data packet received from the data input interface;
the packet header parser further comprises a packet header input interface and a parser start signal receiving interface, wherein the packet header input interface is connected to the packet header buffer memory, the parser start signal receiving interface is connected to the packet header buffer memory and the data buffer memory through a first logic circuit, and the first logic circuit generates the parser start signal when both the packet header buffer memory and the data buffer memory receive data.
7. The data processing circuit of any one of claims 4 to 6, wherein the latch signal generator comprises a latch signal enable interface, a latch signal output interface, a counter and a second logic circuit, wherein the latch signal enable interface is connected to the packet header parser, and the latch signal output interface is connected to the packet header latch circuit and the data generation circuit, respectively; the latch signal generator generates the latch signal according to the destination network selection signal, and includes:
the counter starts an input interface through a latch signal to receive the target network selection signal and generate a counting signal;
the second logic circuit generates the latch signal according to the destination network selection signal and the count signal.
8. A data processing apparatus, comprising:
a plurality of data processing circuits according to any of claims 1-7.
9. A chip comprising a plurality of groups of processing cores, a network on chip connected to each of said groups of processing cores, a plurality of said networks on chip being connected by the data processing apparatus of claim 8.
10. A data processing method for processing data transmitted from a source network to a destination network, comprising:
receiving a raw data packet from the source network, the raw data packet comprising a source packet header and source data;
generating a data control signal and a target packet header according with a target network data format according to the source packet header;
generating target data in accordance with the target network data format according to the data control signal and the source data;
and sending the destination packet header and the destination data to the destination network.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911148502.8A CN112825065A (en) | 2019-11-21 | 2019-11-21 | Data processing circuit, apparatus and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911148502.8A CN112825065A (en) | 2019-11-21 | 2019-11-21 | Data processing circuit, apparatus and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112825065A true CN112825065A (en) | 2021-05-21 |
Family
ID=75907348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911148502.8A Pending CN112825065A (en) | 2019-11-21 | 2019-11-21 | Data processing circuit, apparatus and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112825065A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431806A (en) * | 2003-02-14 | 2003-07-23 | 清华大学 | Network processor system for supporting QoS based on FPGA and data packages processing method |
| CN1467956A (en) * | 2002-07-12 | 2004-01-14 | 华为技术有限公司 | Method for converting packet mode data from high-bit width format to low-bit width format using frame alignment |
| CN1633105A (en) * | 2004-12-09 | 2005-06-29 | 上海交通大学 | Method for implementing packing and unpacking of giga optical Ethernet label switching network |
| CN103748842A (en) * | 2013-06-26 | 2014-04-23 | 华为技术有限公司 | Method, device and route device for forwarding data packages |
| WO2014117688A1 (en) * | 2013-01-30 | 2014-08-07 | 华为技术有限公司 | Data transmission method and related apparatus |
| WO2014146468A1 (en) * | 2013-03-21 | 2014-09-25 | 中兴通讯股份有限公司 | Method and apparatus for scheduling and buffering data packet, and computer storage medium |
| JP2016178494A (en) * | 2015-03-20 | 2016-10-06 | 株式会社Ｎｔｔドコモ | Gateway device and communication method |
| CN109218301A (en) * | 2018-09-05 | 2019-01-15 | 天津市滨海新区信息技术创新中心 | The method and apparatus of the frame head mapping of software definition between multi-protocols |
| WO2019178264A1 (en) * | 2018-03-14 | 2019-09-19 | Fungible, Inc. | Flexible processing of network packets |
-
2019
- 2019-11-21 CN CN201911148502.8A patent/CN112825065A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1467956A (en) * | 2002-07-12 | 2004-01-14 | 华为技术有限公司 | Method for converting packet mode data from high-bit width format to low-bit width format using frame alignment |
| CN1431806A (en) * | 2003-02-14 | 2003-07-23 | 清华大学 | Network processor system for supporting QoS based on FPGA and data packages processing method |
| CN1633105A (en) * | 2004-12-09 | 2005-06-29 | 上海交通大学 | Method for implementing packing and unpacking of giga optical Ethernet label switching network |
| WO2014117688A1 (en) * | 2013-01-30 | 2014-08-07 | 华为技术有限公司 | Data transmission method and related apparatus |
| WO2014146468A1 (en) * | 2013-03-21 | 2014-09-25 | 中兴通讯股份有限公司 | Method and apparatus for scheduling and buffering data packet, and computer storage medium |
| CN103748842A (en) * | 2013-06-26 | 2014-04-23 | 华为技术有限公司 | Method, device and route device for forwarding data packages |
| JP2016178494A (en) * | 2015-03-20 | 2016-10-06 | 株式会社Ｎｔｔドコモ | Gateway device and communication method |
| WO2019178264A1 (en) * | 2018-03-14 | 2019-09-19 | Fungible, Inc. | Flexible processing of network packets |
| CN109218301A (en) * | 2018-09-05 | 2019-01-15 | 天津市滨海新区信息技术创新中心 | The method and apparatus of the frame head mapping of software definition between multi-protocols |
Non-Patent Citations (2)
| Title |
|---|
| 宋仕坤: ""基于以太网MAC IP核的IEEE1588协议的设计与实现"", 《中国优秀硕士学位论文全文数据库（电子期刊）》, no. 2018, 15 April 2018 (2018-04-15) * |
| 肖寅东;王厚军;田书林;: "高速网络入侵检测系统中包头解析方法", 仪器仪表学报, no. 06, 15 June 2012 (2012-06-15) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2668577B1 (en) | Unrolling quantifications to control in-degree and/or out degree of automaton | |
| KR101642086B1 (en) | High performance interconnect link layer | |
| US8514889B2 (en) | Use of common data format to facilitate link width conversion in a router with flexible link widths | |
| CN103559156B (en) | Communication system between a kind of FPGA and computing machine | |
| JP2001229172A (en) | Device and system for data processing using table | |
| WO2024007787A1 (en) | Model training system, model training method, and apparatus | |
| WO2020224380A1 (en) | Blockchain-based data processing method and device | |
| Suhaib et al. | Dataflow architectures for GALS | |
| CN112825065A (en) | Data processing circuit, apparatus and method | |
| CN107918589B (en) | High-efficient buffer memory concurrency system of DMX512 signal based on FPGA | |
| CN116166602A (en) | SPI-based SSI protocol data receiving method and system | |
| CN116186096A (en) | Relational database aggregation query method, device, equipment and medium based on FPGA | |
| Klilou et al. | Performance optimization of high-speed Interconnect Serial RapidIO for onboard processing | |
| CN112866180B (en) | Data processing circuit, apparatus and method | |
| CN102130744A (en) | Method and device for computing Cyclic Redundancy Check (CRC) code | |
| Kim et al. | Compression accelerator for hadoop appliance | |
| US8782164B2 (en) | Implementing asyncronous collective operations in a multi-node processing system | |
| KR20240046830A (en) | On-demand packetization for chip-to-chip interfaces | |
| Oukaira et al. | New architecture for real-time image computing using parallel processing based on DSP/FPGA | |
| JP2014194619A (en) | Buffer circuit and semiconductor integrated circuit | |
| JPH0479422A (en) | Transmission control circuit | |
| CN104331385A (en) | High-speed semi-hardware realization method for serial peripheral interface | |
| Charaabi et al. | Designing a tiny and customizable TCP/IP core for low cost FPGA | |
| WO2023036194A1 (en) | Data transmission method, electronic system, and storage medium | |
| Huang et al. | FPGA-based HDLC Controller Design and Communication Implementation in Normal Response Mode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |