CN112866180B - Data processing circuit, apparatus and method - Google Patents

Data processing circuit, apparatus and method Download PDF

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CN112866180B
CN112866180B CN201911187841.7A CN201911187841A CN112866180B CN 112866180 B CN112866180 B CN 112866180B CN 201911187841 A CN201911187841 A CN 201911187841A CN 112866180 B CN112866180 B CN 112866180B
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data
target
packet
source
network
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CN112866180A (en
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不公告发明人
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Guangzhou Ximu Semiconductor Technology Co ltd
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Beijing Simm Computing Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/565—Conversion or adaptation of application format or content
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The embodiment of the disclosure discloses a data processing circuit, a data processing device and a data processing method. Wherein the data processing circuit comprises: the device comprises a data input interface, a data packet analyzing circuit, a data packet generating circuit and a data output interface; the data input interface sends an original data packet received from a source network to the data packet analysis circuit; the data packet analyzing circuit analyzes the source packet header in the original data packet to obtain broadcast control information; the data packet analysis circuit sends the original data packet to a data packet generation circuit according to broadcast control information, and the data packet generation circuit generates a target packet header and target data according to the corresponding target network; and the data output interface sends the target packet header and the target data to the corresponding target network. By the method, the technical problems of occupation of extra processing cores, increase of power consumption and increase of delay when data are broadcast between networks on chip in the prior art are solved.

Description

Data processing circuit, apparatus and method
Technical Field
The present disclosure relates to the field of data processing, and in particular, to a data processing circuit, apparatus, and method.
Background
With the development of science and technology, the human society is rapidly entering the intelligent era. The chip is a fundamental stone of data processing and fundamentally determines the capability of people for processing data. From the application field, the chip mainly has two routes: one is a general chip route, such as a CPU (Central Processing Unit), which provides great flexibility but is less computationally efficient in Processing domain-specific algorithms; the other is a special chip route, such as TPU (Tensor Processing Unit), which can exert higher effective computing power in some specific fields, but has poorer or even no Processing capability in the more versatile and versatile fields. Because the data of the intelligent era is various and huge in quantity, the chip is required to have extremely high flexibility, can process algorithms in different fields and in different days, has extremely high processing capacity, and can rapidly process extremely large and sharply increased data volume.
In the existing chip, multiple NoCs (network-on-c)hip, network on chip) can be connected through a Bridge, wherein a Bridge is a connecting component of two or more nocs, and converts a data format on one NoC into a data format on another NoC or multiple nocs, so as to complete the functions of data format conversion and forwarding. However, when data needs to be broadcast, only broadcasting of the data in one NoC can be achieved, and data in one NoC cannot be broadcast to other nocs with different bit widths or protocols at the same time. When data needs to be broadcasted to different nocs, the data must be transmitted to a processing core of a different destination NoC, and the processing core receives the data and then broadcasts the data in the NoC. FIG. 1 illustrates a prior art scheme for broadcasting data between multiple NoCs, such as from the NoC if data is needed1K of1_C1Processing core to NoC1And NoC2All processing cores of (1), then K1_C1Will broadcast data to the NoC1All cores in (1), paths such as NoC1And then send the data to the NoC, as indicated by the dashed arrow in2K in (1)2_C1Processing cores, e.g. from K1_C1To K2_C1Is shown by the arrow; NoC2K in (1)2_C1The data is then broadcast to all cores in the NoC2, the path being shown by the dashed arrows in the NoC 2. Through the prior art, data in the prior art can only be broadcasted to the processing core in the NoC, and if the NoC needs to be crossed, the processing cores in other nocs need to participate, and the processing cores in other nocs, which participate in the broadcasting, are occupied; because the data needs to be sent by the source processing core twice, the data is broadcasted to the processing core in the NoC once and is sent to the processing core in another NoC once, and the power consumption is increased; the processing core of the other NoC participating in the broadcast needs to receive the data first and then broadcast the data, so that the delay is increased.
Disclosure of Invention
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
In order to solve the technical problems of occupation of an additional processing core, increase of power consumption and increase of delay when data is broadcast between NoCs in the prior art, the embodiment of the present disclosure provides the following technical solutions:
in a first aspect, an embodiment of the present disclosure provides a data processing circuit, configured to process data sent from a source network to a destination network, where the data processing circuit includes:
the device comprises a data input interface, a data packet analyzing circuit, a data packet generating circuit and a data output interface;
the data input interface sends an original data packet received from a source network to the data packet analysis circuit;
the data packet analyzing circuit analyzes a source packet header in the original data packet to obtain broadcast control information, wherein the broadcast control information comprises information of a target network;
the data packet analyzing circuit sends the source packet header and the source data of the original data packet to a target data packet generating circuit according to broadcast control information, the target data packet generating circuit is at least one of the data packet generating circuits, and the target data packet generating circuit corresponds to a target network indicated by the information of the target network;
the target data packet generating circuit generates a target packet header and target data according to the corresponding target network;
and the data output interface sends the target packet header and the target data to the corresponding target network.
Further, the packet generation circuit includes: a packet header generating circuit and a data generating circuit;
the data packet analyzing circuit sends the source packet header and the source data of the original data packet to the target data packet generating circuit, and the data packet analyzing circuit comprises:
the data packet analysis circuit sends the source packet header to a target packet header generation circuit in the target data packet generation circuit;
and the data packet analyzing circuit sends the source data to a target data generating circuit in the target data packet generating circuit.
Further, the generating circuit of the target data packet generates a target packet header and target data according to the corresponding target network, including:
the target packet header generating circuit generates data control information and the target packet header according to the corresponding target network;
the target data generation circuit converts the source data into the target data supported by the corresponding target network according to the data control information and the corresponding target network.
Further, the data processing circuit further includes: the input interface of the source data buffer memory is connected with the output interface of the data packet parser, and the output interface of the source data buffer memory is connected with the input interface of the data generation circuit;
the target data generation circuit converts the source data into the target data supported by the corresponding target network according to the data control information and the corresponding target network, and includes:
the target data generating circuit reads source data from the source data buffer memory according to the data control information;
the target data generation circuit converts the source data into the target data conforming to a protocol of a target network according to the protocol of the target network.
Further, the data processing circuit further comprises: the input interface of the data packet buffer memory is connected with the data input interface, and the output interface of the data packet buffer memory is connected with the input interface of the data packet analyzer; the data input interface sends the original data packet received from a source network to the data packet parsing circuit, and comprises:
the data input interface sends the original data packet received from a source network to the data packet buffer memory;
the data packet buffer memory generates a starting signal of the data packet parser;
in response to receiving the initiation signal, the packet parser reads the original packet from the packet buffer memory.
Furthermore, the number of the data packet generating circuits and the number of the data output interfaces are multiple, and different data packet generating circuits and different data output interfaces correspond to different target networks.
Further, the broadcast control information includes: a broadcast control bit for indicating whether to broadcast source data; a target address bit to indicate the target network.
In a second aspect, an embodiment of the present disclosure provides a data processing apparatus, including:
a plurality of data processing circuits as described in any of the first aspects.
In a third aspect, an embodiment of the present disclosure provides a data processing method for processing data sent from a source network to a destination network, including:
receiving a raw data packet from the source network, the raw data packet comprising a source packet header and source data;
analyzing the broadcast control information in the source packet header;
generating a target packet header and target data according to the information of the target network in the broadcast control information;
and sending the target packet header and the target data to the target network.
In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including: a memory for storing computer readable instructions; and one or more processors for executing the computer readable instructions, such that the processors when executed implement the data processing method of any of the third aspect.
In a fifth aspect, the disclosed embodiments provide a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute the data processing method of any one of the foregoing third aspects.
In a sixth aspect, the disclosed embodiments provide a computer program product, wherein: comprising computer instructions which, when executed by a computing device, may perform the data processing method of any of the preceding third aspects.
In a seventh aspect, an embodiment of the present disclosure provides a chip, which includes the data processing apparatus described in the second aspect.
In an eighth aspect, an embodiment of the present disclosure provides a computing device, including the chip in the seventh aspect.
The embodiment of the disclosure discloses a data processing circuit, a data processing device and a data processing method. Wherein the data processing circuit comprises: the device comprises a data input interface, a data packet analyzing circuit, a data packet generating circuit and a data output interface; the data input interface sends an original data packet received from a source network to the data packet analysis circuit; the data packet analyzing circuit analyzes the source packet header in the original data packet to obtain broadcast control information; the data packet analysis circuit sends the original data packet to a data packet generation circuit according to broadcast control information, and the data packet generation circuit generates a target packet header and target data according to the corresponding target network; and the data output interface sends the target packet header and the target data to the corresponding target network. By the method, the technical problems of occupation of extra processing cores, increase of power consumption and increase of delay when data are broadcast between networks on chip in the prior art are solved.
The foregoing is a summary of the present disclosure, and for the purposes of promoting a clear understanding of the technical means of the present disclosure, the present disclosure may be embodied in other specific forms without departing from the spirit or essential attributes thereof.
Drawings
The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that elements and features are not necessarily drawn to scale.
Fig. 1 is a schematic data flow diagram of broadcast data between nocs in the prior art;
fig. 2 is a schematic diagram of an application scenario of a data processing circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic data processing flow diagram of a data processing apparatus according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a data processing circuit according to an embodiment of the disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.
The names of messages or information exchanged between devices in the embodiments of the present disclosure are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
Fig. 2 is a schematic view of an application scenario of a data processing circuit in an embodiment of the present disclosure. Shown in fig. 2 is a chip including the data processing circuit of the present disclosure. The chip comprises a plurality of processing cores, the processing cores are divided into a plurality of processing core groups, each processing core in one processing core group shares one network on chip, all networks on chip can use the same protocol or different protocols, data bit widths can be the same or different, each processing core in a processing core group can be isomorphic or heterogeneous, but the data bit widths of data transmitted by the processing cores are the same. The plurality of networks on chip are connected by a data processing means Bridge for forwarding data between the plurality of networks on chip.
As shown in FIG. 2, KM_CNMThe method comprises the steps that a processing core on a chip is represented, wherein M represents the number of a group where the processing core is located, namely the number of a network on the chip, NM (M represents the number of N, namely the Mth N) represents the number of the processing core in the group, and the processing core can be uniquely located through M and NM. NocMRepresenting a network on chip, where M represents the number of the network on chip.
Fig. 3 is a schematic diagram illustrating a data processing flow of a data processing apparatus (Bridge) according to an embodiment of the present disclosure. As shown in fig. 3, the input of the data processing apparatus is connected to each network on chip NoC, the output of the data processing apparatus is also connected to each network on chip NoC, and one network on chip is connected to other networks on chip through internal structures, and as shown in fig. 3, the data processing apparatus is a fully connected network, that is, each network on chip is connected to each other network on chip through the data processing apparatus. The data processing apparatus performs format conversion of a data packet when data is transmitted from one network on chip to another network on chip.
Fig. 4 is a schematic structural diagram of a data processing apparatus in an embodiment of the present disclosure. As shown in fig. 4, the data processing apparatus includes a plurality of data processing circuits, a plurality of networks on chip are interconnected by the plurality of data processing circuits in the data processing apparatus, and an example in fig. 4 is that 3 networks on chip are interconnected by 3 data processing circuits of the data processing apparatus, each network on chip corresponds to a fixed data processing circuit PG, wherein NoC1Corresponding PG1，NoC2Corresponding PG2，NoC3Corresponding PG3。NoC1Data packet IP of1By PG1Is converted into OP12To NoC2Is converted into OP13Sending pending NoC3Data forwarding and NoC for other networks on chip1Similarly, no further description is provided herein.
Fig. 5 is a schematic structural diagram of a data processing circuit according to an embodiment of the disclosure. As shown in fig. 5, the data processing circuit 500 includes: a data input interface 501, a data packet analyzing circuit 502, a data packet generating circuit 503 and a data output interface 504; the data input interface 501 sends the original data packet IP1 received from the source network NoC1 to the data packet parsing circuit 502; the data packet parsing circuit 502 parses a source packet header in the original data packet IP1 to obtain broadcast control information, where the broadcast control information includes information of a target network; the packet parsing circuit sends the source packet header and the source data of the original packet IP1 to a target packet generating circuit according to broadcast control information, the target packet generating circuit is at least one of the packet generating circuits 503, and the target packet generating circuit and the target networkTarget network (NoC) indicated by network information1And/or NoC2) Corresponding; the destination packet generation circuit generates a destination packet according to the corresponding destination network (NoC)1And/or NoC2) Generating a target packet header (H1 and/or H2) and target data (D1 and/or D2); the data output interface 504 sends the target packet header (H1 and/or H2) and the target data (D1 and/or D2) to the corresponding target network (NoC)1And/or NoC2)。
It is to be understood that the target packet generating circuit is one or more of a plurality of packet generating circuits, which are data generating circuits corresponding to a target network determined according to the information of the target network, and for example, if the information of the target network indicates that the target network is NoC2, the target packet generating circuit is a packet generating circuit corresponding to NoC 2.
It is to be understood that, although the data processing circuit shown in fig. 5 includes two data packet generating circuits 503 and two data output interfaces 504, in practical applications, the number of the data packet generating circuits 503 and the number of the data output interfaces 504 correspond to the number of the target networks, and if the number of the target networks to be connected by the source network is T, the number of the data packet generating circuits and the number of the data output interfaces are set to T.
Further, as shown in fig. 5, the packet generating circuit 503 further includes: a packet header generating circuit 505 and a data generating circuit 506; the data packet parsing circuit 502 sends the source packet header and the source data of the original data packet to the target data packet generating circuit, including: the packet parsing circuit 502 sends the source packet header to a target packet header generating circuit 505 in the target packet generating circuit; the packet parsing circuit 502 sends the source data to a destination data generating circuit 506 in the destination packet generating circuit. In this embodiment, the packet parsing circuit 502 receives the packet IP1, and decomposes the packet into a source packet header and source data. Since each data processing circuit corresponds to a fixed source network, the data processing circuit knows the data packet structure of the source network, for example, the original data packet of the source network includes a 32-bit packet header and 64-bit data, the data packet parsing circuit 502 sends the first 32-bit data in the original data packet as the source packet header to the target packet header generating circuit 505, and sends the remaining data in the original data packet as the source data to the target data generating circuit 506 according to the known structure of the data packet of the source network in advance. It is understood that the target packet header generating circuit and the target data generating circuit are a packet header generating circuit and a data generating circuit in a data packet generating circuit corresponding to the target network.
Further, the generating circuit of the target data packet generates a target packet header and target data according to the corresponding target network, including: the target packet header generating circuit 505 generates data control information and the target packet header according to the corresponding target network; the target data generation circuit converts the source data into the target data supported by the corresponding target network according to the data control information and the corresponding target network. For the data processing circuit, each data packet generating circuit corresponds to a unique target network, so the target packet header generating circuit knows the data format of the target network in advance, and after receiving the source packet header, generates data control information to control the target data generating circuit to generate the target data supported by the target network, and the target packet header generating circuit itself can generate the target packet header supported by the target network.
Illustratively, the data control information may be latch information, and assuming that the data bit width of the source network is 16 bits and the data bit width of the target network is 32 bits, the data control information controls the target data generation circuit to read one 16-bit source data per cycle, so as to obtain two 16-bit source data for two cycles in total, and then combine the two 16-bit source data into one 32-bit target data; similarly, the target packet header is modified according to the source packet header by the target network, for example, the packet header may include an indication bit indicating how much valid data is in the data packet, and since the target network is 32-bit wide, it is necessary to indicate that the valid data is 32-bit, and it is necessary to modify the valid bit 16-bit in the source packet header to 32-bit. It can be understood that the above examples of generating the target packet header and the target data are only examples, and do not constitute a limitation to the present disclosure, and actually, according to the actual situation of the network, any conversion may be performed on the source packet header and the source data to generate the target packet header and the target data supported by the target network, and details are not described here again.
Further, as shown in fig. 5, the data processing circuit further includes: a source data buffer memory 507, an input interface of the source data buffer memory 507 being connected to an output interface of the packet parser, and an output interface of the source data buffer memory 507 being connected to an input interface of the data generation circuit 506; the target data generation circuit converts the source data into the target data supported by the corresponding target network according to the data control information and the corresponding target network, and includes: the target data generating circuit reads source data from the source data buffer memory according to the data control information (C2, C3); the target data generation circuit converts the source data into the target data conforming to a protocol of a target network according to the protocol of the target network. The source data buffer memory is configured to buffer a plurality of source data parsed from the packet parser, and the destination data generating circuit reads the source data from the source data buffer according to data control information, for example, the data control information may be a data latch signal including a plurality of data latch signals, and the data latch signals are respectively valid in different periods so that the destination data generating circuit can latch the plurality of source data; for example, the data control information may be a data latch signal and a read signal, which include one data latch signal and a plurality of read signals, wherein the one data latch signal is valid for a plurality of periods, and the plurality of read signals are valid for the plurality of periods, respectively. The target data generating circuit converts the source data into target data according to the width of data specified in a protocol of a target network, wherein the bit width of the target data may be larger than the bit width of the source data or smaller than the bit width of the source data.
Further, as shown in fig. 5, the data processing circuit further includes: a packet buffer 508, an input interface of the packet buffer 508 is connected to the data input interface 501, and an output interface of the packet buffer 508 is connected to an input interface of the packet parsing circuit 502; the data input interface 501 sends the original data packet received from the source network to the data packet parsing circuit 502, including: the data input interface 501 sends the original data packet received from the source network into the data packet buffer 508; the packet buffer 508 generates an enable signal for the packet parser circuit 502; in response to receiving the activation signal, the packet parsing circuit 502 reads the original packet from the packet buffer 508. In this embodiment, the data processing circuit further includes a packet buffer memory configured to buffer an original packet, and when the original packet of a source network is received in the packet buffer memory, the packet buffer memory generates an initiation signal of a packet parser, and when the packet parser receives the initiation signal, the packet parser starts to read the original packet from the packet buffer memory to parse the original packet into a source packet header and source data, and sends the source packet header and the source data to a packet generation circuit of a target network corresponding to network information in broadcast control information in the source packet header.
With the circuit configuration shown in fig. 5, the forwarding process of the data packet from the source network to the target network is described as follows:
when a data processing circuit receives a packet IP1 of the NoC1, the packet IP1 is first buffered in a packet buffer memory, and at this time, a packet parser detects that there is data in the buffered packet buffer memory or receives a signal that there is data in the packet buffer memory, and the packet parser is started to parse the original packet to obtain broadcast control information in a source packet, where the broadcast control information indicates whether broadcasting is needed and the target network.
If the broadcast control information indicates that the broadcast data is not needed and only the data needs to be sent to a certain processing core of a certain NoC, the data packet parser sends the source packet header to a target packet header generation circuit corresponding to a target network and sends the source data to a source data buffer memory corresponding to the target network; and then the target packet header generating circuit generates a target packet header, generates data control information to control the target data generating circuit to read the source data from the source data buffer memory and generate target data, and then sends the target packet header and the target data to a target network, and the target network forwards the target data to a corresponding processing core according to processing core information in the target packet header.
If the broadcast control information indicates that the data needs to be broadcast, the data packet parser sends the source packet headers to a target packet header generating circuit corresponding to one or more target networks, and sends the source data to a source data buffer memory corresponding to the one or more target networks, then the one or more target packet header generating circuits respectively generate one or more target packet headers and respectively generate the data control information to control the one or more target data generating circuits to read the source data from the source data buffer memory corresponding to the one or more target data generating circuits and generate the target data, and then the target packet headers and the target data are sent to the corresponding target networks. The target network broadcasts the target data in the target network after receiving the target packet header and the target data. Illustratively, after the target data generating circuit generates target data, it also sends acknowledgement information (r2 and/or r3) to the target packet header generating circuit to make the target packet header generating circuit send a target packet header matching the target data to the data output interface.
Further, the broadcast control information includes: a broadcast control bit for indicating whether to broadcast source data; a target address bit to indicate the target network. Illustratively, the data format of the source packet header is defined as follows:
Figure BDA0002292830340000091
Figure BDA0002292830340000101
the packet header comprises a Reserved bit Reserved (1bit), a control information bit Ctrl _ bit (2bit), a target network bit destNoC (3bit), a target processing core ID bit (10bit) and a storage address bit (16bit), wherein the broadcast control information comprises the control information bit Ctrl _ bit (2bit) and a target network bit destNoC (3bit), the control information bit Ctrl _ bit (2bit) is used for indicating whether to broadcast source data, and the target network bit destNoC (3bit) indicates a target network. Three networks on chip are included in the example.
Further, the data packet parsing circuit sends the source packet header and the source data of the original data packet to a target data packet generating circuit according to broadcast control information, and the method includes: responding to the broadcast control information to indicate that the source data does not need to be broadcast, and sending the source packet header and the source data to a target data packet generating circuit corresponding to a target network indicated by the target address bit; the target packet header comprises target network broadcast control information indicating that the target data does not need to be broadcast in a target network and target processing core address information of the target data; responding to the broadcast control bit to indicate that source data needs to be broadcast, and sending the source packet header and the source data to a target data packet generating circuit corresponding to a target network indicated by the target address bit; and the target packet header comprises target network broadcast control information indicating that the target data is broadcast in a target network.
Specifically, the control information bits are the broadcast control bits. If its low bit29 is 0, it indicates that the source data does not need to be broadcast; if bit29 is 1, it indicates that the source data needs to be broadcast. The packet parser checks this bit to determine if the source data needs to be processedAnd (5) broadcasting. Of the 3 bits of the target network bits (bit26, bit27, and bit28), bit26 would be ignored by the packet parser, which is for the NoC1Internal broadcast control bit, bit27 corresponds to the target NoC2Bit28 corresponds to a target NoC3. When the source data does not need broadcasting, the 2 target network information bits (Bit 27 and Bit28) have corresponding bits and only one Bit is '1', which indicates that the source data needs to be sent to the NoC corresponding to the target network Bit with the value of '1'; when source data needs to be broadcast, only one bit of the 2 target network bits may be '1', or both bits may be '1', indicating that the source data needs to be sent to the NoC corresponding to the target network bit with the value of '1' and broadcast.
The source packet header is followed by a target processing core ID bit (10bit) and a storage address bit (16bit), if the source data needs to be broadcast, the target processing core ID bit (10bit) is meaningless, so the source data can be sent to all processing cores in the target network, and the storage address is an address indicating that the target data is finally stored in the memory.
The process of broadcasting source data to a target network is illustratively described in terms of the source packet header described above. Such as NoC1One of the processing cores needs to broadcast data to all of the processing cores, i.e., the NoC1、NoC2And NoC3And if all the processing cores are used, the processing core is marked as a sending processing core, the sending processing core needs to set bit29 in the source packet header to be 1, and all three bits of the destination network bit destNoC to be 1. NoC when the sending processing core sends a data packet1And detecting bit29 and bit26, and if both bits are 1, sending the source data in the data packet to the NoC1Said data processing apparatus being considered to be a NoC1The data processing device also receives the data packet, and a packet parser in the data processing device parses the data packet to obtain a source packet header, continues to detect Bit29, Bit27, and Bit28, and finds that the source data needs to be broadcast to the NoC2And NoC3The packet parser sends the source data to the NoC2And NoC3Sending the source packet header to the NoC in the corresponding source data buffer2And NoC3In a corresponding target packet header generating circuit, the target packet header generating circuit generates a target packet header according to a target network, and generates corresponding data control information to control a target data generating circuit to take out source data from the source data buffer memory, the target data generating circuit converts the source data into target data, and then the data packet generating circuit sends the target packet header and the target data to the target network, wherein the target packet header includes information indicating that the target data needs to be broadcast in the target network, such as information sent to a NoC2The control information indicates that the target data is in the NoC, where bit29 is 1, bit27 is 1, bit26 is 0, and bit28 is 02The target network broadcast control information. Thus, the data transmission of the data packet from the source network to the target network can be controlled by the data processing circuit and the setting of the broadcast control information in the source packet header, and the data can be directly broadcast from one sending processing core to all other processing cores in the processor.
The embodiment of the present disclosure further provides a data processing method, which includes: receiving a raw data packet from the source network, the raw data packet comprising a source packet header and source data; analyzing the broadcast control information in the source packet header; generating a target packet header and target data according to the information of the target network in the broadcast control information; and sending the target packet header and the target data to the target network.
An embodiment of the present disclosure further provides a data processing apparatus, including: a plurality of data processing circuits as described in any of the above embodiments.
The embodiment of the present disclosure further provides a chip, which includes a plurality of processing core groups, and an on-chip network connected to each processing core group, where the plurality of on-chip networks are connected through the data processing apparatus described in the above embodiment.
The embodiment of the present disclosure provides a computer program product, wherein: comprising computer instructions which, when executed by a computing device, may perform the data processing method of any of the preceding embodiments.
The embodiment of the present disclosure provides a computing device, which is characterized by comprising the chip in any one of the foregoing embodiments.
The flowchart and block diagrams in the figures of the present disclosure illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present disclosure may be implemented by software or hardware. Where the name of an element does not in some cases constitute a limitation on the element itself.
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and the like.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Claims (10)

1. A data processing circuit for processing data transmitted from a source network to a target network, comprising:
the device comprises a data input interface, a data packet analyzing circuit, a data packet generating circuit and a data output interface;
the data input interface sends an original data packet received from a source network to the data packet analysis circuit;
the data packet analyzing circuit analyzes a source packet header in the original data packet to obtain broadcast control information, wherein the broadcast control information comprises information of a target network;
the data packet analyzing circuit sends the source packet header and the source data of the original data packet to a target data packet generating circuit according to broadcast control information, the target data packet generating circuit is at least one of the data packet generating circuits, and the target data packet generating circuit corresponds to a target network indicated by the information of the target network;
the target data packet generating circuit generates a target packet header and target data according to the corresponding target network;
the data output interface sends the target packet header and the target data to the corresponding target network; wherein the source network and the target network are both networks on chip.
2. The data processing circuit of claim 1, wherein the packet generation circuit comprises: a packet header generating circuit and a data generating circuit;
the data packet analyzing circuit sends the source packet header and the source data of the original data packet to the target data packet generating circuit, and the data packet analyzing circuit comprises:
the data packet analysis circuit sends the source packet header to a target packet header generation circuit in the target data packet generation circuit;
and the data packet analyzing circuit sends the source data to a target data generating circuit in the target data packet generating circuit.
3. The data processing circuit of claim 2, wherein the destination packet generation circuit generates a destination packet header and destination data from the corresponding destination network, comprising:
the target packet header generating circuit generates data control information and the target packet header according to the corresponding target network;
the target data generation circuit converts the source data into the target data supported by the corresponding target network according to the data control information and the corresponding target network.
4. The data processing circuit of claim 3, wherein the data processing circuit further comprises: the input interface of the source data buffer memory is connected with the output interface of the data packet parser, and the output interface of the source data buffer memory is connected with the input interface of the data generation circuit;
the target data generation circuit converts the source data into the target data supported by the corresponding target network according to the data control information and the corresponding target network, and includes:
the target data generating circuit reads source data from the source data buffer memory according to the data control information;
the target data generation circuit converts the source data into the target data conforming to a protocol of a target network according to the protocol of the target network.
5. The data processing circuit of any of claims 1-4, wherein the data processing circuit further comprises: the input interface of the data packet buffer memory is connected with the data input interface, and the output interface of the data packet buffer memory is connected with the input interface of the data packet analyzer; the data input interface sends the original data packet received from a source network to the data packet parsing circuit, and comprises:
the data input interface sends the original data packet received from a source network to the data packet buffer memory;
the data packet buffer memory generates a starting signal of the data packet parser;
in response to receiving the initiation signal, the packet parser reads the original packet from the packet buffer memory.
6. A data processing circuit according to any one of claims 1 to 4, wherein the packet generation circuit and the data output interface are plural, different packet generation circuits and data output interfaces corresponding to different destination networks.
7. The data processing circuit of any of claims 1-4, wherein the broadcast control information comprises: a broadcast control bit for indicating whether to broadcast source data; a target address bit to indicate the target network.
8. A data processing apparatus, comprising:
a plurality of data processing circuits according to any of claims 1-7.
9. A chip comprising a plurality of groups of processing cores, a network on chip connected to each group of processing cores, the plurality of networks on chip being connected to each other by the data processing apparatus according to claim 8.
10. A data processing method for processing data transmitted from a source network to a target network, comprising:
receiving a raw data packet from the source network, the raw data packet comprising a source packet header and source data;
analyzing the broadcast control information in the source packet header, wherein the information of the target network in the broadcast control information comprises: a target address bit to indicate the target network; a target processing core ID bit to indicate the ID of a target processing core in a target network;
generating a target packet header and target data according to the information of the target network in the broadcast control information;
sending the target packet header and the target data to the target network, so that the target network broadcasts the target data to the target processing core in the target network according to the target packet header after receiving the target packet header and the target data; wherein the source network and the target network are both networks on chip.
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