CN117037880A - Optimal design circuit of hardware destruction circuit of solid state disk - Google Patents
Optimal design circuit of hardware destruction circuit of solid state disk Download PDFInfo
- Publication number
- CN117037880A CN117037880A CN202311040275.3A CN202311040275A CN117037880A CN 117037880 A CN117037880 A CN 117037880A CN 202311040275 A CN202311040275 A CN 202311040275A CN 117037880 A CN117037880 A CN 117037880A
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- circuit
- solid state
- state disk
- energy storage
- storage capacitor
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- 230000006378 damage Effects 0.000 title claims abstract description 51
- 239000007787 solid Substances 0.000 title claims abstract description 34
- 239000003990 capacitor Substances 0.000 claims abstract description 40
- 238000004146 energy storage Methods 0.000 claims abstract description 35
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention belongs to the technical field of solid state disks, and particularly provides an optimal design circuit of a hardware destruction circuit of a solid state disk, which comprises a power supply selection circuit and an energy storage capacitor; the power supply selection circuit is used for receiving an external hardware destruction instruction, switching the power supply of the storage chip onto the energy storage capacitor according to the hardware destruction instruction, and destroying the internal data of the storage chip by the high voltage of the energy storage capacitor to destroy the data. The scheme utilizes the original energy storage capacitor (high voltage) of the solid state disk as the impact voltage for destroying the storage chip, and can be realized only by a simple control and conversion circuit. The original destroying power supply booster circuit is simplified, the high-voltage booster circuit is eliminated, meanwhile, the hardware cost is saved, and the layout space of the circuit board is simplified.
Description
Technical Field
The disclosure relates to the technical field of solid state disks, and in particular relates to an optimal design circuit of a hardware destruction circuit of a solid state disk.
Background
When Solid State Disk (SSD) is used for data destruction, two modes of hardware destruction and software destruction can be generally adopted. The hardware destruction means to destroy hard disk data in a physical way, such as heavy object crushing, strong acid solution destruction, high voltage breakdown of a memory chip, etc. The high-voltage destroying mode is to execute one-time destroying action on the memory chip in a high-voltage and impact mode after the controller of the SSD recognizes that the user executes the operation instruction of hardware destroying. The destroying mode is suitable for the situation with higher anti-disclosure security level requirement. The solid state disk which is physically destroyed can not be recovered by any mode.
In the prior art, for destroying hardware of a memory chip by using high voltage, a boost circuit is generally designed for a solid state disk, a low voltage is boosted to a higher voltage, then the high voltage is applied to a power pin (such as a 3.3V power supply) of the memory chip, and after a controller recognizes a hardware destroying instruction, the controller fills the high voltage into the inside of the chip to form high voltage impact, so that data of the memory chip is damaged, and the aim of destroying the data is fulfilled.
At present, a hardware destruction circuit of a Solid State Disk (SSD) has the problems of high voltage, complex circuit design and high cost. How to solve this technical problem is the object of the present solution.
Disclosure of Invention
The disclosure aims to at least solve one of the technical problems in the prior art, and provides an optimal design circuit of a hardware destruction circuit of a solid state disk.
The disclosure provides an optimal design circuit of a hardware destruction circuit of a solid state disk, which comprises a power supply selection circuit and an energy storage capacitor;
the power supply selection circuit is used for receiving an external hardware destruction instruction, switching the power supply of the storage chip onto the energy storage capacitor according to the hardware destruction instruction, and destroying the internal data of the storage chip by the high voltage of the energy storage capacitor to destroy the data.
Preferably, when the power supply selection circuit does not receive the hardware destruction instruction, the energy storage capacitor is used for power-down protection of the solid state disk.
Preferably, the energy storage capacitor comprises two parallel 470 muF and 35V type capacitors.
Preferably, the power supply selection circuit comprises a triode U31 and a MOS tube Q90, wherein the base electrode, the emitter electrode and the collector electrode of the triode U31 are respectively connected with an external hardware destruction instruction, the ground and the energy storage capacitor;
and the S pole and the D pole of the MOS tube Q90 are respectively connected with the energy storage capacitor and the storage chip.
Preferably, the hardware destruction instruction is a high-level voltage signal.
Preferably, two resistors R636 and R637 connected in series are connected between the energy storage capacitor and the collector of the triode U31, and a common terminal of the resistors R636 and R637 is connected with the G pole of the MOS transistor Q90.
Preferably, the resistances of the resistor R636 and the resistor R637 are both 10kΩ.
Preferably, the power port of the memory chip is connected to an external power source through a diode D14, and the voltage of the storage capacitor is higher than the voltage of the external power source.
Preferably, the optimal design circuit further comprises a power management circuit, wherein the power management circuit is used for receiving a hardware destruction instruction of the solid state disk and transmitting the hardware destruction instruction to the power selection circuit.
Drawings
Fig. 1 is an optimized design circuit diagram of a hardware destruction circuit of a solid state disk provided in an embodiment of the disclosure;
Detailed Description
In order that those skilled in the art will better understand the technical solutions of the present disclosure, the present disclosure will be described in further detail with reference to the accompanying drawings and detailed description.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, are not intended to be inclusive of any order, quantity, or importance, but rather are used to distinguish between different components. Also, the terms "a," "an," or "the" and similar terms are not intended to be limiting in number, but rather are intended to mean that there is at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used only for the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed accordingly.
Like elements are designated with like reference numerals throughout the various figures. For purposes of clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Numerous specific details of the present disclosure, such as construction, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.
As shown in fig. 1, an embodiment of the present disclosure provides an optimal design circuit of a hardware destruction circuit of a solid state disk, including a power supply selection circuit and an energy storage capacitor;
the power supply selection circuit is used for receiving an external hardware destruction instruction, switching the power supply of the storage chip onto the energy storage capacitor according to the hardware destruction instruction, and destroying the internal data of the storage chip by the high voltage of the energy storage capacitor to destroy the data.
The scheme utilizes the original energy storage capacitor (high voltage) of the solid state disk as the impact voltage for destroying the storage chip, and can be realized only by a simple control and conversion circuit. The original destroying power supply booster circuit is simplified, the high-voltage booster circuit is eliminated, meanwhile, the hardware cost is saved, and the layout space of the circuit board is simplified.
Preferably, the hardware destruction instruction is transmitted from the original power management circuit. The power management circuit is used for receiving a hardware destruction instruction of the solid state disk and transmitting the hardware destruction instruction to the power selection circuit.
The energy storage capacitor is generally applied to power-down protection of the solid state disk. When the solid state disk has the hardware destruction requirement, the controller can directly act on the pins of the storage chip through the power supply selection circuit by using the high voltage of the energy storage capacitor, so that the effects of high voltage impact and data destruction are achieved.
The power supply selection circuit can be realized by adopting a discrete component (MOS tube).
In one specific implementation, the storage capacitor comprises two 470 muf, 35V type capacitors in parallel.
The following description is made for a specific implementation scenario:
the power supply selection circuit comprises a triode U31 and a MOS tube Q90, wherein the base electrode, the emitter electrode and the collector electrode of the triode U31 are respectively connected with an external hardware destruction instruction, the ground and the energy storage capacitor; and the S pole and the D pole of the MOS tube Q90 are respectively connected with the energy storage capacitor and the storage chip. The energy storage capacitor is connected in series with two resistors R636 and R637 which are connected in series between the collector electrodes of the triode U31, the common end of the resistor R636 and the resistor R637 is connected with the G electrode of the MOS tube Q90, and the G electrode of the MOS tube Q90 is connected with the collector electrode of the triode U31. The resistances of the resistor R636 and the resistor R637 are 10kΩ.
When the high level voltage signal hw_des_con (i.e. the hardware destruction command) is transmitted, the base of the transistor U31 is at a high level, and the transistor U31 is turned on. The voltage of the energy storage capacitor sequentially passes through two resistors R636 and then respectively enters the G pole of the MOS tube Q90 and R637, and then enters the collector of the triode U31 through R637. Resistor R636 pulls the potential high, and the G pole of MOS transistor Q90 also receives the high level, and at this time MOS transistor Q90 is also turned on. The high voltage of the energy storage capacitor is directly input to the power port 3V3_NAND of the storage chip, so that the storage chip is damaged, and the aim of data destruction is fulfilled.
The beneficial effects are that:
the existing energy storage capacitor (power-down protection function) of the solid state disk is used as an energy source for destroying data by hardware. When the user has data destruction demands on the solid state disk (at this time, the user has no power-down protection demands), the electricity on the energy storage capacitor can be switched to the normal power supply of the storage chip, and then the high voltage of the energy storage capacitor can destroy the internal data of the storage chip, so that the data destruction effect is achieved.
It should be noted that the computer readable medium shown in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.
Claims (9)
1. The hardware destruction circuit of the solid state disk is optimally designed and is characterized by comprising a power supply selection circuit and an energy storage capacitor;
the power supply selection circuit is used for receiving an external hardware destruction instruction, switching the power supply of the storage chip onto the energy storage capacitor according to the hardware destruction instruction, and destroying the internal data of the storage chip by the high voltage of the energy storage capacitor to destroy the data.
2. The optimal design circuit of the hardware destruction circuit of the solid state disk according to claim 1, wherein the energy storage capacitor is used for power-down protection of the solid state disk when the power supply selection circuit does not receive the hardware destruction instruction.
3. The optimal design circuit of the hardware destruction circuit of the solid state disk according to claim 1, wherein the energy storage capacitor comprises two capacitors of 470 muf and 35V types connected in parallel.
4. The optimal design circuit of the hardware destruction circuit of the solid state disk according to claim 1, wherein the power supply selection circuit comprises a triode U31 and a MOS tube Q90, and a base electrode, an emitter electrode and a collector electrode of the triode U31 are respectively connected with an external hardware destruction instruction, ground and the energy storage capacitor;
the S pole and the D pole of the MOS tube Q90 are respectively connected with the energy storage capacitor and the storage chip, and the G pole of the MOS tube Q90 is connected with the collector electrode of the triode U31.
5. The optimal design circuit of the hardware destruction circuit of the solid state disk according to claim 4, wherein the hardware destruction instruction is a high-level voltage signal.
6. The circuit for optimizing a hardware destruction circuit of a solid state disk according to claim 4, wherein two resistors R636 and R637 connected in series are connected between the energy storage capacitor and the collector of the triode U31, and a common end of the resistors R636 and R637 is connected with the G pole of the MOS transistor Q90.
7. The optimal design circuit for a hardware destruction circuit of a solid state disk as claimed in claim 6, wherein the resistances of the resistor R636 and the resistor R637 are 10kΩ.
8. The optimal design circuit of the hardware destruction circuit of the solid state disk according to claim 1, wherein the power port of the memory chip is connected to an external power supply through a diode D14, and the voltage of the energy storage capacitor is higher than the voltage of the external power supply.
9. The optimal design circuit of the hardware destruction circuit of the solid state disk according to claim 1, wherein the optimal design circuit further comprises a power management circuit, and the power management circuit is configured to receive a hardware destruction instruction of the solid state disk and transmit the hardware destruction instruction to a power selection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311040275.3A CN117037880A (en) | 2023-08-18 | 2023-08-18 | Optimal design circuit of hardware destruction circuit of solid state disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311040275.3A CN117037880A (en) | 2023-08-18 | 2023-08-18 | Optimal design circuit of hardware destruction circuit of solid state disk |
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| Publication Number | Publication Date |
|---|---|
| CN117037880A true CN117037880A (en) | 2023-11-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311040275.3A Pending CN117037880A (en) | 2023-08-18 | 2023-08-18 | Optimal design circuit of hardware destruction circuit of solid state disk |
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| Country | Link |
|---|---|
| CN (1) | CN117037880A (en) |
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2023
- 2023-08-18 CN CN202311040275.3A patent/CN117037880A/en active Pending
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