CN211457106U - Multi-interface switching circuit and electronic equipment - Google Patents
Multi-interface switching circuit and electronic equipment Download PDFInfo
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- CN211457106U CN211457106U CN201922263819.8U CN201922263819U CN211457106U CN 211457106 U CN211457106 U CN 211457106U CN 201922263819 U CN201922263819 U CN 201922263819U CN 211457106 U CN211457106 U CN 211457106U
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Abstract
The utility model relates to a many interfaces change over switch circuit and electronic equipment, include: the first interface detection circuit is connected with the first input interface, the first driving circuit and the second driving circuit which are respectively connected with the first interface detection circuit, the first change-over switch which is connected with the first input interface and the first driving circuit, and the first output interface which is connected with the first change-over switch; the second input interface is used for connecting the storage card, and the second interface detection circuit is connected with the second interface; a third input interface for providing an EMMC signal input; and the second change-over switch is respectively connected with the second driving circuit, the second interface detection circuit, the second input interface and the third input interface, and is connected with the second output interface of the second change-over switch. Implement the utility model discloses can realize satisfying the multi-way switch switching that the priority order required, the circuit is simple.
Description
Technical Field
The utility model relates to the field of electronic technology, more specifically say, relate to a many interfaces change over switch circuit and electronic equipment.
Background
When the existing embedded system needs to be started from different storage devices and paths, the embedded system can be automatically switched to corresponding target devices. An embedded platform of an existing ARM architecture generally needs to simultaneously support downloading and starting from a plurality of different starting media such as a board-mounted eMMC, a TF card, a USB device, and the like, and an existing switching circuit cannot be suitable for starting the plurality of different media, or needs a high-cost design to realize starting of the plurality of media.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in, to the above-mentioned prior art defect of prior art, a many interfaces change over switch circuit and electronic equipment is provided.
The utility model provides a technical scheme that its technical problem adopted is: a multi-interface switcher circuit is constructed, comprising:
the first interface detection circuit is connected with the first input interface, the first driving circuit and the second driving circuit which are respectively connected with the first interface detection circuit, the first change-over switch which is connected with the first input interface and the first driving circuit, and the first output interface which is connected with the first change-over switch;
the second input interface is used for connecting a storage card, and the second interface detection circuit is connected with the second interface;
a third input interface for providing an EMMC signal input;
and the second change-over switch is respectively connected with the second driving circuit, the second interface detection circuit, the second input interface and the third input interface, and is connected with a second output interface of the second change-over switch.
Preferably, the first driving circuit includes a first MOS transistor, a gate of the first MOS transistor is connected to the first interface detection circuit, a source of the first MOS transistor is grounded, and a drain of the first MOS transistor is connected to the first switch.
Preferably, the display device further comprises an enable signal input end connected with the second driving circuit.
Preferably, the second driving circuit comprises a second MOS transistor, a third MOS transistor and a fourth MOS transistor;
the grid connection of second MOS pipe first interface detection circuitry, the source connection of second MOS pipe the drain electrode of third MOS pipe, the drain electrode of second MOS pipe is connected the grid of fourth MOS pipe, the grid connection of third MOS pipe enable signal input part, the source ground connection of third MOS pipe, the source ground connection of fourth MOS pipe, the drain connection of fourth MOS pipe the second change over switch.
Preferably, the first switch is a USB switch, and the USB switch includes a first USB signal input terminal connected to the first input interface.
Preferably, the multi-interface switch circuit further includes a fourth input interface for connecting an onboard or external USB device, and the USB switch further includes the second USB signal input terminal connected to the fourth input interface.
Preferably, the USB switch is of the type FSUB42 UMX.
Preferably, the first interface detection circuit includes a first resistor and a second resistor, after the first resistor and the second resistor are connected in series, one end of the first resistor is connected to the first input interface, the other end of the first resistor is connected to ground, and series nodes of the first resistor and the second resistor are respectively connected to the first driving circuit and the second driving circuit.
Preferably, the second switch comprises a switch chip U105, and the model of the switch chip U105 is SGM 6505.
The present invention also provides an electronic device including the multi-interface changeover switch circuit as described above.
Implement the utility model discloses a many interfaces change over switch circuit and electronic equipment has following beneficial effect: the multi-way switch switching meeting the priority order requirement is realized, and the circuit is simple.
Drawings
The invention will be further explained with reference to the drawings and examples, wherein:
fig. 1 is a schematic structural diagram of a multi-interface transfer switch circuit according to the present invention;
fig. 2 is a schematic circuit diagram of an embodiment of the multi-interface switch circuit of the present invention.
Detailed Description
In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, in an embodiment of the present invention, a multi-interface switch circuit includes: the first interface detection circuit 121 is used for connecting a first input interface 111 of an upper computer device, connecting the first input interface 111, respectively connecting a first driving circuit 131 and a second driving circuit 132 of the first interface detection circuit 121, connecting a first change-over switch 141 of the first input interface 111 and the first driving circuit 131, and connecting a first output interface 151 of the first change-over switch 141; a second input interface 112 for connecting a memory card, a second interface detection circuit 122 for connecting the second interface; a third input interface 113 for providing an EMMC signal input; the second switch 142 is connected to the second driving circuit 132, the second interface detection circuit 122, the second input interface 112, and the third input interface 113, and the second output interface 152 of the second switch 142 is connected thereto. Specifically, when the first output interface 151 is connected to an upper computer device, the first interface detection circuit 121 connected to the first input interface 111 detects the access of the upper computer device and generates a corresponding detection level, for example, a high level, the first driving circuit 131 receives the detection level and generates a corresponding driving level according to the detection level, and the first switching switch 141 is driven by the driving level to switch the first input interface 111 and the first output interface 151 to be connected. The second driving circuit 132 receives and generates a corresponding driving level according to the detection level, and drives the second switch 142 to be in a closed state through the driving level. At this time, the device connected to the first output interface 151 may load software through the upper computer device connected to the first input interface 111, and no data is output through the second output port no matter whether the second input interface 112 and the third input interface 113 have access to a loading source. When the first input interface 111 is not connected to the host device, the first interface detection circuit 121 connected to the first input interface 111 detects that the generated corresponding detection level is, for example, a low level, and the first driving circuit 131 receives the detection level and generates a corresponding driving level according to the detection level, and drives the first switch 141 to switch to an off state according to the driving level. The second driving circuit 132 receives and generates a corresponding driving level according to the detection level, and drives the second switch 142 to be in an operating state through the driving level. Meanwhile, when the second input interface 112 is connected to a memory card, the second interface detection circuit 122 generates a corresponding detection level, and the second switch 142 switches the second input interface 112 to be conducted with the second output interface 152 according to the detection level, so that software of a device connected to the second output interface 152 is loaded through the memory card. If the first switch 141 is in an off state and the second switch 142 is in an operating state, the second input interface 112 has no memory card connected thereto, and the second interface detection circuit 122 has no corresponding detection level output, at this time, the second switch 142 switches the third input interface 113 to be connected to the second output interface 152, so as to implement software loading of the device connected to the second output interface 152 by the on-board EMMC. According to the above description, the software loading process for the external device can be automatically implemented by selecting the first input interface 111, the second input interface 112 and the third input interface 113 in sequence.
As shown in fig. 2, in an embodiment, the first driving circuit 131 includes a first MOS transistor Q11, a gate of the first MOS transistor Q11 is connected to the first interface detection circuit 121, a source of the first MOS transistor Q11 is grounded, and a drain of the first MOS transistor Q11 is connected to the first switch 141. Specifically, the first driving circuit 131 includes a first MOS transistor Q11, wherein the detection level of the first interface detection circuit 121 can control the first MOS transistor Q11 to turn on or off through the gate of the first MOS transistor Q11, so as to turn on or off the first switch 141 connected to the first MOS transistor Q11.
In one embodiment, the multi-interface switch circuit of the present invention further includes an enable signal input terminal 171 connected to the second driving circuit 132. Specifically, the second driving circuit 132 for driving the second switch 142 to be in the operating state or the non-operating state may further receive an enable signal input from the outside, for example, the controller may input the enable signal through the enable signal input terminal 171, so that the second driving circuit 132 outputs a level to make the second switch 142 be in the operating state or the non-operating state.
In one embodiment, the second driving circuit 132 includes a second MOS transistor Q9, a third MOS transistor Q10, and a fourth MOS transistor Q8; the gate of the second MOS transistor Q9 is connected to the first interface detection circuit 121, the source of the second MOS transistor Q9 is connected to the drain of the third MOS transistor Q10, the drain of the second MOS transistor Q9 is connected to the gate of the fourth MOS transistor Q8, the gate of the third MOS transistor Q10 is connected to the enable signal input terminal 171, the source of the third MOS transistor Q10 is grounded, the source of the fourth MOS transistor Q8 is grounded, and the drain of the fourth MOS transistor Q8 is connected to the second switch 142. Specifically, the enable signal of the enable signal input terminal 171 controls the third MOS transistor Q10 to be turned on or off, and drives the second MOS transistor Q9 to be turned on or off according to the on or off of the third MOS transistor Q10 and the detection level output by the first interface detection circuit 121, so as to further drive the fourth MOS transistor Q8 to be turned on or off, and finally, the operating state of the second switch 142 is switched, that is, the second switch enters the operating state or the non-operating state.
In an embodiment, the first switch 141 is a USB switch, and the USB switch includes a first USB signal input 1411 connected to the first input interface 111. Specifically, the first switch 141 is a USB switch, the first input interface 111 connected to the upper device is a USB interface, the first output interface 151 connected to the later device is also a USB interface, and when the first switch 141 is turned on, USB data of the upper device can be output to the later device through the first switch 141 and the first output interface 151 for loading.
Further, the utility model discloses a many interfaces change over switch circuit is still including the fourth input interface that is used for connecting board and carries or external USB equipment, and USB change over switch is still including the second USB signal input part 1412 of connecting fourth input interface. Specifically, a separate USB interface, that is, a fourth input interface, may be further provided, and the fourth input interface is switched by the USB switch to connect to the second USB signal input end, when the first input interface 111 is not input and connected, the enable signal input end 171 inputs the enable signal that the second driving circuit 132 outputs the driving level to enable the second switch 142 to be in the non-operating state, and when the first driving circuit 131 does not output the driving level, that is, the first switch 141 controls the second USB signal input end to be turned on in the default state, that is, the fourth input interface software connected to the second USB signal input end may be loaded at this time.
Optionally, the USB switch is of type FSUB42 UMX.
In an embodiment, the first interface detection circuit 121 includes a first resistor and a second resistor, the first resistor and the second resistor are connected in series, and then one end of the first resistor and the second resistor are connected to the first input interface 111, and the other end of the first resistor and the second resistor are connected to ground, and a series node of the first resistor and the second resistor is respectively connected to the first driving circuit 131 and the second driving circuit 132. Specifically, when the first input interface 111 is a USB interface and the first input interface 111 is connected to an upper computer device, the input voltage is 5V, the first interface detection circuit 121 is a voltage dividing resistor connected in series, the obtained detection level may be 3.3V, and the first driving circuit 131 and the second driving circuit 132 are driven to operate by the 3.3V level.
In one embodiment, the second switch 142 includes a switch chip U105, and the model of the switch chip U105 is SGM 6505.
In a specific embodiment, when the first input interface 111 is an OTG-USB interface, and the storage card is a TF card, when the lower-level device is powered on and no TF card or OTG-USB signal is detected, the slave-board eMMC is started; when an OTG-USB signal is detected, starting from an OTG upper computer; the priority order is: OTG > TF > eMMC. The specific working sequence is as follows:
if the OTG signal exists, namely an external USB plug-in system exists, the USB _ OTG _ VBUS signal is set high at the moment, the enable signal of the SGM6505 is made invalid, and therefore a path for reading the content from the eMMC or the TF card by the system is disconnected; and meanwhile, the generated OTG _ IN signal enables a switch of the FSUSB42UMX to be switched to the HSD1, and USB signals of the programming upper computer and the target system are switched on, so that the OTG function is realized. Even if the onboard eMMC and the onboard TF card exist, the OTG is still forcibly started if an external OTG signal exists, so that the highest priority is realized. When no external OTG signal exists and an external TF card is inserted, the SD _ CLK _ SDcard signal is set to be low, so that COMx of the SGM6505 is enabled to be directed to NCx, and the CPU of the system is enabled to be started from the TF card. In this case, even if the onboard eMMC exists, the TF card is forcibly started from the inserted TF card, and the priority of the TF card is higher than that of the eMMC. When no external OTG signal and TF card is inserted, the slave on-board eMMC is enabled, the default USB _ OTG _ VBUS signal is set low, and the SD _ CLK _ SDcard signal is set high. Thereby realizing the startup from the onboard eMMC without OTG and TF by default. In other embodiments, the memory card may be an SD card or the like.
The utility model discloses an electronic equipment, include as above arbitrary many interfaces change over switch circuit. Specifically, in some electronic devices, the multi-interface switch circuit may be configured to implement multi-input software loading or data transmission, or the electronic module of the setting unit may be detachably connected to the existing system device to implement multi-input software loading on the existing system device.
It is to be understood that the foregoing examples merely represent preferred embodiments of the present invention, and that the description thereof is more specific and detailed, but not intended to limit the scope of the invention; it should be noted that, for those skilled in the art, the above technical features can be freely combined, and several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention; therefore, all changes and modifications that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims (10)
1. A multi-interface switcher circuit, comprising:
the first interface detection circuit is connected with the first input interface, the first driving circuit and the second driving circuit which are respectively connected with the first interface detection circuit, the first change-over switch which is connected with the first input interface and the first driving circuit, and the first output interface which is connected with the first change-over switch;
the second interface detection circuit is connected with the second input interface;
a third input interface for providing an EMMC signal input;
and the second change-over switch is respectively connected with the second driving circuit, the second interface detection circuit, the second input interface and the third input interface, and is connected with a second output interface of the second change-over switch.
2. The multi-interface switch circuit according to claim 1, wherein the first driving circuit comprises a first MOS transistor, a gate of the first MOS transistor is connected to the first interface detection circuit, a source of the first MOS transistor is grounded, and a drain of the first MOS transistor is connected to the first switch.
3. The multi-interface switcher circuit of claim 1, further comprising an enable signal input connected to the second driver circuit.
4. The multi-interface switch circuit of claim 3, wherein the second driving circuit comprises a second MOS transistor, a third MOS transistor and a fourth MOS transistor;
the grid connection of second MOS pipe first interface detection circuitry, the source connection of second MOS pipe the drain electrode of third MOS pipe, the drain electrode of second MOS pipe is connected the grid of fourth MOS pipe, the grid connection of third MOS pipe enable signal input part, the source ground connection of third MOS pipe, the source ground connection of fourth MOS pipe, the drain connection of fourth MOS pipe the second change over switch.
5. The multi-interface switch circuit of claim 1, wherein the first switch is a USB switch, and the USB switch comprises a first USB signal input connected to the first input interface.
6. The multi-interface switcher circuit of claim 5, further comprising a fourth input interface for connecting an onboard or external USB device, the USB switcher further comprising a second USB signal input connected to the fourth input interface.
7. The multi-interface switcher circuit of claim 6, wherein the USB switcher is of type FSUB42 UMX.
8. The multi-interface switch circuit according to claim 1, wherein the first interface detection circuit comprises a first resistor and a second resistor, the first resistor and the second resistor are connected in series, one end of the first resistor is connected to the first input interface, the other end of the first resistor is connected to ground, and a series node of the first resistor and the second resistor is connected to the first driving circuit and the second driving circuit, respectively.
9. The multi-interface switch circuit of claim 1, wherein the second switch comprises a switch chip U105, and the model of the switch chip U105 is SGM 6505.
10. An electronic device comprising a multi-interface switcher circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922263819.8U CN211457106U (en) | 2019-12-16 | 2019-12-16 | Multi-interface switching circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922263819.8U CN211457106U (en) | 2019-12-16 | 2019-12-16 | Multi-interface switching circuit and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211457106U true CN211457106U (en) | 2020-09-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922263819.8U Expired - Fee Related CN211457106U (en) | 2019-12-16 | 2019-12-16 | Multi-interface switching circuit and electronic equipment |
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| Country | Link |
|---|---|
| CN (1) | CN211457106U (en) |
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2019
- 2019-12-16 CN CN201922263819.8U patent/CN211457106U/en not_active Expired - Fee Related
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200908 Termination date: 20211216 |
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| CF01 | Termination of patent right due to non-payment of annual fee |