CN117037733A - Display panel and display device - Google Patents
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- CN117037733A CN117037733A CN202311039529.XA CN202311039529A CN117037733A CN 117037733 A CN117037733 A CN 117037733A CN 202311039529 A CN202311039529 A CN 202311039529A CN 117037733 A CN117037733 A CN 117037733A
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- 239000003990 capacitor Substances 0.000 claims abstract description 52
- 230000002093 peripheral effect Effects 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000005538 encapsulation Methods 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 5
- 238000007599 discharging Methods 0.000 claims description 3
- 238000005192 partition Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 14
- 239000000758 substrate Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a display panel and a display device, wherein the display panel comprises: the special-shaped display area and a peripheral area surrounding the special-shaped display area; the peripheral area comprises a scanning driving circuit; the scan driving circuit comprises a plurality of scan driving units which are cascaded; the scanning driving circuit is divided into at least two areas, and each area comprises a plurality of scanning driving units; the ratio of the length of the scanning driving unit in the first direction to the width in the second direction is different, and the second direction is orthogonal to the first direction; each scanning driving unit comprises transistors and capacitors, the arrangement modes of the transistors and the capacitors contained in the scanning driving units in the same area are the same, and the arrangement modes of the transistors and the capacitors contained in the scanning driving units in different areas are different. The invention carries out partition design on the scanning driving circuit and can meet the design requirement of a display panel with a narrow frame.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
The array substrate row driving (Gate Driver on Array, abbreviated as GOA) technology integrates a thin film transistor (Thin Film Transistor, abbreviated as TFT) gate switch circuit on an array substrate of a display panel to realize scanning driving of the display panel, so that a binding (Bonding) area and a Fan out (Fan out) wiring space of a gate integrated circuit (Integrated Circuit, abbreviated as IC) can be omitted, which is favorable for narrowing a frame of a display product, however, in a special-shaped display product, a Fan-out area of a data driving circuit occupies a part of an area of a side frame of the product, so that the space of the scanning driving circuit is compressed, and in order to meet the design requirement of a narrow frame, the scanning driving circuit needs to be adaptively designed.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for realizing the design of a narrow frame of a display product.
One aspect of the present invention provides a display panel including: the special-shaped display area and a peripheral area surrounding the special-shaped display area;
the peripheral area comprises a scanning driving circuit; the scanning driving circuit comprises a plurality of cascaded scanning driving units;
the scanning driving circuit is divided into at least two areas, and each area comprises a plurality of scanning driving units; the ratio of the length of the scanning driving unit in a first direction to the width in a second direction, which is orthogonal to the first direction, is different for the different regions;
each scanning driving unit comprises a transistor and a capacitor, the arrangement modes of the transistors and the capacitors contained in the scanning driving units in the same area are the same, and the arrangement modes of the transistors and the capacitors contained in the scanning driving units in different areas are different.
In some embodiments of the present invention, the special-shaped display area is circular in shape; the peripheral area further comprises fan-out area wires, and the fan-out area wires are positioned between the scanning driving circuit and the special-shaped display area;
the scanning driving circuit comprises a first area, a second area and a third area which are sequentially and adjacently arranged; the first area is adjacent to the special-shaped display area, a part of fan-out area wiring is arranged between the second area and the special-shaped display area, and another part of fan-out area wiring is arranged between the third area and the special-shaped display area.
In some embodiments of the present invention, a ratio of a length of the scan driving unit of the first region in the first direction to a width of the scan driving unit in the second direction is a first ratio;
the ratio of the length of the scanning driving unit of the second region in the first direction to the width of the scanning driving unit in the second direction is a second ratio;
the ratio of the length of the scanning driving unit of the third region in the first direction to the width of the scanning driving unit in the second direction is a third ratio;
the third ratio is greater than the first ratio, and the first ratio is greater than the second ratio.
In some embodiments of the present invention, the scan driving unit includes an output transistor and a capacitor; the capacitor is arranged adjacent to the output transistor, and is connected to the grid electrode and the first electrode of the output transistor, and the arrangement modes of the output transistor and the capacitor of each scanning driving unit in different areas are different.
In some embodiments of the present invention, in each scan driving unit of the first region, the output transistor and the capacitor are arranged side by side in the first direction;
in each scan driving unit of the second region, a partial region of the capacitor is located at one side of the output transistor in the first direction, and another partial region of the capacitor is located at one side of the output transistor in the second direction;
in each scan driving unit of the third region, the output transistor and the capacitor are arranged side by side in the second direction.
In some embodiments of the present invention, the scan driving unit further includes a charge transistor and a discharge transistor;
in each scanning driving unit of the first area, the charging transistor and the discharging transistor are arranged in a staggered manner in the first direction and the second direction;
in each scanning driving unit of the second region, the charge transistor and the discharge transistor are arranged side by side in the second direction;
in each scan driving unit of the third region, the charge transistor and the discharge transistor are arranged side by side in the first direction.
In some embodiments of the present invention, the peripheral region further includes a common potential signal circuit; the common potential signal circuit is arranged around the special-shaped display area and is positioned between the scanning driving circuit and the fan-out area wiring.
In some embodiments of the present invention, the peripheral area further includes an encapsulation layer, the encapsulation layer is located at a side of the scan driving circuit facing away from the special-shaped display area, and a distance between a cutting edge of the peripheral area and a side of the encapsulation layer facing away from the scan driving circuit is less than 10 μm.
In some embodiments of the present invention, the scan driving circuit includes a plurality of metal layers stacked and connected by a single via between patterns of different metal layers.
Another aspect of the present invention provides a display device including any one of the display panels described above.
The invention has the following beneficial effects:
the invention provides a display panel and a display device, wherein the display panel comprises: the special-shaped display area and a peripheral area surrounding the special-shaped display area; the peripheral area comprises a scanning driving circuit; the scan driving circuit comprises a plurality of scan driving units which are cascaded; the scanning driving circuit is divided into at least two areas, and each area comprises a plurality of scanning driving units; the ratio of the length of the scanning driving unit in the first direction to the width in the second direction is different, and the second direction is orthogonal to the first direction; each scanning driving unit comprises transistors and capacitors, the arrangement modes of the transistors and the capacitors contained in the scanning driving units in the same area are the same, and the arrangement modes of the transistors and the capacitors contained in the scanning driving units in different areas are different. The invention carries out partition design on the scanning driving circuit and can meet the design requirement of a display panel with a narrow frame.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a scan driving unit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a scan driving unit according to an embodiment of the present invention;
FIG. 4 is a second schematic diagram of a scan driving unit according to an embodiment of the present invention;
FIG. 5 is a third schematic diagram of a scan driving unit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a scan driving unit according to an embodiment of the present invention;
fig. 7 is a partial enlarged view of a display panel according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a via hole in a display panel according to the related art;
fig. 9 is a schematic view of a via hole in a display panel according to an embodiment of the invention;
fig. 10 is a cross-sectional view of fig. 9 in the direction C-C'.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a further description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present invention are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present invention. The drawings of the present invention are merely schematic representations of relative positional relationships and are not intended to represent true proportions.
The liquid crystal display (Liquid Crystal Display, abbreviated as LCD) is driven in a progressive scanning manner, the conventional LCD device needs an external control element to send a control signal, and a scan driving circuit and a data driving circuit are disposed in the LCD device to respectively drive each display pixel in the display panel, and at this time, a certain space is required to be reserved at the frame of the LCD device for setting fan-out wires of the driving circuit and binding the control element. The GOA technology integrates the TFT grid switch circuit on the array substrate of the display panel to realize scanning driving of the display panel, so that a binding area of the scanning drive circuit and a wiring space of a fan-out area can be omitted, the frame of a display product can be narrowed, but in a special-shaped display product, the fan-out area of the data drive circuit occupies a part of the area of the side frame of the product, the space of the scanning drive circuit is compressed, and the scanning drive circuit needs to be adaptively designed in order to meet the design requirement of a narrow frame.
In view of this, the embodiment of the invention provides a display panel, which can realize a narrow frame design of the display panel.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
As shown in fig. 1, the display panel includes a special-shaped display area AA and a peripheral area AA 'surrounding the special-shaped display area AA, wherein an area between the edge of the special-shaped display area AA and the edge of the peripheral area AA' is a frame area of the display panel, and when the width of the frame area is less than 1mm, the display panel can be regarded as meeting the requirement of a narrow-frame product.
In the embodiment of the invention, the display panel integrates the scanning driving circuit 100 into the peripheral area AA' of the display panel by adopting the GOA technology, and the scanning driving circuit 100 comprises a plurality of cascaded scanning driving units for providing row scanning signals for pixels in the special-shaped display area AA, so that the wiring space of a binding area and a fan-out area of the scanning driving circuit 100 can be saved, and the frame of a display product can be narrowed.
Since other wirings are required to be disposed in the peripheral area AA ', the width of the space between the edge of the peripheral area AA' and the edge of the display area, which can be used for disposing the scan driving circuit 100, is different in different areas, so that the scan driving circuit 100 is adapted to the narrow frame requirement of the display panel. Each region of the scan driving circuit 100 includes a plurality of scan driving units, and the ratio of the length of the scan driving units belonging to different regions in the first direction X to the width thereof in the second direction Y, which is orthogonal to the first direction X, is different. Each scanning driving unit comprises transistors and capacitors, the arrangement modes of the transistors and the capacitors contained in the scanning driving units in the same area are the same, and the arrangement modes of the transistors and the capacitors contained in the scanning driving units in different areas are different.
The embodiment of the invention describes the partition design principle of the scan driving circuit 100 in the special-shaped display panel by using the case that the special-shaped display area AA is circular in shape, and in the specific implementation, the scan driving circuit 100 can be adaptively designed by adopting the partition design concept as described below for an R-angle display panel or other special-shaped display panels with narrow frame requirements.
As shown in fig. 1, for a display panel with a circular display area, the peripheral area AA' of the display panel further includes a fan-out area wiring 200, and the fan-out area wiring 200 is located between the scan driving circuit 100 and the special-shaped display area AA, and is generally disposed in the area 1/4 of the lower portion of the circular display panel, and can be used for winding the data driving circuit in the display panel into the binding area to connect with an external control element.
The peripheral area AA' of the display panel further includes a common potential signal circuit 300, where the common potential signal circuit 300 is disposed around the abnormal display area AA and located between the scan driving circuit 100 and the fan-out area wiring 200, and the shape of the common potential signal circuit is adapted to the shape of the side edge of the scan driving circuit 100 near the display area.
The space between the edge of the peripheral area AA' and the common potential signal circuit 300 may be used to set the scan driving circuit 100, and in the embodiment of the present invention, the scan driving circuit 100 of the circular display panel may include a first area Q1, a second area Q2, and a third area Q3 that are sequentially and adjacently arranged, so that, to meet the design requirement of the narrow frame, the space sizes of the three areas that may be used to set the scan driving circuit 100 are different, and thus the ratio of the length of the scan driving unit in the first direction X to the width of the scan driving unit in the second direction Y in each area is different.
Specifically, the first region Q1 is adjacent to the abnormal display area AA in which the space of the scan driving circuit 100 is more abundant, and the width Y1 of each scan driving unit in the second direction Y may be set to be the same as the width of the pixels in the display area in the second direction Y.
A part of the fan-out area wiring 200 is disposed between the second area Q2 and the special-shaped display area AA, and the space of the scan driving circuit 100 in the area is narrower than that of the first area Q1, so that the length X2 of each scan driving unit in the first direction X in the second area Q2 is shorter than that of the scan driving unit in the first direction X in the first area Q1, and accordingly, the width Y2 of each scan driving unit in the second area Q2 in the second direction Y is set shorter than that of the scan driving unit in the first area Q1 because the space occupied by each scan driving unit is the same.
Another part of the fan-out area wiring 200 is disposed between the third area Q3 and the special-shaped display area AA, and the space of the scan driving circuit 100 in the area may be wider than that of the second area Q2, so that the length X3 of each scan driving unit in the third area Q3 in the first direction X is longer than that of the scan driving unit in the second area Q2 in the first direction X, and accordingly, the width Y3 of each scan driving unit in the third area Q3 in the second direction Y is set shorter than that of the scan driving unit in the second direction Y in the second area Q2. In addition, the scanning driving unit of the last stage in the third region Q3 may be flush with the pixel of the last stage in the display area, so as to avoid affecting the design of other parts of the display panel.
In the embodiment of the present invention, the ratio of the length X1 of the scanning driving unit in the first direction X to the width Y1 in the second direction Y of the first region Q1 is a first ratio; the ratio of the length X2 of the scanning driving unit of the second region Q2 in the first direction X to the width Y2 of the scanning driving unit in the second direction Y is a second ratio; the ratio of the length X3 of the scanning driving unit of the third region Q3 in the first direction X to the width Y3 of the scanning driving unit in the second direction Y is a third ratio; the third ratio x3/y3 is greater than the first ratio x1/y1, and the first ratio x1/y1 is greater than the second ratio x2/y2, so that the length and width of the scan driving circuit 100 in each region can be adapted to the size of the available space in each region, and a narrow frame design is realized.
Fig. 2 is a circuit diagram of a scan driving unit according to an embodiment of the present invention.
In the embodiment of the present invention, as shown in fig. 2, in the scan driving unit, an Input signal terminal (Input) is connected to the gate of the first transistor M1, an Output signal terminal (Output) is connected to the first pole of the third transistor M3, a Reset signal terminal (Reset) is connected to the gate of the second transistor M2, a first clock signal terminal (CLK) is connected to the second pole of the third transistor M3, a second clock signal terminal (clk_b) is connected to the gate of the sixth transistor M6, a low-potential signal terminal (VGL) is connected to the first poles of the second transistor M2, the seventh transistor M7, the fifth transistor M5, the eighth transistor M8, and the fourth transistor M4, and a capacitor C is connected between the gate and the first pole of the third transistor M3. The first clock signal end (CLK) and the second clock signal end (clk_b) are used for outputting voltage signals with opposite phases in time sequence, and the specific time sequence driving mode thereof can be adjusted according to practical application and is not limited herein; the first pole and the second pole of each transistor may be determined as a source or a drain according to practical applications, and are not limited herein.
In the 8T1C circuit shown in fig. 2, the first transistor M1 may be used to precharge PU point, which is the pull-up node of the output signal, when Input is pulled high; the second transistor M2 may be used to discharge the PU point; the third transistor M3 may be used for charging and discharging Output and bootstrapping PU (hereinafter referred to as the Output transistor M3); the fourth transistor M4 may be used to noise reduce Output; the fifth transistor M5 may be used to discharge a PD point (hereinafter, referred to as a discharge transistor M5), and the sixth transistor M6 may be used to charge a PD point (hereinafter, referred to as a charge transistor M6), which is a pull-down point of the output signal; the seventh transistor M7 may be configured to release the unwanted noise signal at the PU point; the eighth transistor M8 may be used to release the unwanted noise signal on Output; the capacitor C can be used for PU bootstrap and noise reduction of PU points.
FIG. 3 is a schematic diagram of a scan driving unit according to an embodiment of the present invention; FIG. 4 is a second schematic diagram of a scan driving unit according to an embodiment of the present invention; fig. 5 is a third schematic diagram of a scan driving unit according to an embodiment of the invention.
As shown in fig. 3, 4 and 5, in the scan driving unit 110, the capacitor C is disposed adjacent to the output transistor M3, and the capacitor C is connected to the gate and the first pole of the output transistor M3, and the arrangement manners of the output transistor M3 and the capacitor C of each scan driving unit 110 in different regions are different.
As shown in fig. 3, the space of the scan driving circuit 100 in the first region Q1 is relatively abundant, so that the output transistor M3 and the capacitor C may be disposed side by side in the first direction X in each scan driving unit 110 of the first region Q1, and the charge transistor M6 and the discharge transistor M5 may be disposed offset in both the first direction X and the second direction Y.
As shown in fig. 4, the space of the scan driving circuit 100 in the second region Q2 is narrower than that of the first region Q1, and thus, in each scan driving unit 110 of the second region Q2, a partial region of the capacitor C may be located at one side of the output transistor M3 in the first direction X, another partial region of the capacitor C may be located at one side of the output transistor M3 in the second direction Y, and the charge transistor M6 and the discharge transistor M5 may be disposed side by side in the second direction Y.
In addition, compared with fig. 3, in each scan driving unit 110 in the second area Q2, the positions of the first transistor M1, the second transistor M2, the fourth transistor M4, the seventh transistor M7 and the eighth transistor M8 are relatively unchanged, two vias adjacent to the seventh transistor M7 are aligned from being aligned along the first direction X to being aligned along the second direction Y, and the via between the capacitor C and the first transistor M1 can be adjusted between the fourth transistor M4 and the capacitor C, so that the scan driving unit 110 in the second area Q2 can have a larger width in the second direction Y and a smaller length in the first direction X, thereby meeting the design requirement of the narrow frame display panel.
As shown in fig. 5, the space of the scan driving circuit 100 in the third region Q3 may be wider than that of the second region Q2, the output transistor M3 and the capacitor C may be disposed side by side in the second direction Y, and the charge transistor M6 and the discharge transistor M5 may be disposed side by side in the first direction X within each scan driving unit 110 of the third region Q3.
In addition, compared with fig. 4, in each scan driving unit 110 in the third region Q3, the charge transistor M6, the discharge transistor M5, the seventh transistor M7, the eighth transistor M8 and the fourth transistor M4 may be sequentially arranged along the first direction X and located at one side of the output transistor M3 and the capacitor C, the first transistor M1 and the second transistor M2 may be arranged along the first direction X and located at the other side of the output transistor M3 and the capacitor C, two vias adjacent to the seventh transistor M7 may be aligned along the first direction X, and two vias between the capacitor C and the first transistor M1 may be aligned along the first direction X from the second direction Y, so that the scan driving unit 110 in the third region Q3 may have a smaller width in the second direction Y and a larger length in the first direction X, thereby meeting the design requirement of the narrow frame display panel.
The embodiment of the present invention is described by taking the case of adjusting the shape of the capacitor C in the scan driving unit 110 as an example, and it is understood that, based on the inventive concept of the present invention, the shape of at least one transistor or capacitor in the scan driving unit may be adjusted according to actual requirements, and the relative positions between the transistors and between the capacitors may be adjusted, which is not limited herein. Moreover, the present inventive concept may also be applied to a scan driving unit employing other pixel circuit structures such as an 11T1C circuit, a 17T1C circuit, etc., so that the arrangement of transistors and capacitors is adapted to the length and width of the scan driving unit in each region, and embodiments of the present invention are not limited herein.
Fig. 6 is a schematic diagram of a scan driving unit according to an embodiment of the invention.
Fig. 6 shows a pattern of each film layer in the 8T1C scan driving unit shown in fig. 3, including a first conductive layer 111, a channel layer 112, a second conductive layer 113, an insulating layer 114, and a third conductive layer 115 sequentially disposed on a substrate, wherein the first conductive layer 111 includes a signal trace, a gate electrode of each transistor, and one plate of a capacitor; the second conductive layer 112 includes a signal trace, source and drain electrodes of each transistor, and another plate of the capacitor; the channel of each transistor is provided in the channel layer 112 between the first conductive layer 111 and the second conductive layer 113; the insulating layer 114 includes a plurality of vias therein, each of which exposes a portion of the patterns of the first conductive layer 111 and the second conductive layer 113; the third conductive layer 115 is Indium Tin Oxide (ITO) for electrically connecting the first conductive layer 111 and the second conductive layer 113 exposed in the via hole.
The scan driving unit shown in fig. 4 and 5 also has the above five film layers, which are not described herein. As can be seen from fig. 6, each transistor and capacitor in the scan driving unit are located in a plurality of film layers, it can be understood that when the arrangement and shape of each transistor and capacitor are changed, the pattern of each film layer is correspondingly changed, and the relative positions of the patterns forming the same transistor and the same capacitor in each film layer are unchanged.
Fig. 7 is a partial enlarged view of a display panel according to an embodiment of the invention.
Fig. 7 shows an enlarged view of an area D in the display panel, as shown in fig. 7, the peripheral area AA' further includes a packaging layer 400, the packaging layer 400 is located on a side of the scan driving circuit 100 facing away from the special-shaped display area AA, and the packaging layer 400 may specifically use a sealant (Seal glue) or the like to avoid adverse effects on the performance of the driving circuit caused by the entry of water and oxygen into the display panel.
In the first direction X, the package layer 400, the scan driving circuit 100, and the common potential signal circuit 300 are sequentially disposed in the peripheral area AA', wherein the common potential signal circuit 300 has a certain distance from the edge of the display area to avoid occurrence of short circuit; when the substrate of the display panel is cut, a certain interval may be set between the Cutting line (Cutting line) and the encapsulation layer 400 to avoid that the substrate generates cracks to adversely affect the driving circuit in the Cutting process, and in general, the interval may be set to 200 μm.
In some embodiments, the line width of the common potential signal circuit 300 may be further narrowed, and the line width of the common potential signal circuit 300 may be reduced from a conventional 50 μm or more to about 20 μm, thereby further narrowing the frame of the display panel while ensuring the uniformity of the common potential signal on the display panel.
FIG. 8 is a schematic diagram of a via hole in a display panel according to the related art; fig. 9 is a schematic view of a via hole in a display panel according to an embodiment of the invention; fig. 10 is a cross-sectional view of fig. 9 in the direction C-C'.
As shown in fig. 8, the scan driving circuit 100 includes a plurality of metal layers stacked, and two vias H are disposed between each pattern of the different layers of metal of the scan driving circuit for connection in the related art, so that a short circuit caused by excessive current passing through the vias H during operation of the scan driving circuit 100 can be prevented, a problem of poor display is avoided, the vias H need to be completely wrapped by metal to ensure connection quality, and more space is occupied by the metal wrapping the vias H.
As shown in fig. 9 and 10, in the scan driving circuit 100 provided by the embodiment of the invention, patterns located in different metal layers are connected through a single via H, so that the space occupied by the via H and the metal wrapping the via H can be reduced while the normal connection of the circuit is ensured, and compared with the dual-hole design, the width of the scan driving circuit is reduced by half, which is beneficial to saving space and further narrowing the frame of the display panel. In some embodiments, a single-hole connection may be used between the scan driving circuit 100 and other signal lines, which is also beneficial to narrowing the frame of the display panel, and the more the number of single-hole connections in the driving circuit, the more the frame of the display panel is narrowed.
Based on the same inventive concept, the embodiment of the invention also provides a display device, wherein the display device comprises any display panel, and the narrow-frame display device can provide better viewing experience for users.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A display panel, comprising: the special-shaped display area and a peripheral area surrounding the special-shaped display area;
the peripheral area comprises a scanning driving circuit; the scanning driving circuit comprises a plurality of cascaded scanning driving units;
the scanning driving circuit is divided into at least two areas, and each area comprises a plurality of scanning driving units; the ratio of the length of the scanning driving unit in a first direction to the width in a second direction, which is orthogonal to the first direction, is different for the different regions;
each scanning driving unit comprises a transistor and a capacitor, the arrangement modes of the transistors and the capacitors contained in the scanning driving units in the same area are the same, and the arrangement modes of the transistors and the capacitors contained in the scanning driving units in different areas are different.
2. The display panel of claim 1, wherein the shaped display area is circular in shape; the peripheral area further comprises fan-out area wires, and the fan-out area wires are positioned between the scanning driving circuit and the special-shaped display area;
the scanning driving circuit comprises a first area, a second area and a third area which are sequentially and adjacently arranged; the first area is adjacent to the special-shaped display area, a part of fan-out area wiring is arranged between the second area and the special-shaped display area, and another part of fan-out area wiring is arranged between the third area and the special-shaped display area.
3. The display panel according to claim 2, wherein a ratio of a length of the scan driving unit of the first region in the first direction to a width of the scan driving unit in the second direction is a first ratio;
the ratio of the length of the scanning driving unit of the second region in the first direction to the width of the scanning driving unit in the second direction is a second ratio;
the ratio of the length of the scanning driving unit of the third region in the first direction to the width of the scanning driving unit in the second direction is a third ratio;
the third ratio is greater than the first ratio, and the first ratio is greater than the second ratio.
4. The display panel of claim 3, wherein the scan driving unit includes an output transistor and a capacitor; the capacitor is arranged adjacent to the output transistor, and is connected to the grid electrode and the first electrode of the output transistor, and the arrangement modes of the output transistor and the capacitor of each scanning driving unit in different areas are different.
5. The display panel according to claim 4, wherein in each scan driving unit of the first region, the output transistor and the capacitor are arranged side by side in the first direction;
in each scan driving unit of the second region, a partial region of the capacitor is located at one side of the output transistor in the first direction, and another partial region of the capacitor is located at one side of the output transistor in the second direction;
in each scan driving unit of the third region, the output transistor and the capacitor are arranged side by side in the second direction.
6. The display panel according to claim 4 or 5, wherein the scan driving unit further comprises a charge transistor and a discharge transistor;
in each scanning driving unit of the first area, the charging transistor and the discharging transistor are arranged in a staggered manner in the first direction and the second direction;
in each scanning driving unit of the second region, the charge transistor and the discharge transistor are arranged side by side in the second direction;
in each scan driving unit of the third region, the charge transistor and the discharge transistor are arranged side by side in the first direction.
7. The display panel according to any one of claims 2 to 5, wherein the peripheral region further includes a common potential signal circuit; the common potential signal circuit is arranged around the special-shaped display area and is positioned between the scanning driving circuit and the fan-out area wiring.
8. The display panel of any one of claims 1-5, wherein the peripheral region further comprises an encapsulation layer, the encapsulation layer is located on a side of the scan driving circuit facing away from the special-shaped display region, and a distance between a cutting edge of the peripheral region and a side of the encapsulation layer facing away from the scan driving circuit is less than 10 μm.
9. The display panel according to any one of claims 1 to 5, wherein the scan driving circuit includes a plurality of metal layers stacked one on another, and patterns located in different ones of the metal layers are connected by a single via.
10. A display device comprising the display panel according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311039529.XA CN117037733A (en) | 2023-08-17 | 2023-08-17 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311039529.XA CN117037733A (en) | 2023-08-17 | 2023-08-17 | Display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117037733A true CN117037733A (en) | 2023-11-10 |
Family
ID=88602059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311039529.XA Pending CN117037733A (en) | 2023-08-17 | 2023-08-17 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117037733A (en) |
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2023
- 2023-08-17 CN CN202311039529.XA patent/CN117037733A/en active Pending
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