CN113299334B - Shift register circuit and display device - Google Patents
Shift register circuit and display device Download PDFInfo
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- CN113299334B CN113299334B CN202110726948.5A CN202110726948A CN113299334B CN 113299334 B CN113299334 B CN 113299334B CN 202110726948 A CN202110726948 A CN 202110726948A CN 113299334 B CN113299334 B CN 113299334B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The embodiment of the invention discloses a shift register circuit and a display device, wherein the shift register circuit comprises a multi-stage shift register; the shift register comprises an input module, a voltage division module, a pull-down module and an output module; the input module is started in the input stage, and outputs a first voltage signal provided by a first voltage signal end to a first node; the voltage division module is internally provided with a second node and is connected between the first voltage signal end and the second voltage signal end, and the voltage division module is used for adjusting the potential of the second node; the control end of the pull-down module is connected with the second node, and the potential of the first node and the potential of the output end of the shift register are pulled down when the pull-down module is started; the output module is connected between the first clock signal end and the output end of the shift register, is started in the output stage, and outputs the first clock signal provided by the first clock signal end to the output end of the shift register. The technical scheme of the embodiment of the invention can simplify the structure of the shift register and realize a narrow frame.
Description
Technical Field
The embodiment of the invention relates to a display technology, in particular to a shift register circuit and a display device.
Background
With the continuous development of display technology, the application of display panels is also becoming more and more widespread, for example, the display panels are applied to products such as mobile phones, computers, tablet computers, electronic books, information inquiry machines, and the like, and in addition, the display panels can be applied to instrument displays (for example, vehicle-mounted displays), control panels of smart home, and the like.
The conventional display panel scans pixels of each row line by a shift register circuit, thereby displaying a picture. The shift register circuit comprises a plurality of shift registers which are cascaded, and the shift registers realize the progressive scanning function through the circuit structure of a plurality of transistors and capacitors. The shift register circuit is usually disposed at the left and right frames of the display panel, and signal lines are required to be provided in addition to the circuit elements, so as to transmit signals such as voltage signals and clock signals to each stage of shift register.
If the number of transistors in the shift register is large, the number of signal lines may also increase, which is not beneficial to implementation of the narrow frame.
Disclosure of Invention
The embodiment of the invention provides a shift register circuit and a display device, which realize a narrow frame by simplifying the structure of a shift register.
In a first aspect, an embodiment of the present invention provides a shift register circuit, including: a multi-stage shift register; the shift register comprises an input module, a voltage division module, a pull-down module and an output module;
The input module is connected between the first voltage signal end and the first node and is used for being started in an input stage so as to output a first voltage signal provided by the first voltage signal end to the first node;
the voltage division module is internally provided with a second node, is connected between the first voltage signal end and the second voltage signal end, and is used for adjusting the potential of the second node;
the control end of the pull-down module is connected with the second node, the first end of the pull-down module is connected with the first node, the second end of the pull-down module is connected with the output end of the shift register, and the third end of the pull-down module is connected with the second voltage signal end, and is used for pulling down the potential of the first node and the potential of the output end of the shift register when the pull-down module is started;
the output module is connected between the first clock signal end and the output end of the shift register, and is coupled with a coupling capacitor between the output end of the shift register and the first node, and the output module is used for being started in the output stage so as to output the first clock signal provided by the first clock signal end to the output end of the shift register.
In a second aspect, an embodiment of the present invention further provides a display apparatus, including: the shift register circuit provided in the above aspect.
In the shift register circuit provided by the embodiment of the invention, the shift register comprises an input module, a voltage division module, a pull-down module and an output module; the input module is used for starting in an input stage and outputting a first voltage signal provided by the first voltage signal end to a first node; the voltage division module is internally provided with a second node and is used for adjusting the potential of the second node; the control end of the pull-down module is connected with the second node and is used for pulling down the potential of the first node and the potential of the output end of the shift register when the pull-down module is started; the output module is used for being started in the output stage, and outputting a first clock signal provided by the first clock signal end to the output end of the shift register.
Drawings
FIG. 1 is a circuit diagram of a shift register of the prior art;
FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a driving timing of a shift register according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a shift register in a first pull-down stage according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a shift register in an input stage according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a shift register in an output stage according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a shift register in a second pull-down stage according to an embodiment of the present invention;
FIG. 9 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a partial structure of a shift register according to an embodiment of the present invention;
FIG. 11 is a schematic diagram showing a partial structure of another shift register according to an embodiment of the present invention;
FIG. 12 is a schematic diagram showing a partial structure of another shift register according to an embodiment of the present invention;
fig. 13 is a schematic diagram of a shift register circuit according to an embodiment of the present invention;
FIG. 14 is a schematic diagram showing a driving timing of a shift register circuit according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings.
For example, fig. 1 is a schematic circuit diagram of a shift register in the prior art, as shown in fig. 1, a shutdown module 01 is provided in the conventional shift register, and the shutdown module 01 is further separately provided with a signal line BW, which results in a larger occupied area of the shift register circuit, and is not beneficial to realizing a narrow frame.
In order to solve the above problems, an embodiment of the present application provides a shift register circuit, including a multi-stage shift register; the shift register comprises an input module, a voltage division module, a pull-down module and an output module; the input module is connected between the first voltage signal end and the first node and is used for being started in an input stage so as to output a first voltage signal provided by the first voltage signal end to the first node; the voltage division module is internally provided with a second node, is connected between the first voltage signal end and the second voltage signal end, and is used for adjusting the potential of the second node; the control end of the pull-down module is connected with the second node, the first end of the pull-down module is connected with the first node, the second end of the pull-down module is connected with the output end of the shift register, and the third end of the pull-down module is connected with the second voltage signal end, and is used for pulling down the potential of the first node and the potential of the output end of the shift register when the pull-down module is started; the output module is connected between the first clock signal end and the output end of the shift register, and is coupled with a coupling capacitor between the output end of the shift register and the first node, and the output module is used for being started in the output stage so as to output the first clock signal provided by the first clock signal end to the output end of the shift register.
By adopting the technical scheme, the progressive scanning function of the shift register circuit on the pixel array can be realized, compared with the prior art, the switching-off module is not required, and a signal wire connected with the switching-off module can be omitted, so that the occupied space is smaller, and the narrow frame is facilitated.
The above is the core idea of the application, and based on the embodiments of the application, all other embodiments obtained by a person skilled in the art without making any inventive effort are within the scope of the application. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
The present embodiment provides a shift register circuit including a multi-stage shift register. Fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present application, and as shown in fig. 2, a shift register 100 includes an input module 10, a voltage dividing module 20, a pull-down module 30, and an output module 40. The input module 10 is connected between the first voltage signal terminal VGH and the first node P, and is configured to be turned on during an input stage to output a first voltage signal provided by the first voltage signal terminal VGH to the first node P. The voltage dividing module 20 has a second node Q inside, the voltage dividing module 20 is connected between the first voltage signal end VGH and the second voltage signal end VGL, a first control end of the voltage dividing module 20 is connected to the first shift register signal end gn+1, a second control end is connected to the second shift register signal end Gn-1, and a third control end is connected to the first node P, and the voltage dividing module 20 is used for adjusting the potential of the second node Q. The control terminal of the pull-down module 30 is connected to the second node Q, the first terminal of the pull-down module 30 is connected to the first node P, the second terminal is connected to the output terminal OUT of the shift register, and the third terminal is connected to the second voltage signal terminal VGL, for pulling down the potential of the first node P and the potential of the output terminal OUT of the shift register when turned on. The output module 40 is connected between the first clock signal terminal CLK and the output terminal OUT of the shift register, and a coupling capacitor C is coupled between the output terminal OUT of the shift register and the first node P, and the output module 40 is turned on during the output stage to output the first clock signal provided by the first clock signal terminal CLK to the output terminal OUT of the shift register.
The shift register circuit comprises a plurality of stages of shift registers, and each stage of shift registers can sequentially provide scanning signals for corresponding grid lines.
In this embodiment, the shift register includes a voltage division module 20, wherein a second node Q is disposed in the voltage division module 20 and is connected between the first voltage signal terminal VGH and the second voltage signal terminal VGL, a first control terminal of the voltage division module 20 is connected to the first shift register signal terminal gn+1, a second control terminal is connected to the second shift register signal terminal Gn-1, and a third control terminal is connected to the first node P for adjusting the potential of the second node Q. Specifically, the voltage dividing module 20 may include a plurality of transistors, and through the first shift register signal terminal gn+1, the second shift register signal terminal Gn-1, and the potential of the first node P, the on-off state of the transistors between the first voltage signal terminal VGH and the second node Q and between the second node Q and the second voltage signal terminal VGL may be controlled, so that the first voltage signal of the first voltage signal terminal VGH may be output to the second node Q, or the second voltage signal of the second voltage signal terminal VGL may be output to the second node Q, so as to realize the adjustment of the potential of the second node Q. For example, when the first voltage signal terminal VGH is in an on state and the second node Q is in an off state, the voltage dividing module 20 outputs the first voltage signal of the first voltage signal terminal VGH to the second node Q; when the first voltage signal terminal VGH and the second node Q are in the on state, and the second node Q and the second voltage signal terminal VGL are in the on state, the voltage dividing module 20 outputs the first voltage signal of the second voltage signal terminal VGL to the second node Q.
Further, in the present embodiment, the control end of the pull-down module 30 is connected to the second node Q, so that the on-off state of the pull-down module 30 is different when the second node Q is at different electric potentials. Specifically, when the potential of the second node Q is in the state of the enabling level, the pull-down module 30 is turned on, so that the second voltage signal of the second voltage signal terminal VGL is transmitted to the first node P and the output terminal OUT of the shift register, and the potential of the first node P and the potential of the output terminal OUT of the shift register are pulled down; when the potential of the second node Q is in the non-enabled level state, the pull-down module 30 is turned off, and the second voltage signal of the second voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register, so that the potential of the first node P and the potential of the output terminal OUT of the shift register are not affected.
Optionally, the working phases of the shift register may include a first pull-down phase and a second pull-down phase; the first pull-down stage is performed before the input stage, and the pull-down module 30 performs a first pull-down operation to pull down the potential of the first node P and the potential of the output terminal OUT of the shift register; the second pull-down stage is performed after the output stage, and the pull-down module 30 performs a second pull-down operation to pull down the potential of the first node P and the potential of the output terminal OUT of the shift register.
Specifically, in the first pull-down stage, under the control of the enable level of the second node Q, the pull-down module 30 is turned on to transmit the second voltage signal of the second voltage signal terminal VGL to the first node P and the output terminal OUT of the shift register, and pull down the potential of the first node P and the potential of the output terminal OUT of the shift register.
In the input stage, under the control of the enable level of the second shift register signal terminal Gn-1, the input module 10 is turned on to transmit the first voltage signal of the first voltage signal terminal VGH to the first node P, and charge the first node P. At this time, the voltage dividing module 20 can adjust the potential of the second node Q to be in a state of non-enabling level, and the pull-down module 30 is turned off, so that the second voltage signal of the second voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register.
In the output stage, since the coupling capacitor C stores the potential of the first node P, the potential of the first node P is maintained in the state of the enable level, and the output module 40 is turned on under the control of the potential of the first node P, outputs the first clock signal provided by the first clock signal terminal CLK to the output terminal OUT of the shift register, and provides the scan signal to the corresponding gate line. At this time, the voltage dividing module 20 can adjust the potential of the second node Q to be in a state of non-enabling level, and the pull-down module 30 is turned off, so that the second voltage signal of the second voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register.
In the second pull-down stage, the pull-down module 30 is turned on under the control of the enable level of the second node Q, and transmits the second voltage signal of the second voltage signal terminal VGL to the first node P and the output terminal OUT of the shift register, and pulls down the potential of the first node P and the potential of the output terminal OUT of the shift register.
The working process of one period of the shift register is ended until the potential of the next second shift register signal end Gn-1 is in the state of enabling level, and the working process of the next period is started.
In the shift register circuit provided by the embodiment of the invention, the shift register comprises an input module, a voltage division module, a pull-down module and an output module; the input module is used for starting in an input stage and outputting a first voltage signal provided by the first voltage signal end to a first node; the voltage division module is internally provided with a second node and is used for adjusting the potential of the second node; the control end of the pull-down module is connected with the second node and is used for pulling down the potential of the first node and the potential of the output end of the shift register when the pull-down module is started; the output module is used for being started in the output stage, and outputting a first clock signal provided by the first clock signal end to the output end of the shift register.
Fig. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present invention, referring to fig. 3, optionally, the input module 10 includes a first transistor T1; the first transistor T1 is connected between the first voltage signal terminal VGH and the first node P, and the control terminal of the first transistor T1 is connected to the second shift register signal terminal Gn-1. In the input stage, the potential of the second shift register signal terminal Gn-1 is in the state of the enabling level, the first transistor T1 is turned on, and the first voltage signal of the first voltage signal terminal VGH is transmitted to the first node P to charge the first node P.
With continued reference to fig. 3, the output module 40 optionally includes a second transistor T2; the second transistor T2 is connected between the first clock signal terminal CLK and the output terminal OUT of the shift register, and the control terminal of the second transistor T2 is connected to the first node P. In the output stage, the potential of the first node P is in the state of the enable level, the second transistor T2 is turned on, the first clock signal provided by the first clock signal terminal CLK is transmitted to the output terminal OUT of the shift register, and the scan signal is provided to the corresponding gate line.
Referring to fig. 2, the voltage dividing module 20 may optionally include a first voltage dividing unit 21 and a second voltage dividing unit 22; the first voltage dividing unit 21 is connected between the first voltage signal terminal VGH and the second node Q, and a first control terminal of the first voltage dividing unit 21 is connected to the first shift register signal terminal gn+1; the second voltage division unit 22 is connected between the second voltage signal end VGL and the second node Q, and the first control end of the second voltage division unit 22 is connected to the second shift register signal end Gn-1, and the second control end of the second voltage division unit 22 is connected to the first node P; the first voltage dividing unit 21 is configured to output a first voltage signal to the second node Q when turned on; the second voltage dividing unit 22 is configured to output the second voltage signal provided by the second voltage signal terminal VGL to the second node Q when turned on.
The first control end of the first voltage division unit 21 is a first control end of the voltage division module 20, and the first control end of the first voltage division unit 21 is connected to the first shift register signal end gn+1; the first control end of the second voltage division unit 22 is a second control end of the voltage division module 20, and the first control end of the second voltage division unit 22 is connected to the second shift register signal end Gn-1; the second control end of the second voltage division unit 22 is a third control end of the voltage division module 20, and the second control end of the second voltage division unit 22 is connected to the first node P and is used for controlling the on-off states of the first voltage division unit 21 and the second voltage division unit 22 respectively.
Wherein, the first voltage dividing unit 21 is used for outputting a first voltage signal to the second node Q when being started; the second voltage dividing unit 22 is configured to output the second voltage signal provided by the second voltage signal terminal VGL to the second node Q when turned on. Specifically, when the first voltage dividing unit 21 is turned on and the second voltage dividing unit 22 is turned off, the first voltage signal of the first voltage signal terminal VGH is output to the second node Q, and the potential of the second node Q is pulled up; when the second voltage dividing unit 22 is turned on, the second voltage signal of the second voltage signal terminal VGL is output to the second node Q, and the potential of the second node Q is pulled down.
Referring to fig. 3, optionally, the first voltage dividing unit 21 includes a third transistor T3 and a fourth transistor T4, the third transistor T3 and the fourth transistor T4 are both connected between the first voltage signal terminal VGH and the second node Q, the control terminal of the third transistor T3 is connected to the first shift register signal terminal gn+1, and the control terminal of the fourth transistor T4 is connected to the first voltage signal terminal VGH; the second voltage dividing unit 22 includes a fifth transistor T5 and a sixth transistor T6, wherein the fifth transistor T5 and the sixth transistor T6 are both connected between the second voltage signal terminal VGL and the second node Q, the control terminal of the fifth transistor T5 is connected to the second shift register signal terminal Gn-1, and the control terminal of the sixth transistor T6 is connected to the first node P. Specifically, when the third transistor T3 and/or the fourth transistor T4 are turned on, the first voltage dividing unit 21 is turned on, and when the fifth transistor T5 and/or the sixth transistor T6 are turned on, the second voltage dividing unit 22 is turned on.
Referring to fig. 2, the pull-down module 30 may optionally include a first pull-down unit 31 and a second pull-down unit 32; the first pull-down unit 31 is connected between the first node P and the second voltage signal terminal VGL, and the control terminal of the first pull-down unit 31 is connected to the second node Q; the second pull-down unit 32 is connected between the output terminal OUT of the shift register and the second voltage signal terminal VGL, and the control terminal of the second pull-down unit 32 is connected to the second node Q; the first pull-down unit 31 and the second pull-down unit 32 are turned on or off simultaneously, and when turned on, pull down the potential of the first node P and the potential of the output terminal OUT of the shift register to the second voltage signal provided by the second voltage signal terminal VGL.
The control terminal of the first pull-down unit 31 and the control terminal of the second pull-down unit 32 are both connected to the second node Q, so that when the potential of the second node Q is in the state of the enabling level, the first pull-down unit 31 and the second pull-down unit 32 are simultaneously turned on to pull down the potential of the first node P and the potential of the output terminal OUT of the shift register to the second voltage signal provided by the second voltage signal terminal VGL; when the potential of the second node Q is in the disabled state, the first pull-down unit 31 and the second pull-down unit 32 are turned off at the same time, and the second voltage signal of the second voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register.
Referring to fig. 3, the first pull-down unit 31 includes a seventh transistor T7, and the second pull-down unit 32 includes an eighth transistor T8. The control terminal of the seventh transistor T7 and the control terminal of the eighth transistor T8 are electrically connected to the second node Q, the seventh transistor T7 is connected between the first node P and the second voltage signal terminal VGL, and the eighth transistor T8 is connected between the output terminal OUT of the shift register and the second voltage signal terminal VGL.
Optionally, the width-to-length ratio of the seventh transistor T7 is greater than the width-to-length ratio of the transistor M2 of the prior art (fig. 1).
In contrast to fig. 1 and 3, in the prior art (fig. 1), the first node P is connected to the signal terminal BW through the transistor M1 and connected to the signal terminal VGL through the transistor M2, and the signal terminal BW is at a low level during forward scanning, so that the first node P leaks to the low level terminal through the transistors M1 and M2 based on the characteristics of the transistors. In the present embodiment (fig. 3), the first node P is connected to the second voltage signal terminal VGL through the seventh transistor T7, and therefore, the first node P leaks electricity to the second voltage signal terminal VGL through the seventh transistor T7. In order to ensure that the leakage amount and the leakage current of the first node P are consistent with those of the prior art in this embodiment, so as to ensure the performance stability of the shift register, the leakage current of the seventh transistor T7 needs to be equal to the sum of the leakage currents of the transistors M1 and M2, and therefore, the resistance of the seventh transistor T7 needs to be reduced. In this embodiment, by setting the width-to-length ratio of the seventh transistor T7 to be greater than that of the transistor M2 in the prior art (fig. 1), the resistance of the seventh transistor T7 is reduced in a manner of increasing the width-to-length ratio of the seventh transistor T7, so as to ensure that the leakage amount and the leakage current of the first node P in this embodiment are consistent with those in the prior art, and ensure the performance stability of the shift register.
The transistors in the shift register may be, for example, NMOS transistors, where the enable level of the output signal of each signal terminal is high, the disable level is low, the first voltage signal provided by the first voltage signal terminal VGH is a high level signal greater than 0V, and the second voltage signal provided by the second voltage signal terminal VGL is a low level signal less than or equal to 0V. Accordingly, fig. 4 is a schematic diagram of a driving timing sequence of a shift register according to an embodiment of the present invention, referring to fig. 4, a working process of the shift register includes a first pull-down stage S1, an input stage S2, an output stage S3, and a second pull-down stage S4.
Fig. 5 is a schematic diagram of the shift register in the first pull-down stage according to the embodiment of the present invention, and in combination with fig. 4 and fig. 5, in the first pull-down stage S1, the first voltage signal of the first voltage signal terminal VGH is at a high level, and the fourth transistor T4 is turned on; the initial potential of the first node P is low, so that the sixth transistor T6 is turned off, and at the same time, since the first shift register signal of the first shift register signal terminal gn+1 is low, the second shift register signal of the second shift register signal terminal Gn-1 is low, so that both the third transistor T3 and the fifth transistor T5 are turned off, the first voltage signal of the first voltage signal terminal VGH is transmitted to the second node Q through the fourth transistor T4, and the potential of the second node Q is pulled up. Further, since the potential of the second node Q increases, the seventh transistor T7 and the eighth transistor T8 are turned on, and the potential of the first node P and the potential of the output terminal OUT of the shift register are pulled down to the second voltage signal provided by the second voltage signal terminal VGL.
Fig. 6 is a schematic diagram of the shift register in the input stage according to the embodiment of the invention, and in combination with fig. 4 and 6, in the input stage S2, the input module 10 (T1), the second voltage dividing unit 22 (T5 and T6) and the fourth transistor T4 are all turned on, the first voltage signal (VGH) is written into the first node P, and the second voltage signal (VGL) is written into the second node Q. Specifically, in the input stage S2, the second shift register signal of the second shift register signal terminal Gn-1 is at a high level, so that the first transistor T1 and the fifth transistor T5 are turned on, the first voltage signal provided by the first voltage signal terminal VGH is transmitted to the first node P through the first transistor T1, so as to charge the first node P and pull up the potential of the first node P. Meanwhile, as the potential of the first node P increases, the sixth transistor T6 is turned on, and the second voltage signal of the second voltage signal terminal VGL is transmitted to the second node Q through the fifth transistor T5 and the sixth transistor T6, so that the potential of the second node Q can be quickly pulled down, and further the seventh transistor T7 and the eighth transistor T8 are turned off, so that the potential of the first node P is prevented from being pulled down due to abnormal turn-on of the seventh transistor T7 and the eighth transistor T8 in the input stage S2.
Fig. 7 is a schematic diagram of the shift register in the output stage according to the embodiment of the present invention, and in conjunction with fig. 4 and fig. 7, in the output stage S3, the output module 40 (T2), the fourth transistor T4 and the sixth transistor T6 are all turned on, and the first clock signal provided by the first clock signal terminal CLK is output to the output terminal OUT of the shift register. Specifically, in the output stage S3, the potential of the first node P is kept high due to the coupling capacitor C, so that the second transistor T2 is turned on, and the first clock signal of the first clock signal terminal CLK is transmitted to the output terminal OUT of the shift register through the second transistor T2. Meanwhile, since the first node P is at a high level, the sixth transistor T6 is turned on, the second voltage signal of the second voltage signal terminal VGL is transmitted to the second node Q through the sixth transistor T6, and the potential of the second node Q is pulled down, so that the seventh transistor T7 and the eighth transistor T8 are turned off, and the second voltage signal of the second voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register.
Fig. 8 is a schematic diagram of a shift register in a second pull-down stage according to an embodiment of the present invention, in conjunction with fig. 4 and 8, in the second pull-down stage S4, the first shift register signal of the first shift register signal terminal gn+1 is at a high level, so that the third transistor T3 is turned on, and meanwhile, the fourth transistor T4 is turned on, and in addition, the output stage S3 discharges the coupling capacitor C, so that the potential of the first node P is reduced, and therefore, the sixth transistor T6 is turned off, and meanwhile, since the second shift register signal of the second shift register signal terminal Gn-1 is at a low level, the fifth transistor T5 is turned off, so that the first voltage signal of the first voltage signal terminal VGH can be transmitted to the second node Q through the third transistor T3 and the fourth transistor T4, so that the potential of the second node Q is rapidly pulled up, and further, the seventh transistor T7 and the eighth transistor T8 are turned on, so that the second voltage signal of the second voltage signal terminal VGL is transmitted to the first node P and the output terminal OUT of the shift register are turned on, and the output of the shift register is prevented from influencing the potential of the normal output of the shift register.
Fig. 9 is a circuit schematic diagram of another shift register according to an embodiment of the present invention, referring to fig. 9, optionally, the shift register 100 further includes: the reset module 50 is connected between the first node P and the second voltage signal terminal VGL, and is configured to be turned on in a reset phase, so that the first node P is reset to the second voltage signal provided by the second voltage signal terminal VGL.
Static electricity may be accumulated on the first node P, and before the input stage S2, the static electricity needs to be released, so as to avoid that residual static electricity on the first node P affects an output signal of the shift register, and affects a display effect. Since the duration of the first pull-down stage S1 is generally shorter, the potential of the first node P may not drop to the second voltage signal provided by the second voltage signal terminal VGL at the beginning of the input stage S2, and the reset module 50 is turned on during the reset stage by setting the reset module 50 in this embodiment, the seventh transistor T7 in the pull-down module 30 can be assisted to quickly reset the potential of the first node P to the second voltage signal provided by the second voltage signal terminal VGL, so that static electricity on the first node P can be eliminated, and the output signal of the shift register is ensured to be normal, thereby ensuring the display effect.
Alternatively, the reset phase may be located after the first pull-down phase S1 and before the input phase S2; alternatively, the reset phase may overlap the first pull-down phase S1; alternatively, the reset phase may partially overlap the first pull-down phase S1, and the start time of the first pull-down phase S1 is located before the reset phase.
For example, referring to fig. 9, the RESET module 50 may include a ninth transistor T9, the ninth transistor T9 being connected between the first node P and the second voltage signal terminal VGL, a gate of the ninth transistor T9 being connected to the RESET signal terminal RESET, the ninth transistor T9 being turned on when a potential of the RESET signal terminal RESET is in a state of an enable level, the potential of the first node P being RESET to the second voltage signal supplied from the second voltage signal terminal VGL.
Similarly, referring to fig. 9, the shift register 100 may further include: the initialization module 60, the initialization module 60 is connected between the output terminal OUT of the shift register and the second voltage signal terminal VGL, and is used for being turned on in an initialization stage to initialize the output terminal OUT of the shift register to the second voltage signal (VGL).
In this embodiment, the initialization module 60 is set to be turned on in the initialization stage, so as to assist the eighth transistor T8 in the pull-down module 30 to rapidly initialize the output terminal OUT of the shift register to the second voltage signal (VGL) before the input stage S2, thereby avoiding the influence on the output signal caused by the residual static electricity at the output terminal OUT of the shift register and ensuring the normal display effect.
Alternatively, the initialization phase may be located after the first pull-down phase S1 and before the input phase S2; alternatively, the initialization phase may overlap with the first pull-down phase S1; alternatively, the initialization phase may partially overlap the first pull-down phase S1, and the start time of the first pull-down phase S1 is located before the initialization phase.
For example, referring to fig. 9, the initialization module 60 may include a tenth transistor T10, the tenth transistor T10 being connected between the output terminal OUT of the shift register and the second voltage signal terminal VGL, a gate of the tenth transistor T10 being connected to the initialization signal terminal GOFF, the tenth transistor T10 being turned on when a potential of the initialization signal terminal GOFF is in a state of an enable level, the potential of the output terminal OUT of the shift register being initialized to the second voltage signal supplied from the second voltage signal terminal VGL.
In addition, referring to fig. 9, by setting the reset module 50 and the initialization module 60, in the case that the second node Q fails (e.g., the potential is low), the seventh transistor T7 and the eighth transistor T8 cannot be normally turned on, the reset module 50 is used to pull down the potential of the first node P to the second voltage signal provided by the second voltage signal terminal VGL, and the initialization module 60 is used to pull down the potential of the output terminal OUT of the shift register to the second voltage signal provided by the second voltage signal terminal VGL, so as to replace the pull-down module 30 to realize the functions of the shift register in the first pull-down stage S1 and the second pull-down stage S4, thereby ensuring that the shift register can normally operate.
Optionally, the time periods of the reset phase and the initialization phase at least partially overlap. By the arrangement, the grid scanning time of the shift register can be reduced, the scanning frequency of the display device can be improved, and high resolution can be realized.
In summary, the above embodiments describe the circuit structure of the shift register in detail, and the following describes the film structure of the shift register.
Fig. 10 is a schematic diagram of a partial structure of a shift register according to an embodiment of the present invention, referring to fig. 10, optionally, the shift register circuit further includes: the gate metal layer, the source drain metal layer and the first metal layer are arranged in different layers, and the first metal layer comprises a first bridge structure 101; the gate electrode of the second transistor T2 and the first node P are connected to the same first bridge structure 101 by using a first bridge line-changing hole, and the gate metal layer and the metal layer where the first node P is located are disposed in different layers.
Referring to fig. 10, the film layer where the gate 201 of the second transistor T2 is located is a gate metal layer, the film layers where the source 202 and the drain 203 of the second transistor T2 are located is a source drain metal layer, and the film layer where the first bridge structure 101 is located is a first metal layer.
As shown in fig. 9, the first node P is connected to the gate of the second transistor T2, the gate of the sixth transistor T6, the drain of the seventh transistor T7 and the drain of the ninth transistor T9 at the same time, and the gate and the source drain of the transistors are located in different metal layers, so that a bridge structure is required to connect the metal structures located in different layers, that is, the gates of the second transistor T2 and the sixth transistor T6 and the drains of the seventh transistor T7 and the ninth transistor T9 are connected to the first node P.
As shown in fig. 10, the first node P is optionally co-layered with the source drain metal layer. In this way, the metal layer where the first node P is located is the same layer as the source and drain of the seventh transistor T7 and the ninth transistor T9, and is different from the gate of the second transistor T2 and the sixth transistor T6, and the gate of the second transistor T2 may be connected to the first node P through the first bridge structure 101. As for the metal structure of the same layer, it can be connected with the film layer where it is.
The above structure is merely an example, and is not limited thereto, and in other embodiments, the metal layer where the optional first node P is located is the same layer as the gate metal layer, and the drains of the first node P and the ninth transistor T9 are connected through a bridge structure, which can be set by those skilled in the art according to practical situations.
Similarly, fig. 11 is a schematic diagram of a partial structure of another shift register according to an embodiment of the present invention, and referring to fig. 9 and fig. 11, optionally, the first metal layer includes a second bridge structure 102; the gate 401 of the fourth transistor T4 and the source 402 of the fourth transistor T4 are connected to the same second bridge structure 102 using a second bridge tap.
Fig. 12 is a schematic view of a partial structure of another shift register according to an embodiment of the present invention, and referring to fig. 9 and fig. 12, an optional first metal layer includes a third bridge structure 103; the gate 701 and the second node Q of the seventh transistor T7 are connected to the same third bridge structure 103 by using a third bridge line-changing hole, and the gate metal layer and the metal layer where the second node Q is located are disposed in different layers. Optionally, the second node Q is in the same layer as the source drain metal layer. As shown in fig. 12, the second node Q is arranged in the same layer as the source 702 and the drain 703 of the seventh transistor T7.
The above structure is merely an example, and is not limited thereto, and in other embodiments, the metal layer where the second node Q is located and the gate metal layer are the same, and the source of the third transistor T3 and the second node Q are connected through a bridge structure, which can be set by those skilled in the art according to practical situations.
The specific design principle of the structure shown in fig. 11 and 12 is shown in fig. 10, and will not be described herein. Illustratively, the material of the above-described cross-bridge structure may be Indium Tin Oxide (ITO).
Because the metal layer where the bridge structure is located is closer to the upper surface of the display panel, under the high-temperature and high-humidity environment, if moisture in the environment enters the inside of the display panel, the bridge structure is easy to corrode and break, and abnormal screen display is caused. In fig. 1 and fig. 9, two circular dashed boxes and the dashed lines therebetween represent a bridge structure, and comparing fig. 1 and fig. 9, it can be seen that, in this embodiment, by removing the shutdown module 01 in the prior art, the number of bridge structures can be reduced, and the probability of occurrence of line corrosion can be reduced.
In summary, the above embodiments briefly describe the film structure of the shift register, and the connection relationship between each stage of the shift register in the shift register circuit is described below.
Fig. 13 is a schematic diagram of a shift register circuit according to an embodiment of the present invention, referring to fig. 13, in the shift register circuit 200, a first shift register signal terminal gn+1 is connected to an output terminal OUT of a next stage shift register, and a second shift register signal terminal Gn-1 is connected to an output terminal OUT of a previous stage shift register, so as to implement cascading of the multi-stage shift register 100.
Fig. 14 is a schematic diagram of a driving sequence of a shift register circuit according to an embodiment of the present invention, referring to fig. 13 and 14, an input signal end STV is connected to a second shift register signal end Gn-1 of a first stage shift register circuit ASG1, and is used for triggering the first stage shift register ASG1 to enter an input stage S2, and the working process of the shift register is not described herein. When the output terminal OUT1 of the first stage shift register ASG1 outputs a scan signal to the corresponding gate line, the output signal is transmitted to the second shift register signal terminal Gn-1 of the second stage shift register ASG2, so that the second stage shift register ASG2 enters the input stage S2, and then, when the output terminal OUT2 of the second stage shift register ASG2 outputs a scan signal to the corresponding gate line, the output signal thereof can be simultaneously transmitted to the first shift register signal terminal gn+1 of the first stage shift register ASG1 and the second shift register signal terminal Gn-1 of the third stage shift register ASG3, so that the first stage shift register ASG1 enters the second pull-down stage S4, and the third stage shift register ASG3 enters the input stage S2 … …. By analogy, the multi-stage shift register 100 in the shift register circuit 200 can sequentially output scanning signals to the corresponding gate lines, so as to realize progressive scanning of the pixel array.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 15 is a schematic structural diagram of the display device provided in the embodiment of the present invention, where the display device 300 includes the shift register circuit provided in any one of the embodiments, and the shift register circuit may be located in non-display areas on the left and right sides of the display area AA. The display device has the same advantages as the shift register circuit, and the same points can be referred to the description of the embodiment of the shift register circuit, and the description is omitted herein. The display device 300 provided in the embodiment of the present invention may be a mobile phone as shown in fig. 15, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (21)
1. A shift register circuit, comprising: a multi-stage shift register;
the shift register comprises an input module, a voltage division module, a pull-down module and an output module;
the input module is connected between a first voltage signal end and a first node and is used for being started in an input stage so as to output a first voltage signal provided by the first voltage signal end to the first node;
the voltage division module is connected between the first voltage signal end and the second voltage signal end, a first control end of the voltage division module is connected with the first shift register signal end, a second control end of the voltage division module is connected with the second shift register signal end, a third control end of the voltage division module is connected with the first node, and the voltage division module is used for adjusting the potential of the second node;
the control end of the pull-down module is connected with the second node, the first end of the pull-down module is connected with the first node, the second end of the pull-down module is connected with the output end of the shift register, and the third end of the pull-down module is connected with the second voltage signal end, and is used for pulling down the potential of the first node and the potential of the output end of the shift register when the pull-down module is started;
The output module is connected between a first clock signal end and an output end of the shift register, a coupling capacitor is coupled between the output end of the shift register and the first node, and the output module is used for being started in an output stage so as to output a first clock signal provided by the first clock signal end to the output end of the shift register.
2. The shift register circuit according to claim 1, wherein the first shift register signal terminal is connected to an output terminal of the shift register of a next stage, and the second shift register signal terminal is connected to an output terminal of the shift register of a previous stage.
3. The shift register circuit according to claim 1 or 2, wherein the input module comprises a first transistor;
the first transistor is connected between the first voltage signal end and the first node, and the control end of the first transistor is connected with the second shift register signal end.
4. The shift register circuit of claim 1, wherein the output module comprises a second transistor;
the second transistor is connected between the first clock signal end and the output end of the shift register, and the control end of the second transistor is connected with the first node.
5. The shift register circuit of claim 4, further comprising: the semiconductor device comprises a grid electrode metal layer, a source drain electrode metal layer and a first metal layer, wherein the grid electrode metal layer, the source drain electrode metal layer and the first metal layer are arranged in different layers, and the first metal layer comprises a first bridge-crossing structure;
the grid electrode of the second transistor and the first node are connected to the same first bridge structure by adopting a first bridge line changing hole, and the grid electrode metal layer and the metal layer where the first node is arranged are arranged in different layers.
6. The shift register circuit of claim 5, wherein said first node is co-layer with said source drain metal layer.
7. The shift register circuit according to claim 1, wherein the voltage dividing module comprises a first voltage dividing unit and a second voltage dividing unit;
the first voltage dividing unit is connected between the first voltage signal end and the second node, and a first control end of the first voltage dividing unit is connected with the first shift register signal end;
the second voltage division unit is connected between the second voltage signal end and the second node, and the first control end of the second voltage division unit is connected with the second shift register signal end;
The first voltage dividing unit is used for outputting the first voltage signal to the second node when the first voltage dividing unit is started;
and the second voltage division unit is used for outputting a second voltage signal provided by the second voltage signal end to the second node when the second voltage division unit is started.
8. The shift register circuit as claimed in claim 7, wherein,
the first voltage dividing unit comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor are both connected between the first voltage signal end and the second node, the control end of the third transistor is connected with the first shift register signal end, and the control end of the fourth transistor is connected with the first voltage signal end;
the second voltage division unit comprises a fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor are both connected between the second voltage signal end and the second node, the control end of the fifth transistor is connected with the second shift register signal end, and the control end of the sixth transistor is connected with the first node.
9. The shift register circuit of claim 8, wherein in the input stage, the input module, the second voltage dividing unit, and the fourth transistor are all turned on, the first voltage signal is written to the first node, and the second voltage signal is written to the second node.
10. The shift register circuit according to claim 8, wherein in the output stage, the output module, the fourth transistor and the sixth transistor are turned on, and the first clock signal provided by the first clock signal terminal is output to the output terminal of the shift register.
11. The shift register circuit of claim 8, further comprising: the semiconductor device comprises a grid electrode metal layer, a source drain electrode metal layer and a first metal layer, wherein the grid electrode metal layer, the source drain electrode metal layer and the first metal layer are arranged in different layers, and the first metal layer comprises a second bridge-crossing structure;
and the grid electrode of the fourth transistor and the source electrode of the fourth transistor are connected to the same second bridge structure by adopting a second bridge line changing hole.
12. The shift register circuit according to claim 1, wherein the pull-down module includes a first pull-down unit and a second pull-down unit;
the first pull-down unit is connected between the first node and the second voltage signal end, and the control end of the first pull-down unit is connected with the second node;
the second pull-down unit is connected between the output end of the shift register and the second voltage signal end, and the control end of the second pull-down unit is connected with the second node;
And when the first pull-down unit and the second pull-down unit are simultaneously turned on or simultaneously turned off, the potential of the first node and the potential of the output end of the shift register are pulled down to a second voltage signal provided by the second voltage signal end.
13. The shift register circuit as claimed in claim 12, wherein,
the first pull-down unit includes a seventh transistor,
the second pull-down unit includes an eighth transistor.
14. The shift register circuit of claim 13, further comprising: the semiconductor device comprises a grid electrode metal layer, a source drain electrode metal layer and a first metal layer, wherein the grid electrode metal layer, the source drain electrode metal layer and the first metal layer are arranged in different layers, and the first metal layer comprises a third bridge-crossing structure;
and the grid electrode of the seventh transistor and the second node are connected to the same third bridge structure by adopting a third bridge line changing hole, and the grid electrode metal layer and the metal layer where the second node is arranged are arranged in different layers.
15. The shift register circuit of claim 14, wherein the second node is co-layer with the source drain metal layer.
16. The shift register circuit of claim 1, wherein the shift register further comprises: and the reset module is connected between the first node and the second voltage signal end and is used for being started in a reset stage so as to reset the first node to a second voltage signal provided by the second voltage signal end.
17. The shift register circuit of claim 16, wherein the shift register further comprises: the initialization module is connected between the output end of the shift register and the second voltage signal end and is used for starting in an initialization stage so as to initialize the output end of the shift register to the second voltage signal.
18. The shift register circuit of claim 17, wherein the time periods of the reset phase and the initialization phase at least partially overlap.
19. The shift register circuit of claim 1, wherein the operational phase of the shift register comprises a first pull-down phase and a second pull-down phase;
the first pull-down stage is executed before the input stage, the pull-down module executes a first pull-down operation, and pulls down the potential of the output end of the shift register;
the second pull-down stage is executed after the output stage, and the pull-down module executes a second pull-down operation to pull down the potential of the output end of the shift register.
20. The shift register circuit of claim 1, wherein the first voltage signal provided by the first voltage signal terminal is a high level signal greater than 0V, and the second voltage signal provided by the second voltage signal terminal is a low level signal less than or equal to 0V.
21. A display device, comprising: a shift register circuit as claimed in any one of claims 1 to 20.
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