CN113823348B

CN113823348B - Shift register unit, driving method thereof, shift register and display device

Info

Publication number: CN113823348B
Application number: CN202110989790.0A
Authority: CN
Inventors: 金慧俊; 秦丹丹
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2021-08-26
Filing date: 2021-08-26
Publication date: 2023-09-19
Anticipated expiration: 2041-08-26
Also published as: CN113823348A

Abstract

The application discloses a shift register unit, a driving method thereof, a shift register and a display device. The shift register unit comprises an input module, an output module, a first pull-down module, a pull-down control module and a voltage regulating module. The charge amount of the first capacitor in the voltage regulation module is positively correlated with the voltage of the first node, the charge amount of the first capacitor influences the voltage of the third node, the voltage of the third node influences the pull-up degree of the third voltage signal end to the voltage of the second node, and then the pull-down degree of the second voltage signal end to the voltage of the first node is influenced. In other words, through the setting of voltage regulation module, can effectively guarantee the voltage matching degree between first node and the second node, and then help promoting output signal's quality, effectively avoid display panel to show unusual.

Description

Shift register unit, driving method thereof, shift register and display device

Technical Field

The present application relates to a shift register unit, a driving method thereof, a shift register and a display device, and more particularly, to a shift register unit and a display device.

Background

Currently, amorphous silicon gate drive (Amorphous Silicon Gate, ASG) technology has been widely used in the field of display panels. The ASG circuit may perform a line scan driving on the display panel by using an output signal, and after the ASG finishes the scan driving on one frame in the display panel, a blanking (blanking) period is generally entered. In the blanking period, the potential of the pull-up node of the output signal may be pulled down by controlling the pull-down node (typically the gate point of a transistor) of the output signal so that the pull-up node communicates with a low potential.

However, in the related art, due to the influence of factors such as the threshold voltage shift of the transistors in the ASG circuit, a voltage mismatch phenomenon may occur between the pull-up node and the pull-down node, thereby affecting the quality of the output signal and causing abnormal display of the display panel.

Disclosure of Invention

The embodiment of the application provides a shift register unit, a driving method thereof, a shift register and a display device, which are used for solving the problems that the voltages of a pull-up node and a pull-down node are not matched, the quality of an output signal is influenced and the display panel is abnormal in the related art.

In a first aspect, an embodiment of the present application provides a shift register unit, including:

The input module is coupled to the first input signal end, the first voltage signal end and the first node, and is configured to transmit a first voltage signal from the first voltage signal end to the first node under the control of the first input signal end;

the output module is coupled to the clock signal end, the output signal end and the first node and is configured to transmit a clock signal from the clock signal end to the output signal end under the control of the first node;

the first pull-down module is coupled to the first node, the second node and the second voltage signal end and is configured to pull down the potential of the first node through the second voltage signal end under the control of the second node;

the pull-down control module is coupled to the third voltage signal end, the third node and the second node and is configured to pull up the potential of the second node through the third voltage signal end under the control of the third node;

the voltage regulation module comprises a first capacitor, the voltage regulation module is coupled to a second input signal end, a first voltage signal end, a first node and a third node, the voltage regulation module is configured to charge the first end of the first capacitor through the first voltage signal end under the control of the second input signal end, and charge the second end of the first capacitor through the first voltage signal end under the control of the first node and the first input signal end, the charge amount of the first voltage signal end to the second end of the first capacitor is positively correlated with the voltage of the first node, and the first end of the first capacitor is connected with the third node.

In a second aspect, an embodiment of the present application provides a shift register, including: a plurality of stages of shift register units as in the first aspect; wherein,

the first input signal end of the n-th shift register unit is connected with the output signal end of the n-1-th shift register unit; the second input signal end of the n-th shift register unit is connected with the output signal end of the n-2-th shift register unit, and n is an integer greater than 2.

In a third aspect, an embodiment of the present application provides a display device including the shift register as described in the second aspect.

In a fourth aspect, an embodiment of the present application provides a driving method applied to a shift register unit as shown in the first aspect, the method including:

in the first stage, a first input signal end inputs low potential, a second input signal end inputs high potential, and a first end of a first capacitor is charged through a first voltage signal end so as to pull up the potential of a third node;

in the second stage, a high potential is input to the first input signal end, a low potential is input to the second input signal end, the potential of the first node is pulled up through the first voltage signal end, and the second end of the first capacitor is charged through the first voltage signal end so as to further pull up the potential of the third node; the charge quantity of the first voltage signal end to the second end of the first capacitor is positively correlated with the potential of the first node;

In the third stage, the clock signal end inputs high potential so that the output signal end outputs high potential;

in the fourth stage, under the control of the third node, the potential of the second node is pulled up through the third voltage signal terminal; under the control of the second node, the potential of the first node is pulled down through the second voltage signal terminal.

In the shift register unit, the driving method thereof, the shift register and the display device provided by the embodiment of the application, the charge amount of the first capacitor in the voltage regulation module is positively correlated with the voltage of the first node, the charge amount of the first capacitor influences the voltage of the third node, the voltage of the third node influences the pull-up degree of the third voltage signal end on the voltage of the second node, and further influences the pull-down degree of the second voltage signal end on the voltage of the first node. In other words, through the setting of voltage regulation module, can effectively guarantee the voltage matching degree between first node and the second node, and then help promoting output signal's quality, effectively avoid display panel to show unusual.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are needed to be used in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.

FIG. 1 is a schematic diagram of a shift register unit in the related art;

FIG. 2 is a timing diagram of input signals at the signal terminals of the shift register unit shown in FIG. 1;

FIG. 3 is a schematic diagram of a shift register unit according to an embodiment of the present application;

FIG. 4 is a timing diagram of the input signals of the signal terminals of the shift register unit shown in FIG. 3;

FIG. 5 is a schematic diagram of a shift register unit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another embodiment of a shift register unit according to the present application;

FIG. 7 is a schematic diagram of another configuration of a shift register unit according to an embodiment of the present application;

FIG. 8 is a schematic diagram of another configuration of a shift register unit according to an embodiment of the present application;

FIG. 9 is a schematic diagram of another configuration of a shift register unit according to an embodiment of the present application;

FIG. 10 is a schematic diagram of another embodiment of a shift register unit according to the present application;

FIG. 11 is a schematic diagram of another configuration of a shift register unit according to an embodiment of the present application;

FIG. 12 is a schematic diagram showing another configuration of a shift register unit according to an embodiment of the present application;

FIG. 13 is a schematic diagram showing another configuration of a shift register unit according to an embodiment of the present application;

FIG. 14 is a schematic diagram showing another configuration of a shift register unit according to an embodiment of the present application;

FIG. 15 is a schematic diagram showing another configuration of a shift register unit according to an embodiment of the present application;

FIG. 16 is a schematic diagram showing another configuration of a shift register unit according to an embodiment of the present application;

FIG. 17 is a schematic diagram showing another configuration of a shift register unit according to an embodiment of the present application;

fig. 18 is a timing chart of input signals of respective signal terminals of the shift register unit shown in fig. 16 or 17;

FIG. 19 is a schematic diagram of a shift register according to an embodiment of the present application;

FIG. 20 is a schematic diagram of a shift register according to an embodiment of the present application;

fig. 21 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 22 is a schematic flow chart of a driving method according to an embodiment of the present application.

The figure shows: 100-input module, 200-output module, 300-first pull-down module, 400-pull-down control module, 500-voltage regulation module, 600-second pull-down module, 700-third pull-down module, 800-reset module, 900-pull-down charging module.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to illustrate the invention and are not configured to limit the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the invention by showing examples of the invention.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.

Features and exemplary embodiments of various aspects of the application are described in detail below. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The embodiment of the application provides a shift register unit, a driving method thereof, a shift register and a display device. The shift register unit, the driving method thereof, the shift register and the display device according to the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Based on the amorphous silicon gate driving (Amorphous Silicon Gate, ASG) circuit, the function of driving the row scan of the display panel can be realized. In general, an ASG circuit performs progressive scan driving, interlace scan driving, or the like on a display panel, and therefore, the ASG circuit practically corresponds to the function of a shift register.

For example, when the ASG circuit is used for progressive scan driving of the display panel, each row of pixel units in the display panel may be correspondingly configured with a shift register unit.

Fig. 1 is a schematic diagram of a shift register unit, and fig. 2 is a timing diagram of input signals of signal terminals in the shift register unit shown in fig. 1.

The shift register unit shown in fig. 1 mainly includes an input module, an output module, a first pull-down module, a pull-down control module, and a second pull-down module. The input module includes a transistor T '0, the output module includes a transistor T '4 and a capacitor C ', the first pull-down module includes a transistor T '2 and a transistor T '5, the pull-down control module includes a transistor T '7 and a transistor T '8, and the second pull-down module includes a transistor T '3 and a transistor T '6.

The output signal of the shift register unit is denoted Gout. In general, there are a plurality of rows of pixel units in a display panel, and a plurality of shift register units are correspondingly present, and the plurality of shift register units are cascaded to obtain a shift register. Thus, each shift register may correspond to a number of stages, denoted n. The output signal Gout of the n-th shift register unit may be denoted Gn.

Thus, similarly, in fig. 1, the signal terminal shown by Gn-1 may be an output signal for inputting to the n-1 th stage shift register unit; the signal terminal shown in gn+1 may be an output signal for inputting to the n+1th stage shift register unit.

For the remaining signal terminals in fig. 1, the signal terminal shown in FW may be used for continuously inputting a high potential, the signal terminal shown in VGL may be used for continuously inputting a low potential, and the signal terminal shown in Clock may be used for inputting a Clock signal. As for the signal terminals shown in Reset, goff and BW, respectively, corresponding level signals may be input according to the timing diagram shown in fig. 2, which will not be described herein.

The operating principle of the shift register unit shown in fig. 1 can be summarized as follows, with reference to fig. 1 and 2:

in the first stage a ', the signal terminal Reset and the signal terminal Goff output a high potential, the P ' node is at a low potential, the transistor T '4 is turned off, and Gout does not output a high potential.

In the second stage b ', a high potential is input to the signal terminal Gn-1, and the control transistor T'0 is turned on so that the signal terminal FW charges the P 'node and the potential of the P' node is raised; at this time, the transistor T'4 is turned on, but Gout does not output a high potential because the signal terminal Clock inputs a low potential.

In the third stage c ', the signal end Gn-1 inputs low potential, the signal end Clock inputs high potential, the potential of the P' node is continuously raised under the capacitive coupling action of the parasitic capacitance of the grid electrode and the source electrode of the transistor T '4, and the conduction capacity of the transistor T'4 is greatly increased, so that Gout outputs high potential;

in addition, in the third stage c ', the P' node is at a high potential, the transistor T '3 is turned on with the transistor T'6, the Q 'node potential is pulled down by the signal source VGL, the transistor T'2 is turned off with the transistor T '5, and the potential of the P' node is prevented from being pulled down.

In the fourth stage d ', the signal terminal Gn-1 inputs low potential, the signal terminal Clock inputs low potential, gn+1 outputs high potential, and the potential of the P' node is pulled down, at this time Gout does not output high potential;

in addition, in the fourth stage d ', the potential of the P' node is pulled down, the transistors T '3 and T'6 are turned off, the potential of the Q 'node is pulled up under the control of the pull-down control module, the transistors T'2 and T '5 are turned on, and the potential of the P' node is reliably pulled down by the signal source VGL.

The shift register cell shown in fig. 1 is capable of compensating for threshold voltage shifts of the transistors to some extent. However, during actual operation, the problem of capability mismatch between the P 'node and the Q' node may still occur, subject to various factors. The following exemplifies the reasons for the problem of mismatch of two node capabilities, and the effects that result.

Generally, after the shift register unit corresponding to each row of pixel units in the display panel completes the output of the high potential, one frame of image is refreshed, and then a blanking (blanking) stage is performed. In the blanching stage, under the control of the Q 'node, the first pull-down module continuously pulls down the potential of the P' node.

In some application scenarios, the display panel to which the shift register unit is applied may have a need to change the refresh frequency, for example, it may be necessary to increase the refresh frequency of the display panel from 60Hz to 90Hz, or decrease it from 60Hz to 45Hz. However, since the size and configuration of the display panel may have been determined, it is often necessary to implement the change in refresh frequency by means of signal timing adjustment. The change of the refresh frequency will cause the time of the blanking phase to change, thereby generating the problem of capability mismatch between the P 'node and the Q' node.

For example, when the refresh frequency increases to decrease the time of the blanking period, the transistors T '2 and T '5 (corresponding to the first pull-down module) may not guarantee a sufficient on time, which makes it difficult for the signal source VGL to effectively pull the potential of the P ' node low; under the condition that the potential of the P ' node is difficult to be effectively pulled down, the transistors T '3 and T '6 (corresponding to the second pull-down module) may be kept on for a long time, the potential of the Q ' node is continuously pulled down by the signal source VGL, and the pull-down control module is difficult to effectively pull up the potential of the Q ' node, so that in the next refresh period, the transistors T '2 and T '5 are difficult to be reliably turned on.

Under the condition that the refresh frequency is increased, the voltage of the P' node is higher and higher along with the working time, and the corresponding capacity is stronger and stronger; conversely, the Q' node becomes weaker in capability. This results in the P 'node always clamping the Q' node, which in turn causes Gout output anomalies.

For example, gout is normally kept low after the fourth stage d' in one refresh period. While the P ' node always clamps the Q ' node, the P ' node may maintain a higher potential after the fourth stage d ', so that the transistor T '4 has a certain turn-on capability. Since the signal terminal Clock may still input a high voltage after the fourth stage d ', and the transistor T'4 has a certain turn-on capability, gout may abnormally output a high voltage.

For another example, when the refresh frequency decreases to increase the time of the blanking period, the transistors T '2 and T '5 have too long on-time, and the signal source VGL pulls the potential of the P ' node sufficiently low; under the condition that the potential of the P ' node is sufficiently pulled down, the transistor T '3 and the transistor T '6 may not be sufficiently conducted, so that the potential of the Q ' node is difficult to be effectively pulled down by the signal source VGL, and the potential of the Q ' node is continuously lifted under the pulling-up action of the pull-down control module; in the subsequent process, the potential of the Q 'node is kept high, so that the transistors T'2 and T '5 are difficult to be effectively turned off, and the potential of the P' node is continuously pulled down.

It can be seen that with decreasing refresh frequency, the ability of the P 'node becomes weaker and the ability of the Q' node becomes stronger over time. This results in the Q 'node always clamping the P' node, which in turn causes Gout output anomalies.

For example, in the second stage b ' and the third stage c ', the P ' node is normally charged continuously to raise the potential. When the Q 'node clamps the P' node all the time, the transistors T '2 and T'5 have a certain turn-on capability, and the P 'node potential may be pulled down in the second stage b' and the third stage c ', so that the P' node cannot reach a normal high potential. In this case, the transistor T'4 may have insufficient on-capability. When the signal terminal Clock of the third stage c 'inputs a high potential, it may cause the output potential of Gout to be low, i.e., cause Gout output abnormality, due to the influence of the on-state capability of the transistor T' 4.

Of course, in practical applications, other factors may exist in addition to the change in refresh frequency that may result in a capability mismatch between the P 'node and the Q' node. For example, in high temperature and high humidity type operation, as transistor characteristics drift gradually, capability mismatch between two nodes is also caused.

In order to solve the problem of capability mismatch between the P 'node and the Q' node generated in the operation process of the shift register unit shown in fig. 1, as shown in fig. 3, fig. 3 is one of schematic structural diagrams of the shift register unit provided in the embodiment of the present application, and the embodiment of the present application provides a shift register unit, including:

the input module 100, the input module 100 is coupled to the first input signal terminal Gn-1, the first voltage signal terminal FW and the first node P, and the input module 100 is configured to transmit the first voltage signal from the first voltage signal terminal FW to the first node P under the control of the first input signal terminal Gn-1;

the output module 200 is coupled to the Clock signal terminal Clock, the output signal terminal Gout and the first node P, and the output module 200 is configured to transmit the Clock signal from the Clock signal terminal Clock to the output signal terminal Gout under the control of the first node P;

the first pull-down module 300 is coupled to the first node P, the second node Q and the second voltage signal terminal VGL, and the pull-down module 300 is configured to pull the potential of the first node P low through the second voltage signal terminal VGL under the control of the second node Q;

The pull-down control module 400 is coupled to the third voltage signal terminal QUP, the third node S and the second node Q, and the pull-down control module 400 is configured to pull the potential of the second node Q high through the third voltage signal terminal QUP under the control of the third node S;

the voltage adjustment module 500, the voltage adjustment module 500 includes a first capacitor C1, the voltage adjustment module 500 is coupled to the second input signal terminal Gn-2, the first input signal terminal Gn-1, the first voltage signal terminal FW, the first node P and the third node S, the voltage adjustment module 500 is configured to charge the first terminal N of the first capacitor C1 through the first voltage signal terminal FW under the control of the second input signal terminal Gn-2, and charge the second terminal M of the first capacitor C1 through the first voltage signal terminal FW under the control of the first node P and the first input signal terminal Gn-1, the charge amount of the second terminal M of the first capacitor C1 by the first voltage signal terminal FW is positively correlated with the voltage of the first node P, and the first terminal N of the first capacitor C1 is connected with the third node S.

In this embodiment, the first node P may correspond to the first node P 'or the pull-up node, and the first node Q may correspond to the first node Q' or the pull-down node.

The working principle of the shift register unit in this embodiment is described below with reference to an application scenario.

To facilitate understanding of the operational relationship between the various modules, solid arrows may be considered as the direction of transmission of control signals in fig. 3, and non-solid arrows may be considered as the direction of transmission of voltage signals not used for control, as shown in fig. 3.

It should be emphasized that, in the schematic structural diagrams of the shift register unit provided in the embodiments of the present application, the connection between each signal end and the module, and the connection between the modules are only used for illustrating the coupling relationship, and the distinction of the connection arrow form is also only used for intuitively showing the transmission relationship of the control signal or the non-control signal. These connections do not constitute any limitation on the manner in which the specific connections between the electronic components in the shift register unit are arranged.

Fig. 4 is an exemplary diagram of a timing chart of input signals of respective signal terminals of the shift register unit shown in fig. 3, as shown in fig. 4:

in the first stage a, the second input signal terminal Gn-2 may input a control signal to control the first voltage signal terminal FW to charge the first terminal N (hereinafter referred to as the first terminal N) of the first capacitor C1, where the voltage of the first terminal N may be denoted as V1;

In the second phase b, the first input signal terminal Gn-1 may input a control signal to control the first voltage signal terminal FW to transmit the first voltage signal to the first node; at this time, the voltage of the first node P may be denoted as V2;

at this time, the control signal input from the first input signal terminal Gn-1 and the voltage of the first node P may cooperate, such that the first voltage signal terminal FW charges the second terminal M (hereinafter referred to as the second terminal M) of the first capacitor C1.

In this embodiment, the amount of charge of the first voltage signal terminal FW to the second terminal M is positively correlated with the voltage V2 of the first node P.

For example, the first node P may be connected to a charging loop of the first voltage signal terminal FW to the second terminal M through a transistor. The first node P may be connected to the gate of the transistor, and the second terminal M is connected to the drain of the transistor. The larger the voltage of the gate, the larger the drain current, and the larger the charge amount of the second terminal M in a certain time period, when the transistor operates in the linear region.

Since the first end N is charged in the first stage a, and the second end M is charged in the second stage b, the voltage of the first end N is raised from V1 to V3 under the capacitive coupling effect; it is readily understood that V2 is positively correlated with (V3-V1), and that V2 is positively correlated with V3 if V1 is constant.

Since the first terminal N is connected to the third node S, it is known from the above analysis that the higher the voltage of the first node P, the higher the voltage of the third node S, and vice versa.

In the third stage c, the Clock signal terminal Clock may input a Clock signal (high potential) which may be transmitted to the output signal terminal Gout under the control of the first node P.

In the fourth phase d, the third voltage signal terminal QUP pulls the potential of the second node Q high under the control of the third node S. Here, the transistor may also be arranged and operated in a linear region such that the higher the voltage of the third node S, the higher the voltage of the second node Q after being pulled up, and vice versa, as will be further illustrated in detail below.

The first pull-down module 300 may pull the potential of the first node P down through the second voltage signal terminal VGL under the control of the second node Q. Similarly, the first pull-down module 300 may also be configured to include a transistor and operate the transistor in a linear region, and accordingly, the higher the voltage of the second node Q, the higher the potential pull-down capability of the second voltage signal terminal VGL to the first node P, and vice versa.

It should be emphasized that fig. 4 is an exemplary diagram provided for understanding the operation principle of the shift register unit, and in practical application, the timing sequence of each signal terminal may be adjusted according to needs, so that the above operation stages may be implemented.

As can be seen from the above description of the operation principle of the shift register unit, in the second phase b, the higher the voltage of the first node P, the higher the voltage of the second node Q in the fourth phase d, the stronger the potential pull-down capability of the first pull-down module 300 to the first node P, so that the first node P can be prevented from clamping the second node Q, and vice versa. Therefore, the first node P and the second node Q can be clamped to each other in each operation stage of the shift register unit, and the increase or decrease of the time of the blanking stage is difficult to affect the relative capability between the first node P and the second node Q.

It can be seen that, in this embodiment, by the arrangement of the voltage adjustment module 500, the voltage matching degree between the first node P and the second node Q can be effectively ensured, thereby being beneficial to improving the quality of the output signal.

When the shift register unit provided in the embodiment is applied to a display panel, the quality of the output signal is improved, and display abnormality of the display panel can be effectively avoided.

In order to simplify the explanation, in the following embodiments, the description of the relevant operation phases of the first phase a, the second phase b, and the like may be considered to correspond to the respective operation phases in the present embodiment.

Optionally, as shown in fig. 5, fig. 5 is a schematic structural diagram of a shift register unit according to an embodiment of the present application, where, based on the structure shown in fig. 3, the shift register unit may further include a second pull-down module 600;

the second pull-down module 600 is coupled to the second end M of the first capacitor C1, the second input signal end Gn-2 and the second voltage signal end VGL; the second pull-down module 600 is configured to pull the potential of the second terminal M of the first capacitor C1 low through the second voltage signal terminal VGL under the control of the second input signal terminal Gn-2.

In connection with the explanation of the operation principle of the shift register unit shown in fig. 3, in the first stage a, the second input signal terminal Gn-2 may input a control signal to control the first voltage signal terminal FW to charge the first terminal N. In this embodiment, in order to ensure the stability of the charge amount of the first terminal N, the control signal input by the second input signal terminal Gn-2 may also pull the potential of the second terminal M down by the second voltage signal terminal VGL.

Specifically, in the first stage a, the first terminal N of the first capacitor C may be connected to the second voltage signal terminal VGL, and the second terminal M may be connected to the first voltage signal terminal FW. Therefore, the two ends of the first capacitor C may have a relatively stable potential difference, and according to the formula that the charge amount is equal to the capacitance multiplied by the potential difference, in the first stage a, the charge amount of the first end N of the first capacitor C may be relatively stable, so that fluctuation of the voltage of the third node S caused by fluctuation of the charge amount of the first end N may be effectively avoided, and further the voltage change of the first node P may effectively affect the voltage change of the second node Q, so as to improve the voltage matching degree between the first node P and the second node Q.

Optionally, as shown in fig. 6, fig. 6 is a schematic diagram of another structure of a shift register unit according to an embodiment of the present application, where the voltage adjustment module 500 further includes a first transistor T1, a second transistor T2, and a third transistor T3, and the second pull-down module 600 includes a fourth transistor T4; wherein,

the grid electrode of the first transistor T1 is connected with the first input signal end Gn-1, the source electrode of the first transistor T1 is connected with the first voltage signal end FW, and the drain electrode of the first transistor T1 is connected with the source electrode of the second transistor T2;

the grid electrode of the second transistor T2 is connected with the first node, and the drain electrode of the second transistor T2 is connected with the source electrode of the fourth transistor T4 and the second end M of the first capacitor C1;

the grid electrode of the fourth transistor T4 is connected with the second input signal end Gn-2, and the drain electrode of the fourth transistor T4 is connected with the second voltage signal end VGL;

the gate of the third transistor T3 is connected to the second input signal terminal Gn-2, the source of the third transistor T3 is connected to the first voltage signal terminal FW, and the drain of the third transistor T3 is connected to the third node S.

In one example, each of the above transistors may be a thin film transistor (Thin Film Transistor, TFT). For simplicity of description, each transistor mentioned in the following embodiments will be described by taking a TFT as an example unless otherwise specified.

In one example, the individual transistors described above may operate in the cut-off region, the linear region, and the saturation region. Wherein the transistor operates in the linear region, the voltage of the gate and the drain current may be positively correlated.

Accordingly, in the first stage a, the second input signal terminal Gn-2 may output a high potential, and the first input signal terminal Gn-1 may output a low potential. At this time, the first transistor T1 is in an off state; the first node P may be at a low potential at this time due to non-charging, and the second transistor T2 is in an off state. Therefore, the first voltage signal terminal FW is not communicated with the second terminal M of the first capacitor C1.

Meanwhile, since Gn-2 outputs a high potential, the third transistor T3 and the fourth transistor T4 may be in a conductive state. The fourth transistor T4 is turned on, so that the second voltage signal terminal VGL can pull the point of the second terminal M of the first capacitor C1 low; the third transistor T3 is turned on, the first voltage signal terminal FW may charge the first terminal N of the first capacitor C1, and the voltage of the charged first terminal N during this stage may be denoted as V1.

After entering the second phase b, the first input signal terminal Gn-1 may output a high potential, and the second input signal terminal Gn-2 may output a low potential. At this time, the third transistor T3 and the fourth transistor T4 may be in an off state. At this time, the second voltage signal terminal VGL is not conductive to the second terminal M, so the second voltage signal terminal VGL will not pull down the point of the second terminal M. The first terminal N of the first capacitor C1 is disconnected from the first voltage signal terminal FW.

At the same time, the first input signal terminal Gn-1 outputs a high potential, the first voltage signal of the first voltage signal terminal FW is transmitted to the first node P, and the voltage of the first node P is raised to V2. The first input signal terminal Gn-1 and the first node P are respectively connected to the gate of the first transistor T1 and the gate of the second transistor T2, and since the first input signal terminal Gn-1 and the first node P are both at high voltage, the first transistor T1 and the second transistor T2 are turned on, and the first voltage signal terminal FW charges the second terminal M of the first capacitor C1.

The voltage V2 of the first node P can make the second transistor T2 operate in the amplifying region, and further, the charged amount of the second terminal M of the first capacitor C1 is positively correlated with the voltage of the first node P.

Due to the capacitive coupling effect, when the second terminal M is charged, the voltage of the first terminal N is also correspondingly increased, and after the second stage b is performed, the voltage of the first terminal N is increased to V3, that is, the voltage of the third node S is increased to V3. As indicated above, the value of (V3-V1) is positively correlated with V2.

In the third stage C and the fourth stage d, the first input signal terminal Gn-1 and the second input signal terminal Gn-2 can output low voltages, and at this time, the first transistor T1, the third transistor T3 and the fourth transistor T4 are all in the off state, and the voltage across the first capacitor C1 and the voltage at the third node S can be maintained. Therefore, the voltage V3 of the third node S in the second phase b may be stably input to the pull-down control module 400 to implement the adjustment of the point location of the second node P.

It can be seen that, in this embodiment, through the design of the connection relationship between the transistors, the smooth progress of the charging process at the two ends of the first capacitor C1 can be ensured, and meanwhile, the voltage change of the first node P can be effectively ensured, the voltage change of the third node S can be reliably caused, and further the voltage change of the second node Q is positively influenced, so as to ensure the matching degree of the voltages between the first node P and the second node Q.

It is easy to understand that the connection positions of the source and drain of each transistor can be adjusted accordingly according to the channel type of the transistor. For example, when the first transistor T1 is a P-channel transistor, a source thereof may be connected to the first voltage signal terminal FW; and when the first transistor T1 is an N-channel transistor, the drain may be connected to the first voltage signal terminal FW.

Alternatively, as shown in fig. 7, fig. 7 is a schematic diagram of another structure of a shift register unit according to an embodiment of the present application, where the pull-down control module 400 includes a fifth transistor T5;

the gate of the fifth transistor T5 is connected to the third node S, the source of the fifth transistor T5 is connected to the third voltage signal terminal QUP, and the drain of the fifth transistor T5 is connected to the second node Q.

In this embodiment, the fifth transistor T5 can operate in the linear region, i.e. the larger the gate voltage, the larger the drain current.

The gate of the fifth transistor T5 is connected to the third node S, and the drain of the fifth transistor T5 is connected to the second node Q, that is, the larger the voltage of the third node S is, the larger the current of the second node Q is, and the smaller the voltage drop of the fifth transistor T5 is.

In one example, the output signal of the third voltage signal terminal QUP can have a high-low point, the third voltage signal terminal QUP outputs a low voltage in the first phase a to the third phase c, and the third voltage signal terminal QUP outputs a high voltage in the fourth phase d to pull up the potential of the second node Q. And the higher the voltage of the third node S, the greater the pull-up degree of the potential of the second node Q.

In another example, the third voltage signal terminal QUP and the first voltage signal source FW may be the same signal source and continuously output a high potential. Alternatively, the third voltage signal terminal QUP and the first voltage signal source FW may be independent signal sources, and continuously output high voltages, and the output voltages of the third voltage signal terminal QUP and the first voltage signal source FW may be equal or unequal, so as to adapt to the working parameter requirements of different transistors.

In the case that the third voltage signal terminal QUP continuously outputs the high potential, the potential of the second node Q can be continuously pulled down by the second voltage signal terminal VGL in the second phase b to the third phase c, so as to avoid the situation that the potential of the first node P is abnormally pulled down under the control of the first pull-down module 300. In the fourth phase d, the second node Q may be disconnected from the second voltage signal terminal VGL, so that the third voltage signal terminal QUP can pull up the potential of the second node Q. The specific construction of the shift register unit that can realize this operation will be described in detail later.

Optionally, as shown in fig. 8, fig. 8 is a schematic diagram of another structure of a shift register unit according to an embodiment of the present application, where the pull-down control module 400 further includes a sixth transistor T6 and a seventh transistor T7; wherein,

the gate and the source of the sixth transistor T6 are both connected to the third voltage signal terminal QUP, and the drain of the sixth transistor T6 is connected to the gate of the seventh transistor T7;

the source of the seventh transistor T7 is connected to the third voltage signal terminal QUP, and the drain of the seventh transistor T7 is connected to the second node Q.

In one example, the sixth transistor T6 and the seventh transistor T7 may operate in a linear region, and the characteristic parameters of the two transistors may be the same. Let the third voltage signal terminal QUP continuously output a high voltage, and the voltage is V4.

If the fifth transistor T5 is not considered, the sixth transistor T6 operates in the linear region, and a certain voltage drop exists between the source and the drain, denoted as Δv1, so the voltage V5 at the drain of the sixth transistor T6 is smaller than V4; the gate voltage of the seventh transistor T7 is equal to V5, and accordingly, the voltage drop Δv2 between the source and the drain of the seventh transistor T7 may be greater than Δv1. At this time, the voltage of the second node Q is equal to (V4-DeltaV 2). To a certain extent, the seventh transistor T7 may be equivalently a voltage dividing resistor (hereinafter referred to as a first equivalent resistor) with a constant resistance.

Of course, the above is some examples of the characteristic parameters and the operation parameters between the sixth transistor T6 and the seventh transistor T7, and in practical applications, the characteristic parameters and the operation parameters can be adjusted as required.

Similarly to the seventh transistor T7, the fifth transistor T5 may be equally equivalent to a voltage dividing resistor (hereinafter referred to as a second equivalent resistor), but the resistance may be changed according to the voltage of the third node S. Specifically, the higher the voltage of the third node S, the smaller the voltage drop between the source and the drain of the fifth transistor T5, the smaller the resistance equivalent to the second equivalent resistance.

As shown in fig. 8, the fifth transistor T5 and the seventh transistor T7 may be considered as being connected in parallel between the third voltage signal terminal QUP and the second node Q. The smaller the resistance value of the second equivalent resistor is, the smaller the total resistance value of the first equivalent resistor and the second equivalent resistor connected in parallel is, the smaller the voltage drop caused by the first equivalent resistor and the second equivalent resistor is, and the higher the voltage of the second node Q is; and vice versa.

In summary, the higher the voltage at the first node P, the higher the voltage at the third node S, and the higher the voltage at the second node Q, and vice versa; thus, the situation that the capacities of the first node P and the second node Q are not matched can be effectively avoided.

As a variation of the embodiment shown in fig. 8, as shown in fig. 9, fig. 9 is another schematic structural diagram of a shift register unit according to an embodiment of the present application, where the pull-down control module 400 includes a sixth transistor T6 and a seventh transistor T7, in this embodiment, the sixth transistor T6 and the seventh transistor T7 may be further connected as follows:

the source of the seventh transistor T7 is connected to the drain of the fifth transistor T5, and the drain of the seventh transistor T7 is connected to the second node Q.

As shown in fig. 9, the difference between the present embodiment and the previous embodiment is that the connection mode of connecting the fifth transistor T5 and the seventh transistor T7 in parallel between the third voltage signal terminal QUP and the second node Q is replaced by connecting the fifth transistor T5 and the seventh transistor T7 in series between the third voltage signal terminal QUP and the second node Q.

Similarly, the fifth transistor T5 and the seventh transistor T7 may be respectively equivalent to a second equivalent resistance and a first equivalent resistance. The higher the voltage of the third node S is, the smaller the resistance of the second equivalent resistor is, the smaller the total resistance of the first equivalent resistor and the second equivalent resistor which are connected in series is, the smaller the voltage drop caused by the first equivalent resistor and the second equivalent resistor is, and the higher the voltage of the second node Q is; and vice versa.

Based on fig. 8 and fig. 9, the embodiment of the application designs different circuit configurations for the pull-down control module 400, and in practical application, a reasonable circuit configuration can be selected according to the design requirements of the characteristic parameters and the working parameters of each transistor, so that the applicability of the shift register unit provided by the embodiment of the application can be effectively improved.

As shown in fig. 10, fig. 10 is another schematic structural diagram of a shift register unit according to an embodiment of the present application, where the shift register unit further includes a third pull-down module 700, and the third pull-down module 700 includes an eighth transistor T8 and a ninth transistor T9; wherein,

a gate of the eighth transistor T8 is connected with the first node P, a source of the eighth transistor T8 is connected with the second node Q, and a drain of the eighth transistor T8 is connected with the second voltage signal end VGL;

the gate of the ninth transistor T9 is connected to the first node P, the source of the ninth transistor T9 is connected to the drain of the sixth transistor T6, and the drain of the ninth transistor T9 is connected to the second voltage signal terminal VGL.

In connection with the above description of the working principle of the shift register unit shown in fig. 3, the first node P is at a high potential in the second phase b with the third node.

The gates of the eighth transistor T8 and the ninth transistor T9 are both connected to the first node P, and when the first node P is at the high potential, the eighth transistor T8 and the ninth transistor T9 can be fully turned on, so that the second voltage signal terminal VGL can pull down the potentials of the gates of the second node Q and the seventh transistor T7.

In this way, the second voltage signal terminal VGL continuously pulls down the potential of the second node Q, so that the first pull-down module 300 disconnects the first node P from the second voltage signal terminal VGL, and the Gout output abnormality caused by the second voltage signal terminal VGL pulling down the potential of the first node P in the second stage b and the third stage c is avoided.

In addition, the second voltage signal terminal VGL may pull down the potential of the gate of the seventh transistor T7, so that the seventh transistor T7 may be turned off, and in the case where the fifth transistor T5 and the seventh transistor T7 are connected in series as shown in fig. 10, the seventh transistor T7 may be turned off, so that the third voltage signal terminal QUP may raise the potential of the second node Q in the second stage b and the third stage c, thereby playing a role in redundancy ensuring the normal output of Gout.

Of course, in the case where the fifth transistor T5 is connected in parallel with the seventh transistor T7, the second node Q potential is continuously pulled down by the second voltage signal terminal VGL, so that the Gout output abnormality can be avoided, and the circuit structure and the operation principle when the fifth transistor T5 is connected in parallel with the seventh transistor T7 will not be described herein.

Optionally, as shown in fig. 11, fig. 11 is a schematic diagram of another structure of a shift register unit according to an embodiment of the present application, and the output module 200 includes a tenth transistor T10 and a second capacitor C2; wherein,

A gate of the tenth transistor T10 is connected to the first node P, a source of the tenth transistor T10 is connected to the Clock signal terminal Clock, and a drain of the tenth transistor T10 is connected to the output signal terminal Gout;

the first end of the second capacitor C2 is connected to the first node P, and the second end of the second capacitor C2 is connected to the output signal terminal Gout.

In connection with the above description of the operation principle of the shift register unit shown in fig. 3, in the second stage b, the first input signal terminal Gn-1 may input a control signal to control the first voltage signal terminal FW to transmit the first voltage signal to the first node; at this time, the voltage of the first node P, that is, the voltage of the first terminal of the second capacitor C2 is V2.

At the same time, the Clock signal terminal Clock is at a low potential, and the output signal terminal Gout does not output a high potential.

In the third stage c, the Clock signal terminal Clock inputs a high-level Clock signal, and due to parasitic capacitance between the gate and the source of the tenth transistor T10, the voltage of the first node P is further pulled up to V6 under the capacitive coupling effect, and the turn-on capability of the tenth transistor T10 is also increased. At this time, the clock signal of high potential can be transmitted to the output signal terminal Gout.

Therefore, in the embodiment, the quality of the output signal terminal Gout can be effectively ensured based on the capacitive coupling effect of the second capacitor C2.

In one example, when the voltage of the first node P is V6, the tenth transistor T10 may operate in a saturation region, thereby enabling the output signal terminal Gout to reliably output a high potential.

Alternatively, as shown in fig. 12, fig. 12 is a schematic diagram of another structure of a shift register unit according to an embodiment of the present application, and the first pull-down module 300 includes an eleventh transistor T11 and a twelfth transistor T12; wherein,

a gate of the eleventh transistor T11 is connected to the second node Q, a source of the eleventh transistor T11 is connected to the first node P, and a drain of the eleventh transistor T11 is connected to the second voltage signal terminal VGL;

the gate of the twelfth transistor T12 is connected to the second node Q, the source of the twelfth transistor T12 is connected to the output signal terminal Gout, and the drain of the twelfth transistor T12 is connected to the second voltage signal terminal VGL.

As shown above, the first pull-down module 300 may be used to pull down the potential of the first node P through the second voltage signal terminal VGL under the control of the second node Q.

In this embodiment, when the second node Q is at a high potential, the eleventh transistor T11 may be turned on, and the second voltage signal terminal VGL may pull down the potential of the second node Q.

Generally, the above process of pulling down the potential of the second node Q through the second voltage signal terminal VGL may occur in the fourth stage d. In the fourth stage d, the output signal terminal Gout has completed outputting the output signal, so as to avoid that the output signal terminal Gout is continuously in the high-level state, the twelfth transistor T12 may be turned on under the control of the high level of the second node Q, and further, the second voltage signal terminal VGL pulls the potential of the output signal terminal Gout low.

Since the potential of the second node Q is continuously pulled down, the tenth transistor T10 is turned off due to the gate being at the low potential, and even if the subsequent Clock signal terminal Clock inputs the high potential, the output signal terminal Gout cannot be made to output the high potential, thereby effectively ensuring the quality of the output signal terminal Gout.

Optionally, as shown in fig. 13, fig. 13 is another schematic structural diagram of a shift register unit according to an embodiment of the present application, where the shift register unit may further include a reset module 800, and the reset module 800 includes a thirteenth transistor T13 and a fourteenth transistor T14; wherein,

a gate of the thirteenth transistor T13 is connected to the first Reset signal terminal Reset, a source of the thirteenth transistor T13 is connected to the first node P, and a drain of the thirteenth transistor T13 is connected to the second voltage signal terminal VGL;

the gate of the fourteenth transistor T14 is connected to the second reset signal terminal Goff, the source of the fourteenth transistor T14 is connected to the output signal terminal Gout, and the drain of the fourteenth transistor T14 is connected to the second voltage signal terminal VGL.

In one example, the first Reset signal terminal Reset and the second Reset signal terminal Goff may be the same signal terminal, for example, both may be connected to the output signal terminal of the next stage shift register unit.

In another example, the first Reset signal terminal Reset and the second Reset signal terminal Goff may be different signal terminals.

In the following, a number of possible operation modes of the Reset module 800 are mainly exemplified by the fact that the first Reset signal terminal Reset and the second Reset signal terminal Goff are different signal terminals. It should be emphasized that in practical applications, the reset module 800 may implement a certain working mode thereof, or may implement multiple working modes simultaneously.

The Reset module 800 may operate before the first stage a, for example, before the second input signal terminal Gn-2 inputs the signals, the first Reset signal terminal Reset and the second Reset signal terminal Goff may input the high voltage, the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, and the voltage levels of the first node P and the output signal terminal Gout are pulled down, so that the shift register unit has a reasonable initial voltage level between the first node P and the output signal terminal Gout before entering the signal output period.

The Reset module 800 may operate in the fourth stage d, for example, the first Reset signal terminal Reset may be connected to the output signal terminal of the next stage shift register unit, and further may control the thirteenth transistor T13 to be turned on when the output voltage of the next stage shift register unit is high, so as to pull down the voltage of the first node P through the second voltage signal terminal VGL.

The reset module 800 may operate in a blanking period, for example, the second reset signal terminal Goff inputs a high level, so that the fourteenth transistor T14 is turned on, and the potential of the output signal terminal Gout is pulled down by the second voltage signal terminal VGL.

Based on the above description, the reset module 800 provided in this embodiment can effectively pull down the potential of the first node P through the second voltage signal terminal VGL in the preset operation phase of the shift register unit according to the actual requirement.

Optionally, as shown in fig. 14, fig. 14 is another schematic structural diagram of a shift register unit provided in an embodiment of the present application, where the shift register unit further includes a pull-down charging module 900, and the pull-down charging module 900 includes a fifteenth transistor T15;

the gate of the fifteenth transistor T15 is connected to the third input signal terminal gn+1, the drain of the fifteenth transistor T15 is connected to the fourth voltage signal terminal BW, and the source of the fifteenth transistor T15 is connected to the first node P.

In this embodiment, the pull-down charging module 900 may implement at least one of the functions of potential pull-down and charging.

First, the potential pull-down function of the pull-down charging module 900 is illustrated. The pull-down charging module 900 may implement a function of pulling down the potential of the first node P in the fourth stage d.

Specifically, in the fourth stage d, the fourth voltage signal terminal BW inputs a low potential, the third input signal terminal gn+1 inputs a high potential, and at this time, the fifteenth transistor T15 is turned on, and the fourth voltage signal terminal BW can pull down the potential of the first node P.

In an embodiment, in the case that the shift register unit includes the third pull-down module 700, the pull-down charging module 900 assists to pull down the potential of the first node P according to the high potential input by the third input signal terminal gn+1, so that the eighth transistor T8 and the ninth transistor T9 in the third pull-down module 700 are turned off, and the potential of the second node Q is raised by the third voltage signal terminal QUP, so as to further control the first pull-down module 300 to pull down the potential of the first node P.

The pull-down charging module 900 may also charge the first node P during the blanking phase.

Specifically, in the blanching phase, the fourth voltage signal terminal BW may input a high potential, and if the voltage of the first node P is too low, the fourth voltage signal terminal BW may charge the first node P under the condition that the fifteenth transistor T15 is turned on slightly, so as to avoid that the potential of the first node P is excessively pulled down.

In practical applications, the potential of the fourth voltage signal terminal BW may be set as required, so that the charge amount of the pull-down charging module 900 to the first node P in the blanking phase is kept at a relatively reasonable level.

In one example, the fifteenth transistor T15 may operate in the saturation region in the fourth phase d and in the linear region in the blanking phase.

Optionally, as shown in fig. 15, fig. 15 is another schematic structural diagram of a shift register unit provided in an embodiment of the present application, and the input module 100 includes a sixteenth transistor T16;

the gate of the sixteenth transistor T16 is connected to the first input signal terminal Gn-1, the source of the sixteenth transistor T16 is connected to the first voltage signal terminal FW, and the drain of the sixteenth transistor T16 is connected to the first node P.

In one example, in the second phase b, the first input signal terminal Gn-1 inputs a high potential so that the sixteenth transistor T16 is turned on, the first voltage signal of the first voltage signal terminal FW is transmitted to the first node P, and the voltage of the first node P is raised to V2. In the third phase c, the first input signal terminal Gn-1 inputs a low potential, and the sixteenth transistor T16 is turned off so that the first node P can maintain a high potential. The subsequent first node P may pull high further under the capacitive coupling action of the second capacitor C2, so that the output signal terminal Gout outputs a signal normally.

Fig. 16 and 17 are schematic diagrams of another structure of a shift register unit according to an embodiment of the present application, and fig. 17 is a schematic diagram of another structure of a shift register unit according to an embodiment of the present application, and a circuit structure of a shift register unit according to an embodiment of the present application. In these specific application examples, the shift register unit may include an input module 100, an output module 200, a first pull-down module 300, a pull-down control module 400, a voltage adjustment module 500, a second pull-down module 600, a third pull-down module 700, a reset module 800, and a pull-down charging module 900.

The shift register unit shown in fig. 16 is different from the shift register unit shown in fig. 17 in that: in the pull-down control module 400 of the former, the fifth transistor T5 and the seventh transistor T7 are connected in parallel; in the pull-down control module 400 of the latter, the fifth transistor T5 and the seventh transistor T7 are connected in series.

As shown in fig. 18, fig. 18 is a timing chart of input signals of respective signal terminals of the shift register unit shown in fig. 16 or 17.

The above components and connection relationships of the electronic components of each module, and the working principles of each module have been described in detail in the above embodiments, which are not described herein. In these specific application examples, the voltage adjustment module 500 in the shift register unit may match the voltage between the first node P and the second node Q, so as to ensure the quality of the output signal of the output module 200.

As shown in fig. 19, fig. 19 is a schematic structural diagram of a shift register according to an embodiment of the present application, and the embodiment of the present application further provides a shift register, including: multistage the shift register unit shown in the above embodiments; wherein,

The following describes the working principle of the shift register provided in the application embodiment with reference to the structure of the shift register unit shown in fig. 3.

In the first stage, the output module of the N-2 th stage shift register unit may output a high potential, the high potential may be input to the second input signal terminal (corresponding to Gn-2) of the N-th stage shift register unit, the first terminal N of the first capacitor C1 in the N-th stage shift register unit is charged, and at this time, the voltage of the first terminal N may be denoted as V1;

in the second stage, the output module of the n-1 th stage shift register unit may output a high potential, which may be input to the first input signal terminal (corresponding to Gn-1) of the n-th stage shift register unit, and the potential of the first node P in the n-th stage shift register unit is raised to V2.

Meanwhile, the second end M of the first capacitor C1 in the nth stage shift register unit is charged, the voltage of the first end N is raised from V1 to V3 under the capacitive coupling effect, the first end N is connected with the third node S, and correspondingly, the voltage of the third node S is V3. It is readily understood that V2 is positively correlated with (V3-V1), and that V2 is positively correlated with V3 if V1 is constant.

In the third stage, the Clock signal terminal Clock in the nth stage shift register unit may input a Clock signal (high potential) that may be transmitted to the output signal terminal Gout under the control of the first node P.

In the fourth stage, in the nth stage shift register unit, under the control of the third node S, the third voltage signal terminal QUP pulls the potential of the second node Q high, and the first pull-down module can pull the potential of the first node P low through the second voltage signal terminal VGL under the control of the second node Q, and the output signal terminal Gout does not output the high potential.

As can be seen from the above description of the working principle of the shift register, in the second stage, the higher the voltage of the first node P, the higher the voltage of the second node Q in the fourth stage, the stronger the potential pull-down capability of the first pull-down module to the first node P, so that the first node P can be prevented from clamping the second node Q, and vice versa. Therefore, in this embodiment, by setting the voltage adjusting module, the voltage matching degree between the first node P and the second node Q can be effectively ensured, thereby being beneficial to improving the quality of the output signal.

Optionally, as shown in fig. 20, fig. 20 is a schematic diagram of still another structure of the shift register according to the embodiment of the present application, where the shift register unit includes a pull-down charging module, a third input signal terminal of the n-th stage shift register unit is connected to an output signal terminal of the n+1th stage shift register unit.

In the third stage, the high potential output from the n-th shift register unit may be input to the n+1th shift register, so that the output module of the n+1th shift register unit may output the high potential, which may be input to the third input signal terminal of the n-th shift register unit in the fourth stage.

Accordingly, for the n-th stage shift register unit, in the fourth stage, the fourth voltage signal terminal may input a low potential to pull down the potential of the first node P.

The embodiment of the application also provides a display device which comprises the shift register.

As shown in fig. 21, fig. 21 is a schematic structural diagram of a display panel according to an embodiment of the present application, a display device may include a display area VA and a non-display area AA, the non-display area AA is disposed around the display area VA, and a shift register may be disposed in the non-display area AA.

It should be noted that the implementation manner of the shift register unit embodiment and the shift register embodiment are also adapted to the embodiment of the display device, and the same technical effects can be achieved, which is not described herein.

As shown in fig. 22, fig. 22 is a schematic flow chart of a driving method provided by an embodiment of the present application, and the embodiment of the present application further provides a driving method applied to the shift register unit, where the method includes:

Step 2201, in the first stage, a low potential is input to the first input signal terminal, a high potential is input to the second input signal terminal, and the first terminal of the first capacitor is charged through the first voltage signal terminal to raise the potential of the third node;

step 2202, in the second stage, the first input signal terminal inputs a high potential, the second input signal terminal inputs a low potential, the potential of the first node is pulled up by the first voltage signal terminal, and the second terminal of the first capacitor is charged by the first voltage signal terminal, so as to further pull up the potential of the third node; the charge quantity of the first voltage signal end to the second end of the first capacitor is positively correlated with the potential of the first node;

step 2203, in the third stage, the clock signal terminal inputs a high potential, so that the output signal terminal outputs a high potential;

step 2204, in the fourth stage, under the control of the third node, pulling up the potential of the second node through the third voltage signal terminal; under the control of the second node, the potential of the first node is pulled down through the second voltage signal terminal.

In this embodiment, in step 2202, the amount of charge of the first voltage signal terminal to the second terminal of the first capacitor is positively correlated with the voltage of the first node, and the amount of charge of the first voltage signal terminal to the second terminal of the first capacitor is positively correlated with the degree of lifting of the potential of the third node.

Accordingly, the higher the voltage of the first node, the higher the voltage of the third node, and in step 2204, the higher the degree of potential rise of the second node, the higher the voltage of the second node. And vice versa.

Therefore, the embodiment of the application can effectively ensure the voltage matching degree between the first node and the second node, thereby being beneficial to improving the quality of output signals.

These examples are not intended to be exhaustive or to limit the application to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A shift register unit, comprising:

an input module coupled to a first input signal terminal, a first voltage signal terminal, and a first node, the input module configured to transmit a first voltage signal from the first voltage signal terminal to the first node under control of the first input signal terminal;

An output module coupled to a clock signal terminal, an output signal terminal, and the first node, the output module configured to transmit a clock signal from the clock signal terminal to the output signal terminal under control of the first node;

a first pull-down module coupled to the first node, the second node, and a second voltage signal terminal, the pull-down module configured to pull down a potential of the first node through the second voltage signal terminal under control of the second node;

the pull-down control module is coupled to a third voltage signal end, a third node and the second node, and is configured to pull up the potential of the second node through the third voltage signal end under the control of the third node;

the voltage regulation module comprises a first capacitor, the voltage regulation module is coupled to a second input signal end, a first voltage signal end, a first node and a third node, the voltage regulation module is configured to charge a first end of the first capacitor through the first voltage signal end under the control of the second input signal end, and charge a second end of the first capacitor through the first voltage signal end under the control of the first node and the first input signal end, the charge amount of the second end of the first capacitor by the first voltage signal end is positively correlated with the voltage of the first node, and the first end of the first capacitor is connected with the third node.

2. The shift register cell of claim 1, further comprising a second pull-down module;

the second pull-down module is coupled to the second end of the first capacitor, the second input signal end and the second voltage signal end; the second pull-down module is configured to pull down the potential of the second end of the first capacitor through the second voltage signal end under control of the second input signal end.

3. The shift register cell of claim 2, wherein the voltage adjustment module further comprises a first transistor, a second transistor, and a third transistor, the second pull-down module comprising a fourth transistor; wherein,

the grid electrode of the first transistor is connected with the first input signal end, the source electrode of the first transistor is connected with the first voltage signal end, and the drain electrode of the first transistor is connected with the source electrode of the second transistor;

the grid electrode of the second transistor is connected with the first node, and the drain electrode of the second transistor is connected with the source electrode of the fourth transistor and the second end of the first capacitor;

the grid electrode of the fourth transistor is connected with the second input signal end, and the drain electrode of the fourth transistor is connected with the second voltage signal end;

The grid electrode of the third transistor is connected with the second input signal end, the source electrode of the third transistor is connected with the first voltage signal end, and the drain electrode of the third transistor is connected with the third node.

4. The shift register cell of claim 1, wherein the pull-down control module comprises a fifth transistor;

the grid electrode of the fifth transistor is connected with the third node, the source electrode of the fifth transistor is connected with the third voltage signal end, and the drain electrode of the fifth transistor is connected with the second node.

5. The shift register cell as claimed in claim 4, wherein the pull-down control module further comprises a sixth transistor and a seventh transistor; wherein,

the grid electrode and the source electrode of the sixth transistor are connected with the third voltage signal end, and the drain electrode of the sixth transistor is connected with the grid electrode of the seventh transistor;

and the source electrode of the seventh transistor is connected with the third voltage signal end, and the drain electrode of the seventh transistor is connected with the second node.

6. The shift register cell as claimed in claim 4, wherein the pull-down control module further comprises a sixth transistor and a seventh transistor; wherein,

the source of the seventh transistor is connected with the drain of the fifth transistor, and the drain of the seventh transistor is connected with the second node.

7. The shift register cell of claim 5 or 6, further comprising a third pull-down module comprising an eighth transistor and a ninth transistor; wherein,

the grid electrode of the eighth transistor is connected with the first node, the source electrode of the eighth transistor is connected with the second node, and the drain electrode of the eighth transistor is connected with the second voltage signal end;

the grid electrode of the ninth transistor is connected with the first node, the source electrode of the ninth transistor is connected with the drain electrode of the sixth transistor, and the drain electrode of the ninth transistor is connected with the second voltage signal end.

8. The shift register cell of claim 1, wherein the output module comprises a tenth transistor and a second capacitor; wherein,

a grid electrode of the tenth transistor is connected with the first node, a source electrode of the tenth transistor is connected with the clock signal end, and a drain electrode of the tenth transistor is connected with the output signal end;

The first end of the second capacitor is connected with the first node, and the second end of the second capacitor is connected with the output signal end.

9. The shift register cell of claim 8, wherein the first pull-down module comprises an eleventh transistor and a twelfth transistor; wherein,

the grid electrode of the eleventh transistor is connected with the second node, the source electrode of the eleventh transistor is connected with the first node, and the drain electrode of the eleventh transistor is connected with the second voltage signal end;

the grid electrode of the twelfth transistor is connected with the second node, the source electrode of the twelfth transistor is connected with the output signal end, and the drain electrode of the twelfth transistor is connected with the second voltage signal end.

10. The shift register cell of claim 8, further comprising a reset module comprising a thirteenth transistor and a fourteenth transistor; wherein,

a grid electrode of the thirteenth transistor is connected with a first reset signal end, a source electrode of the thirteenth transistor is connected with the first node, and a drain electrode of the thirteenth transistor is connected with the second voltage signal end;

The grid electrode of the fourteenth transistor is connected with a second reset signal end, the source electrode of the fourteenth transistor is connected with the output signal end, and the drain electrode of the fourteenth transistor is connected with the second voltage signal end.

11. The shift register cell of claim 1, further comprising a pull-down charging module comprising a fifteenth transistor;

the grid electrode of the fifteenth transistor is connected with the third input signal end, the drain electrode of the fifteenth transistor is connected with the fourth voltage signal end, and the source electrode of the fifteenth transistor is connected with the first node.

12. The shift register cell of claim 1, wherein the input module comprises a sixteenth transistor;

the grid electrode of the sixteenth transistor is connected with the first input signal end, the source electrode of the sixteenth transistor is connected with the first voltage signal end, and the drain electrode of the sixteenth transistor is connected with the first node.

13. A shift register, comprising: multistage shift register unit according to any one of claims 1 to 12; wherein,

the first input signal end of the shift register unit of the nth stage is connected with the output signal end of the shift register unit of the (n-1) th stage; the second input signal end of the shift register unit of the nth stage is connected with the output signal end of the shift register unit of the n-2 th stage, and n is an integer larger than 2.

14. The shift register of claim 13, wherein in case the shift register cell comprises a pull-down charging module, the third input signal terminal of the n-th stage of the shift register cell is connected to the output signal terminal of the n+1-th stage of the shift register cell.

15. A display device comprising a shift register as claimed in claim 13 or 14.

16. A driving method applied to the shift register unit according to any one of claims 1 to 12, characterized in that the method comprises:

in the second stage, the first input signal end inputs high potential, the second input signal end inputs low potential, the potential of the first node is pulled up through the first voltage signal end, and the second end of the first capacitor is charged through the first voltage signal end so as to further pull up the potential of the third node; wherein the charge amount of the first voltage signal end to the second end of the first capacitor is positively correlated with the potential of the first node;

in the fourth stage, under the control of the third node, the potential of the second node is pulled up through a third voltage signal terminal; and under the control of the second node, the potential of the first node is pulled down through a second voltage signal terminal.