CN117015298A - Capacitor forming method, capacitor array structure and semiconductor device - Google Patents

Capacitor forming method, capacitor array structure and semiconductor device Download PDF

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Publication number
CN117015298A
CN117015298A CN202210445625.3A CN202210445625A CN117015298A CN 117015298 A CN117015298 A CN 117015298A CN 202210445625 A CN202210445625 A CN 202210445625A CN 117015298 A CN117015298 A CN 117015298A
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CN
China
Prior art keywords
electrode
thickness
capacitor
dielectric
forming
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Pending
Application number
CN202210445625.3A
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Chinese (zh)
Inventor
金学云
金玄永
郭挑远
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Chengdu Gaozhen Technology Co ltd
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Chengdu Gaozhen Technology Co ltd
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Priority to CN202210445625.3A priority Critical patent/CN117015298A/en
Publication of CN117015298A publication Critical patent/CN117015298A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a capacitor forming method, a capacitor array structure and a semiconductor device, which are used for solving the problem that a top electrode in the existing capacitor array structure is large in deformation in the forming process. The capacitor forming method comprises the following steps: providing a substrate; forming a plurality of first electrodes on a substrate, wherein the first electrodes are arranged at intervals; forming a dielectric layer on the substrate and all the first electrodes, wherein the dielectric layer between two adjacent first electrodes forms a filling gap; forming a second electrode on the dielectric layer, wherein the filling degree of the second electrode in the filling gap is not less than 91%; and removing part of the second electrode in the filling gap by adopting an etching process to form a continuous uniform-thickness second electrode. When the capacitor forming method provided by the invention is adopted, the deformation of the second electrode is smaller in the forming process, so that the margin of the whole edge of the capacitor is larger, and the subsequent etching process is convenient to carry out.

Description

Capacitor forming method, capacitor array structure and semiconductor device
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a capacitor forming method, a capacitor array structure, and a semiconductor device.
Background
Capacitors are important building blocks in integrated circuits and are widely used in various chips. With the continuous progress of semiconductor integrated circuit manufacturing technology, the performance of semiconductor devices is also continuously improved. How to control the capacitance of a capacitor to precisely control an analog circuit in the process of improving the integration level of an integrated circuit is an important subject.
In the prior art, a capacitor within a semiconductor device typically includes a bottom electrode, a dielectric layer, and a top electrode. The bottom electrode is typically deposited on the semiconductor substrate by a deposition process, a dielectric layer is formed on the bottom electrode by a deposition process, and a top electrode is formed on the dielectric layer by a deposition process. The top electrode is generally made of a metal conductive material, and in the final forming process of the top electrode, certain strain is generated on the top electrode due to interaction among atoms in the top electrode, and the dielectric layer is pulled when certain strain is generated on the top electrode due to interaction force generated when the top electrode is bonded with the dielectric layer. Particularly in the formation of capacitor array structures, the top electrode is particularly prone to damage to the dielectric layer and the bottom electrode due to the large electrode scale, resulting in bending or cracking of the dielectric layer or the bottom electrode. Therefore, in the existing capacitor forming process, there is a high requirement for controlling the thickness of the top electrode, i.e., the thickness of the top electrode needs to be made thinner. However, when the thickness of the top electrode is controlled to be thinner, the top electrode is easier to deform, typically shrinkage, which results in a decrease in the margin of the whole capacitor array structure, so that the difficulty of the subsequent etching process is increased.
Disclosure of Invention
The invention aims to provide a capacitor forming method, a capacitor array structure and a semiconductor device.
The invention is realized by the following technical scheme:
in one aspect, the present invention provides a capacitor forming method comprising the steps of:
providing a substrate;
forming a plurality of first electrodes on the substrate, wherein the plurality of first electrodes are arranged at intervals;
forming a dielectric layer on the substrate and all the first electrodes, wherein the dielectric layer between two adjacent first electrodes forms a filling gap;
forming a second electrode on the dielectric layer, wherein the filling degree of the second electrode in the filling gap is not less than 91%;
and removing part of the second electrode in the filling gap by adopting an etching process to form a continuous uniform-thickness second electrode.
In some possible embodiments, the thickness of the continuous equal thickness second electrode is 120A-200A.
In some possible embodiments, the thickness of the continuous equal thickness second electrode is no greater than 120A.
In some possible embodiments, a SiGe layer having a thickness of 500-1000A is used as an etch mask in an etching process to form a continuous uniform thickness second electrode having a thickness of no more than 120A.
In some possible embodiments, in the etching process, a W layer having a thickness of 300A to 500A obtained by a chemical vapor deposition process is used as an etching mask to form a continuous uniform thickness second electrode having a thickness of not more than 120A.
In some possible embodiments, in the etching process, a WN layer having a thickness of 300A to 500A obtained by a chemical vapor deposition process is used as an etching mask to form a continuous uniform thickness second electrode having a thickness of not more than 120A.
In some possible embodiments, the material of the second electrode is TiN.
In some possible embodiments, the second electrode is obtained by an atomic layer deposition process.
In another aspect, the present invention provides a capacitor array structure comprising:
the first electrode is provided with a plurality of first convex columns which are arranged at intervals, and a first pore canal is formed between two adjacent first convex columns;
the dielectric layer is fully coated on one side of the first electrode, which is provided with the first convex columns, so as to form a plurality of dielectric convex columns, and dielectric pore channels are formed between the adjacent dielectric convex columns;
the second electrode is provided with a plurality of second convex columns which are arranged at intervals, and a second pore canal is formed between two adjacent second convex columns;
the dielectric convex columns are positioned in the second pore channels, the second convex columns are positioned in the dielectric pore channels, wherein the second convex columns are completely attached to the inner walls of the dielectric pore channels, and the volume of the second convex columns is not less than 91% of the volume of the dielectric pore channels.
In still another aspect, the present invention provides a semiconductor device, including a power supply and the capacitor array structure described above, where two power output sides of the power supply are connected to a first electrode and a second electrode, respectively.
Compared with the prior art, the invention has the following advantages and beneficial effects:
according to the capacitor forming method, the capacitor array structure and the semiconductor device, the second electrode is formed into the filling structure in the gap between the first electrodes, when the filling rate of the second electrode is not less than 91%, the second electrode between the two first electrodes can shrink in smaller space during final forming, the whole deformation of the second electrode is smaller, so that the second electrode and the dielectric layer are less in pulling force, the second electrode and the dielectric layer are not easy to damage, and meanwhile, the whole deformation of the second electrode is smaller, the margin of the edge of the capacitor array structure is larger, the subsequent etching process can be facilitated, and the etching difficulty is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional structure of a capacitor array structure according to an embodiment of the present invention;
fig. 2 is an exploded view of a cross-sectional structure of a capacitor array according to an embodiment of the present invention.
In the drawings, the reference numerals and corresponding part names:
1-first electrode, 11-first stud, 12-first via, 2-second electrode, 21-second stud, 22-second via, 3-dielectric layer, 31-dielectric stud, 32-dielectric via.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: no such specific details are necessary to practice the invention. In other instances, well-known structures, circuits, materials, or methods have not been described in detail in order not to obscure the invention.
Throughout the specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean: a particular feature, structure, or characteristic described in connection with the embodiment or example is included within at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an example," or "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Moreover, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and that the illustrations are not necessarily drawn to scale. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, the terms "front", "rear", "left", "right", "upper", "lower", "vertical", "horizontal", "high", "low", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, merely to facilitate description of the present invention and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the scope of the present invention.
Examples
In one embodiment of a method for forming a capacitor provided by the present invention, the method comprises the steps of:
s1, providing a substrate.
The substrate is mainly used as a carrier substrate for the capacitor, and is generally configured as a wafer. Of course, in this embodiment, the specific shape of the substrate is not limited, and in other embodiments, the substrate may also include substances, components and/or devices that may be formed or mounted or disposed on the wafer. The substrate may be formed of any one selected from Si, siO2, al2O3, mgO, laAlO3, and SrTiO3, or a combination thereof. However, if the capacitance layer is formed of polysilicon, the substrate may be formed of silicon to increase adhesion between the substrate and the capacitance layer. For example, a silicon wafer may be used as the substrate.
S2, forming a plurality of first electrodes 1 on the substrate, wherein the plurality of first electrodes 1 are arranged at intervals.
Referring to fig. 2, in the present embodiment, the first electrode 1 is a bottom electrode of a single capacitor in a capacitor array structure, and the material of the first electrode 1 may include metal nitride, such as TiN, but is not limited thereto. The first electrodes 1 are arranged in a line to form an array structure.
And S3, forming a dielectric layer 3 on the substrate and all the first electrodes 1, wherein the dielectric layer 3 between two adjacent first electrodes 1 forms a filling gap.
The dielectric layer 3 is obtained by a chemical deposition or physical deposition process, but is not limited thereto. The dielectric layer 3 may be formed of a paraelectric material such as a metal oxide or the like. The dielectric layer 3 may include any one of metal oxides such as Al2O3, zrO2, hfO2, or the like, or a combination thereof. The dielectric layer 3 may contain a metal oxide such as Al2O3, zrO2, hfO2, or the like as a single material and be formed of a metal oxide such as Al2O3, zrO2, hfO2, or the like as a single material. Alternatively, the dielectric layer 3 may also be formed of a composite layer to improve the anti-creeping property. In the case where the dielectric layer 3 is formed of a composite layer, the dielectric layer 3 may be a ZrO2-Al2O3-ZrO2 composite layer.
The dielectric layer 3 is formed on the first electrode 1 and the substrate, and then is formed in a continuous folded plate shape having a certain thickness, and the cross-sectional shape thereof is serpentine, so that the dielectric layer 3 between adjacent first electrodes 1 forms a filling gap.
And S4, forming a second electrode 2 on the dielectric layer 3, wherein the filling degree of the second electrode 2 in the filling gap is not less than 91%.
The second electrode 2 is formed on the dielectric layer 3 using an atomic layer deposition process. The second electrode 2 is in a coating state on the dielectric layer 3, and in particular, the second electrode 2 is in a filled state in the filled gap, and the filling degree is not less than 91%. Wherein, when depositing the second electrode 2, it needs to ensure that it is completely attached to the dielectric layer 3 in the filling gap, so as to prevent the second electrode 2 in the filling gap from being distorted in the final forming process. When the second electrode 2 is formed in the filling gap in a filled state, the deformation amount generated in the final forming is relatively small, and the dielectric layer 3 in the filling gap is completely attached to the second electrode 2, so that the unfilled space is located inside the second electrode 2, and during the final forming of the second electrode 2, the deformed part is generated inside the second electrode 2, and the stress of the second electrode 2 itself is greatly released, so that the acting force on the dielectric layer 3 is relatively small. The strain of the second electrode 2 in the filling gap is released in the second electrode 2 in the forming process, and the second electrode 2 in the filling gap has smaller pulling force for the second electrode 2 outside the filling gap, so that the deformation of the second electrode 2 in the forming process is smaller, the deformation of the second electrode 2 at the integral edge of the capacitor is smaller, namely the margin of the second electrode 2 at the integral edge of the capacitor is larger, and the subsequent etching process is facilitated. The material of the second electrode 2 may include a metal nitride such as TiN, but is not limited thereto.
Note that, the filling degree of the second electrode 2 in the filling gap does not reach 100% by any process in the prior art, so the upper limit of the filling degree is not limited in this embodiment. However, as will be appreciated by those skilled in the art, the degree of filling in this example is 91% to 100%.
And S5, removing part of the second electrode 2 in the filling gap by adopting an etching process to form a continuous equal-thickness second electrode 2.
By providing a barrier layer on the second electrode 2 at a position corresponding to each first electrode 1 to perform etching as a mask, only the portion of the second electrode 2 filling the gap is removed at this time, and after etching to a predetermined depth, a continuous uniform thickness of the second electrode 2 can be formed.
In some possible embodiments, the thickness of the continuous equal thickness second electrode 2 is 120A to 200A.
In some possible embodiments, the thickness of the continuous equal thickness second electrode 2 may also be set to be not more than 120A.
When the thickness of the continuous equal-thickness second electrode 2 is set to be not more than 120A, etching is performed by providing an etching mask of a certain thickness. Specifically, in the etching process, an example is to use a SiGe layer having a thickness of 500 to 1000A as an etching mask and etch the second electrode 2 filled in the gap, thereby obtaining a continuous uniform thickness second electrode 2 having a thickness of not more than 120A. Another example is to use a W layer having a thickness of 300A to 500A obtained by a chemical vapor deposition process as an etching mask and etch the second electrode 2 filled in the gap, thereby obtaining a continuous uniform thickness second electrode 2 having a thickness of not more than 120A. A further example is to use a WN layer having a thickness of 300A to 500A obtained by a chemical vapor deposition process as an etching mask and etch the second electrode 2 filled in the gap, thereby obtaining a continuous uniform thickness second electrode 2 having a thickness of not more than 120A.
As shown in fig. 1 to 2, in one embodiment of a capacitor array structure provided by the present invention, the capacitor array structure includes:
the first electrode 1, the first electrode 1 has a plurality of first convex columns 11 which are arranged at intervals, and a first pore canal 12 is formed between two adjacent first convex columns 11;
the dielectric layer 3 is entirely coated on one side of the first electrode 1, which is provided with the first convex columns 11, so as to form a plurality of dielectric convex columns 31, and dielectric pore channels 32 are formed between the adjacent dielectric convex columns 31;
the second electrode 2 is provided with a plurality of second convex columns 21 which are arranged at intervals, and a second pore canal 22 is formed between two adjacent second convex columns 21;
the dielectric pillar 31 is located in the second hole 22, and the second pillar 21 is located in the dielectric hole 32, where the second pillar 21 is completely attached to the inner wall of the dielectric hole 32, and the volume of the second pillar 21 is not less than 91% of the volume of the dielectric hole 32.
In one embodiment of a semiconductor device provided by the present invention, the semiconductor device includes a power supply and the capacitor array structure described in the foregoing embodiment, where two power output sides of the power supply are connected to the first electrode 1 and the second electrode 2, respectively.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (10)

1. A method of forming a capacitor, comprising the steps of:
providing a substrate;
forming a plurality of first electrodes (1) on the substrate, wherein the plurality of first electrodes (1) are arranged at intervals;
forming a dielectric layer (3) on the substrate and all the first electrodes (1), wherein the dielectric layer (3) between two adjacent first electrodes (1) forms a filling gap;
forming a second electrode (2) on the dielectric layer (3), wherein the filling degree of the second electrode (2) in the filling gap is not less than 91%;
and removing part of the second electrode (2) in the filling gap by adopting an etching process to form a continuous equal-thickness second electrode (2).
2. The method of forming a capacitor according to claim 1, wherein the thickness of the continuous uniform thickness second electrode (2) is 120A to 200A.
3. The capacitor forming method according to claim 1, wherein the thickness of the continuous equal thickness second electrode (2) is not more than 120A.
4. A capacitor forming method according to claim 3, characterized in that in the etching process, a SiGe layer having a thickness of 500-1000A is used as an etching mask to form the continuous uniform thickness second electrode (2) having a thickness of not more than 120A.
5. A capacitor forming method according to claim 3, wherein in the etching process, a W layer having a thickness of 300A to 500A obtained by a chemical vapor deposition process is used as an etching mask to form the continuous uniform thickness second electrode (2) having a thickness of not more than 120A.
6. A capacitor forming method according to claim 3, characterized in that in the etching process, a WN layer having a thickness of 300A to 500A obtained by a chemical vapor deposition process is employed as an etching mask to form the continuous uniform thickness second electrode (2) having a thickness of not more than 120A.
7. The method of forming a capacitor according to claim 1, wherein the material of the second electrode (2) is TiN.
8. The capacitor forming method according to claim 1, characterized in that the second electrode (2) is obtained by an atomic layer deposition process.
9. A capacitor array structure, comprising:
the electrode comprises a first electrode (1), wherein the first electrode (1) is provided with a plurality of first convex columns (11) which are arranged at intervals, and a first pore channel (12) is formed between two adjacent first convex columns (11);
the dielectric layer (3), the said dielectric layer (3) is totally coated on one side with first convex pillar (11) on the first electrode (1) in order to form several dielectric convex pillars (31), form the dielectric duct (32) between the adjacent dielectric convex pillars (31);
the second electrode (2), the said second electrode (2) has several second convex columns (21) arranged at intervals, form the second pore canal (22) between two adjacent second convex columns (21);
the dielectric convex columns (31) are located in the second pore channels (22), the second convex columns (21) are located in the dielectric pore channels (32), wherein the second convex columns (21) are completely attached to the inner walls of the dielectric pore channels (32), and the volume of the second convex columns (21) is not smaller than 91% of the volume of the dielectric pore channels (32).
10. A semiconductor device comprising a power supply and a capacitor array structure as claimed in claim 9, wherein the two power supply output sides of the power supply are connected to the first electrode (1) and the second electrode (2), respectively.
CN202210445625.3A 2022-04-26 2022-04-26 Capacitor forming method, capacitor array structure and semiconductor device Pending CN117015298A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210445625.3A CN117015298A (en) 2022-04-26 2022-04-26 Capacitor forming method, capacitor array structure and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210445625.3A CN117015298A (en) 2022-04-26 2022-04-26 Capacitor forming method, capacitor array structure and semiconductor device

Publications (1)

Publication Number Publication Date
CN117015298A true CN117015298A (en) 2023-11-07

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CN202210445625.3A Pending CN117015298A (en) 2022-04-26 2022-04-26 Capacitor forming method, capacitor array structure and semiconductor device

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