CN111900166B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN111900166B CN111900166B CN202010575383.0A CN202010575383A CN111900166B CN 111900166 B CN111900166 B CN 111900166B CN 202010575383 A CN202010575383 A CN 202010575383A CN 111900166 B CN111900166 B CN 111900166B
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- side wall
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000004380 ashing Methods 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 238000012886 linear function Methods 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 238000002360 preparation method Methods 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present disclosure provides a semiconductor structure and a method of manufacturing the same, the semiconductor structure comprising: a semiconductor substrate; a plurality of linear functional parts located on the semiconductor substrate; an air gap located at both sides of the linear function part; the air gap consists of a vertical part and a horizontal part, has an L-shaped vertical section shape, and is positioned outside the side wall of the linear functional part. The linear functional component in the semiconductor structure has the advantages that the air gap is arranged outside the side wall of the linear functional component, so that parasitic capacitance can be effectively reduced, meanwhile, the preparation steps of the air gap are fewer, the process is simple, the cost can be well reduced, and the yield can be improved.
Description
Technical Field
The disclosure relates to the field of semiconductor technology, in particular to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor memory and an electronic device.
Background
Among the main characteristics of DRAM (Dynamic Random Access Memory) and dynamic random access memory, there are capacitance characteristics of linear functional parts such as bit lines and metal lines, which are closely related to data sensing margin (Data Sensing Margin). Although the size of the DRAM is continuously reduced, the sensing margin must be kept as high as possible in the previous generation, and for this reason, the capacitance characteristics of the line-shaped functional portion also need to be continuously reduced. The main factors determining the capacitance characteristics of the linear function portion are the thickness and dielectric constant of the sidewall of the linear function portion. The side wall of the linear functional part in the prior art generally adopts a three-layer structure, such as a SiN/oxide/SiN three-layer structure, but the parasitic capacitance of the existing side wall is still higher, so that an Air Gap (Air Gap) is required to be manufactured on the side wall to further reduce the parasitic capacitance, however, the conventional Air Gap manufacturing process has a plurality of steps and high difficulty.
Disclosure of Invention
The disclosure provides a semiconductor structure, a manufacturing method thereof, a semiconductor memory and an electronic device.
A first aspect of the present disclosure provides a semiconductor structure comprising:
a semiconductor substrate;
a plurality of linear functional parts located on the semiconductor substrate;
air gaps respectively positioned outside two side walls of the linear functional part;
wherein the air gap is composed of a vertical portion and a horizontal portion, and forms an L-shaped vertical cross-section.
A second aspect of the present disclosure provides a method for fabricating a semiconductor structure, including:
providing a semiconductor substrate, and forming a plurality of linear functional parts on the semiconductor substrate;
a sacrificial core mould is formed at the lower part between the side walls of the adjacent linear functional parts, and an upper side wall is formed at the upper part; the sacrificial core mould comprises two vertical parts and a horizontal part, wherein the vertical parts are respectively positioned outside the side walls of the adjacent linear functional parts, and the horizontal parts connect the bottoms of the two vertical parts; the upper side wall is positioned outside the side wall above the vertical part;
forming a first outer side wall on the outer sides of the upper side wall and the vertical part;
removing the sacrificial mandrel to form an air gap space;
and depositing a second external side wall on the whole semiconductor structure to close the air gap space, thereby forming an air gap.
A third aspect of the present disclosure provides an electronic device comprising the semiconductor structure described above.
Compared with the prior art, the utility model has the advantages that:
the linear functional component in the semiconductor structure has the advantages that the air gap is arranged outside the side wall of the linear functional component, so that parasitic capacitance can be effectively reduced, meanwhile, the preparation steps of the air gap are fewer, the process is simple, the cost can be well reduced, and the yield can be improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIGS. 1a-1j are schematic diagrams of the present disclosure where the line feature is a bit line structure fabrication method;
fig. 2 a-2 b are schematic illustrations of a product structure in which the wire feature of the present disclosure is an aluminum wire structure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
In order to solve the above-mentioned problems in the prior art, an embodiment of the present disclosure provides a semiconductor structure, a method for manufacturing the same, a semiconductor memory, and an electronic device, which are described below with reference to the accompanying drawings.
Referring first to fig. 1j, fig. 1j shows a schematic cross-sectional view of a semiconductor provided by the present disclosure. As shown in fig. 1j, the semiconductor structure may be, for example, a DRAM (Dynamic Random Access Memory ), and may include: a semiconductor substrate, and a plurality of linear features on the semiconductor substrate. In this embodiment, the linear feature may be a Bit Line structure 100 (Bit Line), and the Bit Line structure 100 may include a polysilicon layer 110, a metal tungsten layer 120 on the polysilicon layer 110, and a silicon nitride layer 130 on the metal tungsten layer 120, and may further include sidewalls 140 on both sides of the Bit Line structure, where the sidewalls 140 may be, for example, silicon nitride layers. On the outside of the sidewall 140, an upper sidewall 200 at the upper portion and an air gap 300 at the lower portion may be included. The air gap 300 may be formed by a vertical portion 310 and a horizontal portion 320, as shown in fig. 1j, where the vertical portion 310 and the horizontal portion 320 form an "L" shape in vertical section, and the vertical portion 310 is located outside the side wall 140 of the linear function. The upper sidewall 200 may be located above the vertical portion 310 of the air gap 300 and attached to the outside of the sidewall 140 of the linear functional portion, and the material of the upper sidewall 200 may be oxide, for example. And may further include an outer sidewall 400 positioned outside of the air gap 300 and the upper sidewall 200, the inner side of the outer sidewall 400 defining the inner side of the air gap 300 and the upper sidewall 200 (i.e., the inner side of the outer sidewall 400 conforms to the outer sides of the air gap 300 and the upper sidewall 200), thereby sealing the air gap 300. The exterior sidewalls may include a first exterior sidewall 410 and a second exterior sidewall 420, among others. The first outer sidewall 410 is located outside the upper sidewall 200 and the vertical portion 310 of the air gap 300. And the second outer sidewall 420 includes a vertical portion 421 and a horizontal portion 422, wherein the vertical portion 421 is located outside the first outer sidewall 410 and the horizontal portion 320 of the air gap 300, one end of the horizontal portion 422 is connected to the vertical portion 421 as a unit, and the other end is connected to the horizontal portion 422 of the second outer sidewall 420 of the adjacent bit line structure as a unit. The first outer sidewall 410 and the second outer sidewall 420 may be, for example, silicon nitride layers.
Next, a method for manufacturing the semiconductor structure in this embodiment will be described in detail with reference to fig. 1a to 1 j:
as shown in fig. 1a, a semiconductor substrate may be provided, a plurality of bit line structures 100 may be formed on the semiconductor substrate, the bit line structures 100 may be formed by sequentially depositing a polysilicon layer 110, a metal tungsten layer 120 on the polysilicon layer 110, and a silicon nitride layer 130 on the metal tungsten layer 120, and then, sidewalls 140 on both sides of the bit line structures may be formed by a sidewall process, and the sidewalls 140 may be, for example, silicon nitride layers.
Subsequently, as shown in FIG. 1b, a Spin-on process may be used to fill the sacrificial mold layer 340 between the sidewalls 140 of adjacent bit line structures, the sacrificial mold layer 340 may be Spin-on hard mask composition (SOH), spin-on Carbon (SOC), or Spin-on SiGe. In other embodiments of the invention, siGe may also be formed by epitaxy or other conventional deposition processes. In the present disclosure, the above materials and spin-coating process are used to replace the commonly used oxide materials and deposition process to prepare the sacrificial mold Layer of the air gap (which may also be referred to as the core mold Layer of the air gap, mandrel Layer); it is known that when an oxide material is used as the sacrificial mold layer, a wet etching process is required to be used to remove the sacrificial core mold to obtain the air gap, so that the process steps and equipment are increased, and the manufacturing difficulty is high.
Subsequently, as shown in fig. 1c, the sacrificial mold layer 340 may be etched back to the level of the air gap that is ultimately desired to be produced, for example, by a conventional ash stripping (ash) process.
Subsequently, as shown in fig. 1d, an upper sidewall layer 210 may be deposited over the entire semiconductor structure, the deposition process employing an atomic layer deposition process (ALD), and the upper sidewall layer 210 may be, for example, an oxide.
Subsequently, as shown in fig. 1e, the bottom of the upper sidewall layer 210 may be etched away to form the upper sidewall 200.
Subsequently, as shown in fig. 1f, the sacrificial mold layer 340 may be etched down along the dimension defined by the upper sidewall 200 and using the upper sidewall 200 as a mask to form a sacrificial core mold 350, where the etching may be performed by a conventional Ashing and stripping (Ashing) process; the sacrificial core mold 350 obtained by etching may include two vertical portions 351 and one horizontal portion 352, the vertical portions 351 are respectively located outside the sidewalls 140 of the adjacent bit line structures, the horizontal portions 352 connect bottoms of the two vertical portions 351, and the upper sidewall 200 may be located outside the sidewalls 140 above the vertical portions 351.
Subsequently, as shown in fig. 1g, a first outer sidewall layer 411 may be deposited over the entire semiconductor structure, the first outer sidewall layer 411 may be, for example, silicon nitride.
Subsequently, as shown in fig. 1h, the bottom of the first outer sidewall layer 411 may be etched away to form a first outer sidewall 410, the first outer sidewall 410 being located outside the upper sidewall 200 and the vertical portion 351 of the sacrificial mandrel 350.
Thereafter, as shown in FIG. 1i, sacrificial plug 350 may be removed to form air gap space 300' below the upper sidewall, and in particular, sacrificial plug 350 may be removed using a conventional ash stripping (ash and Strip) process. As described above, since SOH and other spin-coating materials are used for the sacrificial mold layer in the present disclosure, a wet etching process and equipment are not required to be used for removing the sacrificial core mold 350, a common ashing process can be used, and the sacrificial core mold layer can be formed in the same process chamber, so that the process steps and equipment are greatly saved, and the production cost and the manufacturing difficulty are reduced.
Subsequently, as shown in fig. 1j, a second outer sidewall 420 may be deposited over the entire semiconductor structure to seal the air gap 300', the second outer sidewall 420 may be, for example, silicon nitride. The second outer sidewall 420 may include a vertical portion 421 and a horizontal portion 422, wherein the vertical portion 421 is located outside the first outer sidewall 410 and the horizontal portion 320 of the air gap 300, and one end of the horizontal portion 422 is connected to the vertical portion 421 as a unit, and the other end is connected to the horizontal portion 422 of the second outer sidewall 420 of the adjacent bit line structure as a unit.
The semiconductor structure of another embodiment of the present disclosure may be, for example, a DRAM, and the linear functional component may be an aluminum Metal Line structure (Al Metal Line), as shown in fig. 2a, which is merely to replace the bit Line structure 100 in the first embodiment with an aluminum Metal Line structure 100', wherein the aluminum Metal Line structure 100' may be, for example, prepared by sequentially depositing an aluminum Metal layer 110', a titanium nitride layer 120' on the aluminum Metal layer 110', and a silicon nitride layer on the outermost side of the aluminum Metal Line structure, and both sides of the silicon nitride layer form sidewalls 130' of the aluminum Metal Line structure 100 '. Except for the aluminum wire structure 100', the air gap structure and the manufacturing method of the present embodiment are the same as those of the bit line structure, and will not be described or illustrated again, and the air gap of the finally prepared aluminum wire structure is shown in fig. 2b, wherein the same reference numerals have the same meanings as those in the first embodiment.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (14)
1. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of linear functional parts located on the semiconductor substrate;
air gaps respectively positioned outside two side walls of the linear functional part;
wherein the air gap consists of a vertical part and a horizontal part, and forms an L-shaped vertical section shape;
the air gap sealing device is characterized by further comprising an upper side wall positioned above the vertical part of the air gap and an outer side wall positioned outside the air gap, wherein the upper side wall and/or the outer side wall are/is used for sealing the air gap.
2. The semiconductor structure of claim 1, wherein:
the sidewall includes an outermost silicon nitride layer.
3. The semiconductor structure of claim 1, wherein:
the upper side wall is oxide.
4. The semiconductor structure of claim 1, wherein:
the inner side surface of the outer side wall defines the outer side surface of the air gap.
5. The semiconductor structure of any one of claims 1-4, wherein:
the outer side wall comprises a first outer side wall and a second outer side wall;
the first outer side wall is positioned outside the vertical part of the air gap;
the second outer side wall comprises a vertical portion and a horizontal portion, wherein the vertical portion is located on the outer side of the horizontal portion of the first outer side wall and the air gap, one end of the horizontal portion is connected with the vertical portion into a whole, and the other end of the horizontal portion is connected with the horizontal portion of the second outer side wall of the adjacent bit line structure into a whole.
6. The semiconductor structure of any one of claims 1-4, wherein:
the outer side wall is silicon nitride.
7. The semiconductor structure of any one of claims 1-4, wherein:
the linear functional part is in a bit line structure or a metal line structure.
8. The semiconductor structure of any one of claims 1-4, wherein:
the semiconductor structure is a dynamic random access memory.
9. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, and forming a plurality of linear functional parts on the semiconductor substrate;
a sacrificial core mould is formed at the lower part between the side walls of the adjacent linear functional parts, and an upper side wall is formed at the upper part; the sacrificial core mould comprises two vertical parts and a horizontal part, wherein the vertical parts are respectively positioned outside the side walls of the adjacent linear functional parts, and the horizontal parts connect the bottoms of the two vertical parts; the upper side wall is positioned outside the side wall above the vertical part;
forming a first outer side wall on the outer sides of the upper side wall and the vertical part;
removing the sacrificial mandrel to form an air gap space;
and depositing a second external side wall on the whole semiconductor structure to close the air gap space, thereby forming an air gap.
10. The method of manufacturing according to claim 9, wherein:
the lower part between the side walls of the adjacent linear functional parts forms a sacrificial core mould, the upper part forms an upper side wall, comprises,
filling a sacrificial mold layer between the side walls of the adjacent linear functional parts;
etching the sacrificial mold layer back to the height of the air gap;
depositing an upper side wall layer on the whole semiconductor structure;
etching to remove the bottom of the upper side wall layer to form an upper side wall;
the sacrificial mold layer is etched down to form a sacrificial core mold.
11. The method of manufacturing according to claim 10, wherein:
the filling sacrificial mould layer adopts a spin coating or deposition process;
the sacrificial mold layer is spin-on hard mask composition, spin-on carbon, spin-on SiGe, or deposited SiGe.
12. The method of manufacturing according to claim 10, wherein:
and depositing a side wall layer on the whole semiconductor structure, and adopting an atomic layer deposition process.
13. The method of any one of claims 9-12, wherein:
and removing the sacrificial core mould by adopting an ashing stripping process.
14. The method of any one of claims 9-12, wherein:
the linear functional part is in a bit line structure or a metal line structure.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103903994A (en) * | 2012-12-26 | 2014-07-02 | 爱思开海力士有限公司 | Semiconductor device including air gaps and method of fabricating the same |
| KR20150012033A (en) * | 2013-07-24 | 2015-02-03 | 에스케이하이닉스 주식회사 | Semiconductor device with air gap and method for manufacturing the same |
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| US10923565B2 (en) * | 2018-09-27 | 2021-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned contact air gap formation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103903994A (en) * | 2012-12-26 | 2014-07-02 | 爱思开海力士有限公司 | Semiconductor device including air gaps and method of fabricating the same |
| KR20150012033A (en) * | 2013-07-24 | 2015-02-03 | 에스케이하이닉스 주식회사 | Semiconductor device with air gap and method for manufacturing the same |
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