CN111223843A - Capacitor array structure, method of manufacturing the same, and semiconductor memory including the same - Google Patents
Capacitor array structure, method of manufacturing the same, and semiconductor memory including the same Download PDFInfo
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- CN111223843A CN111223843A CN201811417939.2A CN201811417939A CN111223843A CN 111223843 A CN111223843 A CN 111223843A CN 201811417939 A CN201811417939 A CN 201811417939A CN 111223843 A CN111223843 A CN 111223843A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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Abstract
A capacitor array structure is provided, which is arranged on a semiconductor substrate and comprises an upper electrode layer, a lower electrode layer and a capacitance medium layer adhered between the upper electrode layer and the lower electrode layer, wherein the lower electrode layer is provided with a step surface in a direction vertical to the substrate. The invention forms the lower electrode layer by two times, thereby solving the problem of etching stop generated when the groove with high depth-width ratio is etched.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a capacitor array structure, a manufacturing method thereof and a semiconductor memory comprising the capacitor array structure.
Background
The memory capacitor is an essential element in an integrated circuit, and has functions of voltage adjustment, filtering, charge storage, and the like in the circuit.
The vertical capacitor is formed by forming a deep groove in a substrate, and the side wall of the deep groove is used for providing a main plate area, so that the occupied area of the capacitor on the surface of a chip is reduced, and a larger capacitance can be obtained.
With the improvement of the integration level of a semiconductor device, the size of a capacitor is continuously reduced, the depth of a groove is increased, and meanwhile, the size of an opening is continuously reduced, so that the depth-to-width ratio of the groove is greatly increased, and the etching difficulty is increased. When etching a trench with a high aspect ratio, the problem of etch stop is likely to occur.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks, the present invention provides a memory capacitor, a method of manufacturing the same, and a semiconductor memory including the same.
The capacitor array structure is arranged on a semiconductor substrate and comprises an upper electrode layer, a lower electrode layer and a capacitance medium layer adhered between the upper electrode layer and the lower electrode layer, and is characterized in that the lower electrode layer is provided with a step surface in a direction vertical to the substrate.
According to an embodiment of the present invention, the lower electrode layer includes a first lower electrode layer and a second lower electrode layer, and a connection surface of the first lower electrode layer and the second lower electrode layer constitutes the step surface.
According to another embodiment of the present invention, the first lower electrode layer and the second lower electrode layer have different inclinations with respect to a direction perpendicular to the substrate.
According to another embodiment of the present invention, the first lower electrode layer is inclined by 5 ° to 10 ° with respect to a direction perpendicular to the substrate, and the second lower electrode layer is inclined by 0 ° to 5 ° with respect to a direction perpendicular to the substrate.
According to another embodiment of the present invention, the first lower electrode layer electrode connection layer and the second lower electrode layer include the same material.
According to another embodiment of the present invention, the first lower electrode layer is connected to the second lower electrode layer through an electrode connection layer.
According to another embodiment of the present invention, the electrode connection layer is parallel to the substrate direction.
According to another embodiment of the present invention, the electrode connection layer and the first lower electrode layer include the same material.
According to another embodiment of the present invention, the thickness of the electrode connection layer is 20 to 30 nm.
Another aspect of the present invention provides a method for manufacturing a capacitor array structure, including: providing a substrate with a plurality of capacitance contact points which are distributed at intervals; sequentially forming a first sacrificial layer and a first supporting layer on the substrate; forming a first capacitor hole on the first support layer and the first sacrificial layer by an etching process, wherein the capacitor contact point is exposed out of the first capacitor hole; forming a first lower electrode layer on the inner wall of the first capacitor hole; forming a capacitor filling layer in the first capacitor hole; sequentially forming a second sacrificial layer and a second supporting layer on the first supporting layer; etching the second sacrificial layer and the second support layer by an etching process to form a second capacitor hole above the first capacitor hole, wherein the capacitor filling layer is exposed from the second capacitor hole, and wherein: the second capacitor hole and the first capacitor hole have different gradients in a direction opposite to the direction vertical to the substrate; forming a second lower electrode layer on the side wall of the second capacitor hole, wherein the second lower electrode layer is connected with the first lower electrode layer; removing the capacitor filling layer; removing the first sacrificial layer and the second sacrificial layer; forming a capacitance dielectric layer to cover the first lower electrode layer and the second lower electrode layer; and forming an upper electrode layer to cover the capacitance dielectric layer.
According to an embodiment of the present invention, the sidewall of the first capacitor hole is inclined toward the outside thereof by 5 ° to 10 ° with respect to the vertical direction to the substrate, and the sidewall of the second capacitor hole is inclined toward the outside thereof by 0 ° to 5 ° with respect to the vertical direction to the substrate.
According to another embodiment of the present invention, before forming the second sacrificial layer and the second support layer, a capacitor recess is formed on the capacitor filling layer, and an electrode connection layer is formed in the capacitor recess, wherein the electrode connection layer connects the first lower electrode layer and the second lower electrode layer.
According to another embodiment of the present invention, the depth of the capacitor recess is the same as the thickness of the first support layer.
According to another embodiment of the present invention, the electrode connection layer and the first and second lower electrode layers include the same material.
Another aspect of the present invention also provides a semiconductor memory device including the capacitor array structure described above.
The invention forms the lower electrode layer by two times, thereby solving the problem of etching stop generated when the groove with high depth-width ratio is etched. Furthermore, an electrode connecting layer is arranged between the first lower electrode layer and the second lower electrode layer, so that the problems of misalignment and poor contact existing when the lower electrode layers are formed twice respectively are solved.
Drawings
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 to 9 are schematic views illustrating a manufacturing process of a capacitor array structure according to an embodiment of the invention.
Wherein the reference numerals are as follows:
1: substrate
2: capacitance contact point
3: first sacrificial layer
4: a first support layer
5: a first lower electrode layer
6: capacitor filling layer
7: groove
8: electrode connecting layer
9: second sacrificial layer
10: a second supporting layer
11: a second lower electrode layer
12,13: guide opening
14: capacitor dielectric layer
15,16: upper electrode layer
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. In the drawings, the thickness of regions and layers are exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.
It should be noted that the terms "upper" and "lower" in the present invention are only relative concepts or reference to the normal use status of the product, and should not be considered as limiting.
Please refer to fig. 1-9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention in a schematic way, and are not intended to limit the present invention. The components relevant to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation can be changed freely, and the layout of the components can be more complicated.
As shown in fig. 1, a substrate 1 having a plurality of spaced capacitive contacts 2 is provided. A memory array structure is formed in the substrate 1, and the memory array structure includes a plurality of capacitor contacts 2. The memory array structure further includes a Word line (Word line) and a Bit line (Bit line), and the capacitor contact 2 is electrically connected to a source of the transistor in the memory array structure. The capacitor contact points 2 correspond to the arrangement of the capacitor array structure manufactured subsequently.
A first sacrificial layer 3 and a first support layer 4 are sequentially formed on the upper surface of the substrate 1. The first sacrificial layer 3 and the first support layer 4 may be formed by Chemical Vapor Deposition (CVD) or other suitable means. The materials of the first sacrificial layer 3 and the first support layer 4 are different, and the etching rate of the first sacrificial layer 3 is different from the etching rate of the first support layer 4 in the same etching process, which is embodied in that in the same etching process, the etching rate of the first sacrificial layer 3 is far greater than the etching rate of the first support layer 4, so that when the first sacrificial layer 3 is completely removed, the first support layer 4 is almost completely retained. The first sacrificial layer 3 and the first support layer 4 are formed of a dielectric material. Preferably, the first sacrifice layer 3 is formed of silicon oxide, and the first support layer 4 is formed of silicon nitride. The thickness of the first sacrificial layer is 500-1000 nm. The thickness of the first support layer is 20-50 nm.
As shown in fig. 2, a plurality of openings may be formed in the first support layer 4 and the first sacrificial layer 3 by etching, for defining the position and shape of the first capacitor hole. The first capacitor hole exposes the capacitor contact 2, and the sidewall of the first capacitor hole is inclined 5-10 ° with respect to the vertical substrate direction, preferably inclined outward, but not limited thereto, i.e., the first capacitor hole is formed to be narrow at the bottom and wide at the top to facilitate the subsequent filling process. The specific method may be that the first support layer 4 and the first sacrificial layer 3 are etched by using a dry etching method, a wet etching method or a method combining the dry etching method and the wet etching method, so as to form a first capacitor hole which is through up and down in the first support layer 4 and the first sacrificial layer 3, and the capacitor contact 2 is exposed out of the first capacitor hole. A first lower electrode layer 5 is formed in the first capacitor hole. Specifically, the first lower electrode Layer 5 may be deposited on the sidewall and the bottom of the first capacitor hole by Atomic Layer Deposition (ALD) or chemical vapor Deposition. The first lower electrode layer 5 may be formed of a compound including one or both of a metal Nitride and a metal Silicide, such as Titanium Nitride (Titanium Nitride), Titanium Silicide (Titanium Silicide), nickel Silicide (Titanium Silicide), Titanium silicon Nitride (TiSi)xNy) In this embodiment, the material of the first lower electrode layer 5 is preferably titanium nitride (TiN); then, the first lower electrode layer 5 on the upper surface of the first support layer 4 is removed by etching, and the first lower electrode layer 5 on the sidewall and the bottom of the first capacitor hole is remained. The bottom lower surface of the lower electrode layer 26 is bonded to the capacitor contact 2. The thickness of the first lower electrode layer 5 may be 20-30 nm.
As shown in fig. 3, a capacitor filling layer 6 is formed in the capacitor hole formed with the first lower electrode layer 5, and the upper surface of the capacitor filling layer 6 is lower than the upper surface of the first support layer 4, so that a groove 7 is formed with respect to the upper surface of the first support layer 4. A specific formation method may be to fill a dielectric material, such as silicon oxide, in the first capacitor hole formed with the first lower electrode layer 5 by using ALD or other deposition methods. Then, a part of the silicon oxide is removed by, for example, etching to form a recess with respect to the upper surface of the first support layer 4. The depth of the grooves preferably corresponds to the thickness of the first support layer 4.
As shown in fig. 4, the electrode connection layer 8 may be deposited within the groove using ALD or other deposition methods. The upper surface of the electrode connection layer 8 is flush with the first produced layer 4. The electrode connection layer 8 functions to connect the first lower electrode layer and the second lower electrode layer, and therefore the electrode connection layer 8 may be formed of a material for forming the first lower electrode layer 5, for example, a compound including one or both of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride, and preferably formed of the same material as the first lower electrode layer 5, that is, in the present embodiment, it is preferable that the electrode connection layer 8 be formed of TiN. The thickness of the electrode connection layer 8 may be 20-30 nm.
As shown in fig. 5, a second sacrificial layer 9 and a second support layer 10 are sequentially formed to cover the first support layer 4 and the electrode connection layer 8. The second sacrificial layer 9 and the second support layer 10 may be formed as in the manner of forming the first sacrificial layer 3 and the first support layer 4. The materials of the second sacrificial layer 9 and the second support layer 10 are different, so that the etching rate of the second sacrificial layer 9 and the etching rate of the second support layer 10 are much greater than the etching rate of the second support layer 10 in the same etching process, so that the second support layer 10 is almost completely retained when the second sacrificial layer 9 is completely removed. The second sacrificial layer 9 and the second support layer 10 are formed of a dielectric material. Preferably, the second sacrificial layer 9 is formed of silicon oxide and the second support layer 10 is formed of silicon nitride. The thickness of the second sacrificial layer is 500-1000 nm. The thickness of the second support layer is 20-50 nm.
As shown in fig. 6, a plurality of openings may be formed in the second support layer 10, the second sacrificial layer 9 and the electrode connection layer 8 by etching to define the position and shape of a second capacitor hole, which exposes the capacitor filling layer 6, and whose sidewall is inclined by 0 to 5 ° with respect to the vertical substrate direction, preferably, the sidewall of the second capacitor hole is vertical to the surface of the substrate 1. A second lower electrode layer 11 is formed on the sidewall of the second capacitor hole by depositing an electrode material in the second capacitor hole and then removing the electrode material formed on the capacitor filling layer 6, the second lower electrode layer 11 being connected to the electrode connection layer 8. The second lower electrode layer 11 may be formed of a material for forming the first lower electrode layer 5, for example, a compound including one or both of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride, and is preferably formed of the same material as the first lower electrode layer 5, that is, in the present embodiment, it is preferable that the second lower electrode layer 11 be formed of TiN. The thickness of the second lower electrode layer 11 may be 20-30 nm.
As shown in fig. 7, the capacitor filling layer 6 may be removed by wet etching.
As shown in fig. 8, the first sacrificial layer 3 and the second sacrificial layer 9 are removed. Specifically, the lead 12 may be formed on the second support layer 11 by dry etching, and the shape and size of the lead 12 may be selected according to the actual method, for example, square, diamond, circle, ellipse or other patterns may be selected. The second sacrificial layer 10 is then cleaned off using a wet etch process. Thereafter, the via 13 is formed on the first support layer 4 by using a dry etching method, and the shape and size of the via 13 may be selected according to an actual method, for example, a square, a diamond, a circle, an oval, or other patterns may be selected. The first sacrificial layer 3 is then cleaned off using a wet etch process.
As shown in fig. 9, a capacitor dielectric layer 14 is deposited by using an ALD method or other methods to cover the first and second lower electrode layers 5 and 11. The capacitor dielectric layer 14 may optionally be formed of a high-K dielectric material to increase the capacitance per unit area of the capacitor, including ZrOx、HfOx、ZrTiOx、RuOx、SbOx、AlOxOne or more of (a).
Thereafter, the upper electrode layers 15,16 are deposited by CVD or other methods to cover the capacitor dielectric layer 14. The material of the upper electrode layers 15,16 may include one or more of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, and P-type polysilicon. Preferably, in this embodiment, the upper electrode layer material 15,16 is generally formed of polysilicon.
In another embodiment of the present invention, as shown in fig. 9, the capacitor array structure is disposed on the semiconductor substrate 1, and includes a lower electrode layer, a capacitor dielectric layer 14 adhered between the upper electrode layer 1 and the lower electrode layer, and upper electrode layers 15 and 16. The lower electrode layer has a step surface in a direction perpendicular to the substrate. The invention solves the problem of etching stop generated by etching the high depth-to-width ratio groove in the prior art through fractional etching. And forming a step surface on the side wall of the capacitor hole easily during the step etching, so that a step surface is formed on the lower electrode layer. As shown in the figure, the lower electrode layer includes a first lower electrode layer 5 and a second lower electrode layer 11 connected to each other, and a connection face (e.g., electrode connection layer 8) therebetween constitutes a step face of the lower electrode layer. The first lower electrode layer 5 and the second lower electrode layer 11 have different inclinations with respect to a direction perpendicular to the substrate. Preferably, the first lower electrode layer 5 is inclined by 5 to 10 ° with respect to the vertical substrate direction, and the second lower electrode layer 11 is inclined by 0 to 5 ° with respect to the vertical substrate direction. Preferably, the second lower electrode layer 11 is perpendicular to the substrate surface. The first lower electrode layer 5 and the second lower electrode layer 11 can be connected through the electrode connecting layer 8, and the defect of poor contact caused by misalignment of the lower electrode layers due to previous two times of etching in the process of etching for multiple times can be overcome. The first lower electrode layer 5, the second lower electrode layer 11, and the electrode connection layer 8 may be formed of the same material, for example, TiN. The thicknesses of the first lower electrode layer 5, the second lower electrode layer 11 and the electrode connection layer 8 are 20 to 30 nm. The upper electrode layers 15,16 are formed of polysilicon. The thickness of the capacitor dielectric layer 14 is 45-55 nm.
The semiconductor memory of the invention comprises the capacitor array prepared by the above structure or method.
The invention aims to solve the problem of etching stop when a memory capacitor is formed, and the etching process is carried out step by step. During step etching, the hole alignment during the lower electrode layer deposition twice can be increased by controlling the appearance of the holes etched twice. When the lower electrode layer is deposited twice, the problem of poor contact during the deposition of the lower electrode layer twice can be solved by adding the electrode connecting layer.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A capacitor array structure is arranged on a semiconductor substrate and comprises an upper electrode layer, a lower electrode layer and a capacitance medium layer adhered between the upper electrode layer and the lower electrode layer, wherein the lower electrode layer is provided with a step surface in the direction vertical to the substrate.
2. The capacitor array structure according to claim 1, wherein the lower electrode layer includes a first lower electrode layer and a second lower electrode layer, and connection faces of the first lower electrode layer and the second lower electrode layer constitute the step face.
3. The capacitor array structure according to claim 2, wherein the first lower electrode layer and the second lower electrode layer have different inclinations with respect to a direction perpendicular to the substrate.
4. The capacitor array structure of claim 3, wherein the first lower electrode layer is inclined by 5 ° -10 ° with respect to a direction perpendicular to the substrate, and the second lower electrode layer is inclined by 0 ° -5 ° with respect to a direction perpendicular to the substrate.
5. The capacitor array structure according to claim 2, wherein the first lower electrode layer electrode connection layer and the second lower electrode layer comprise the same material.
6. The capacitor array structure according to any one of claims 2 to 5, wherein the first lower electrode layer is connected to the second lower electrode layer through an electrode connection layer.
7. The capacitor array structure of claim 6, wherein the electrode connection layer is parallel to the substrate direction.
8. The capacitor array structure of claim 6, wherein the electrode connection layer and the first lower electrode layer comprise the same material.
9. The capacitor array structure of claim 6, wherein the electrode connection layer has a thickness of 20-30 nm.
10. A method of fabricating a capacitor array structure, comprising:
providing a substrate with a plurality of capacitance contact points which are distributed at intervals;
sequentially forming a first sacrificial layer and a first supporting layer on the substrate;
forming a first capacitor hole on the first support layer and the first sacrificial layer by an etching process, wherein the capacitor contact point is exposed out of the first capacitor hole;
forming a first lower electrode layer on the inner wall of the first capacitor hole;
forming a capacitor filling layer in the first capacitor hole;
sequentially forming a second sacrificial layer and a second supporting layer on the first supporting layer;
etching the second sacrificial layer and the second support layer by an etching process to form a second capacitor hole above the first capacitor hole, wherein the capacitor filling layer is exposed from the second capacitor hole, and wherein: the second capacitor hole and the first capacitor hole have different gradients in a direction opposite to the direction vertical to the substrate;
forming a second lower electrode layer on the side wall of the second capacitor hole, wherein the second lower electrode layer is connected with the first lower electrode layer;
removing the capacitor filling layer;
removing the first sacrificial layer and the second sacrificial layer;
forming a capacitance dielectric layer to cover the first lower electrode layer and the second lower electrode layer;
and forming an upper electrode layer to cover the capacitance dielectric layer.
11. The manufacturing method according to claim 10, wherein the side wall of the first capacitor hole is inclined toward the outside thereof by 5 ° to 10 ° with respect to the vertical direction to the substrate, and the side wall of the second capacitor hole is inclined toward the outside thereof by 0 ° to 5 ° with respect to the vertical direction to the substrate.
12. The method of claim 10, further comprising forming a capacitor recess on the capacitor fill layer before forming the second sacrificial layer and the second support layer, and forming an electrode connection layer in the capacitor recess, the electrode connection layer connecting the first lower electrode layer and the second lower electrode layer.
13. The method of manufacturing of claim 12, wherein a depth of the capacitive depression is the same as a thickness of the first support layer.
14. The manufacturing method according to claim 12 or 13, wherein the electrode connection layer and the first and second lower electrode layers include the same material.
15. A semiconductor memory device comprising the capacitor array structure of any one of claims 1 to 9.
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| CN201811417939.2A CN111223843A (en) | 2018-11-26 | 2018-11-26 | Capacitor array structure, method of manufacturing the same, and semiconductor memory including the same |
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| CN113053900A (en) * | 2021-03-22 | 2021-06-29 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN113823630A (en) * | 2020-06-19 | 2021-12-21 | 长鑫存储技术有限公司 | Semiconductor device, capacitor device, and method for manufacturing capacitor device |
| WO2022022171A1 (en) * | 2020-07-31 | 2022-02-03 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method and semiconductor structure |
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| CN114420678A (en) * | 2022-03-29 | 2022-04-29 | 威海嘉瑞光电科技股份有限公司 | Capacitor structure and manufacturing method thereof |
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