CN111900166A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN111900166A CN111900166A CN202010575383.0A CN202010575383A CN111900166A CN 111900166 A CN111900166 A CN 111900166A CN 202010575383 A CN202010575383 A CN 202010575383A CN 111900166 A CN111900166 A CN 111900166A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000004380 ashing Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 238000002360 preparation method Methods 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present disclosure provides a semiconductor structure and a method of manufacturing the same, the semiconductor structure including: a semiconductor substrate; a plurality of linear functional portions on the semiconductor substrate; air gaps positioned on both sides of the linear functional part; the air gap is composed of a vertical part and a horizontal part, and has an L-shaped vertical section shape, and the vertical part is positioned outside the side wall of the linear functional part. The air gap is arranged outside the side wall of the linear functional component in the semiconductor structure, so that parasitic capacitance can be effectively reduced, meanwhile, the air gap is few in preparation steps, the process is simple, cost can be well reduced, and yield can be well improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor memory and an electronic device.
Background
Main characteristics of a DRAM (Dynamic Random Access Memory) include capacitance characteristics of a linear functional portion such as a bit line and a metal line, which are closely related to a Data Sensing Margin (Data Sensing Margin). Although the size of DRAMs is continuously reduced, the sensing margin must be kept as high as possible in the previous generation, and for this reason, the capacitance characteristics of the linear functional portion must be further reduced. The main factors determining the capacitance characteristics of the linear functional portions are the thickness and permittivity of the sidewalls of the linear functional portions. The sidewall of the linear functional portion in the prior art generally adopts a three-layer structure, such as a SiN/oxide/SiN three-layer structure, but the parasitic capacitance of the existing sidewall is still high, and therefore, an Air Gap (Air Gap) needs to be manufactured on the sidewall to further reduce the parasitic capacitance, however, the manufacturing process of the Air Gap at present has many steps and is difficult.
Disclosure of Invention
The present disclosure provides a semiconductor structure, a method of manufacturing the same, a semiconductor memory and an electronic device.
A first aspect of the present disclosure provides a semiconductor structure comprising:
a semiconductor substrate;
a plurality of linear functional portions on the semiconductor substrate;
air gaps respectively positioned at the outer sides of the two side walls of the linear functional part;
wherein, the air gap comprises vertical part and horizontal part, constitutes "L" type vertical cross sectional shape.
A second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, including:
providing a semiconductor substrate, and forming a plurality of linear functional parts on the semiconductor substrate;
forming a sacrificial core mold at the lower part between the side walls of the adjacent linear functional parts, and forming an upper side wall at the upper part; the sacrificial core mold comprises two vertical parts and a horizontal part, the vertical parts are respectively positioned outside the side walls of the adjacent linear functional parts, and the horizontal part connects the bottoms of the two vertical parts; the upper side wall is positioned outside the side wall above the vertical part;
forming a first outer side wall on the outer sides of the upper side wall and the vertical part;
removing the sacrificial mandrel to form an air gap space;
and depositing and forming a second outer side wall on the whole semiconductor structure to seal the air gap space, thereby forming the air gap.
A third aspect of the present disclosure provides an electronic device comprising the semiconductor structure described above.
This disclosure compares advantage with prior art and lies in:
the air gap is arranged outside the side wall of the linear functional component in the semiconductor structure, so that parasitic capacitance can be effectively reduced, meanwhile, the air gap is few in preparation steps, the process is simple, cost can be well reduced, and yield can be well improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIGS. 1a-1j are schematic diagrams of a method of fabricating a line feature as a bitline structure according to the present disclosure;
fig. 2 a-2 b are schematic structural diagrams of products in which the line-shaped functional component is an aluminum metal line structure according to the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In order to solve the above-mentioned problems in the prior art, an embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof, a semiconductor memory and an electronic device, which are described below with reference to the accompanying drawings.
Referring to fig. 1j, fig. 1j shows a schematic cross-sectional view of a semiconductor according to the present disclosure. As shown in fig. 1j, the semiconductor structure may be, for example, a DRAM (Dynamic Random Access Memory), and may include: the semiconductor device includes a semiconductor substrate, and a plurality of line-shaped functional parts on the semiconductor substrate. In the present embodiment, the Line-shaped functional component may be a Bit Line structure 100(Bit Line), and the Bit Line structure 100 may include a polysilicon layer 110, a metal tungsten layer 120 on the polysilicon layer 110, and a silicon nitride layer 130 on the metal tungsten layer 120, and may further include sidewalls 140 on both sides of the Bit Line structure, where the sidewalls 140 may be, for example, silicon nitride layers. On the outside of the sidewalls 140, there may be included an upper sidewall 200 on the upper portion and an air gap 300 on the lower portion. Wherein the air gap 300 may be composed of a vertical portion 310 and a horizontal portion 320, as shown in fig. 1j, the vertical portion 310 and the horizontal portion 320 form an "L" shape in vertical section, and the vertical portion 310 is located outside the sidewall 140 of the linear functional portion. The upper sidewall 200 may be located above the vertical portion 310 of the air gap 300 and attached to the outside of the sidewall 140 of the linear functional portion, and the material of the upper sidewall 200 may be, for example, oxide. An outer sidewall 400 may be further included to be positioned outside the air gap 300 and the upper sidewall 200, wherein an inner side of the outer sidewall 400 defines an inner profile of the air gap 300 and the upper sidewall 200 (i.e., an inner side of the outer sidewall 400 is conformal with an outer side of the air gap 300 and the upper sidewall 200) to seal the air gap 300. The outer side walls may include a first outer side wall 410 and a second outer side wall 420. The first outer sidewalls 410 are positioned outside the upper sidewall 200 and the vertical portion 310 of the air gap 300. The second outer sidewall 420 includes a vertical portion 421 and a horizontal portion 422, wherein the vertical portion 421 is located outside the first outer sidewall 410 and the horizontal portion 320 of the air gap 300, one end of the horizontal portion 422 is connected to the vertical portion 421, and the other end is connected to the horizontal portion 422 of the second outer sidewall 420 of the adjacent bit line structure. The first outer sidewall 410 and the second outer sidewall 420 may be, for example, silicon nitride layers.
Next, the method of manufacturing the semiconductor structure in the present embodiment is described in detail with reference to fig. 1a to 1 j:
as shown in fig. 1a, first, a semiconductor substrate may be provided, and a plurality of bit line structures 100 are formed on the semiconductor substrate, where the formation of the bit line structures 100 may be sequentially depositing a polysilicon layer 110, a metal tungsten layer 120 on the polysilicon layer 110, and a silicon nitride layer 130 on the metal tungsten layer 120, and then, sidewalls 140 at two sides of the bit line structures may be formed by a sidewall process, where the sidewalls 140 may be, for example, silicon nitride layers.
Subsequently, as shown in fig. 1b, a Spin-on process may be used to fill a sacrificial mold layer 340 between the sidewalls 140 of the adjacent bit line structures, wherein the sacrificial mold layer 340 may be a Spin-on hard mask composition (SOH), Spin-on Carbon (SOC), or Spin-on SiGe. In other embodiments of the present invention, the SiGe may also be formed by epitaxy or other conventional deposition processes. In the disclosure, the above materials and spin coating process are used to replace the common oxide material and deposition process to prepare the air-gap sacrificial mold Layer (which may also be referred to as air-gap core mold Layer, Mandrel Layer); it is known that when an oxide material is used as the sacrificial mold layer, a wet etching process is required to remove the sacrificial core mold to obtain an air gap, which results in an increase of process steps and equipment, and high manufacturing difficulty, whereas the sacrificial mold layer formed by SOH and other materials in the present disclosure and the sacrificial core mold obtained from the sacrificial mold layer can be easily removed by using a common Ashing and Strip (Ashing and Strip) process in the same etching chamber, thereby reducing the process steps and equipment and reducing the manufacturing difficulty.
Subsequently, as shown in fig. 1c, the sacrificial mold layer 340 may be etched back to the height of the air gap to be finally obtained, for example, a conventional Ashing and Strip (Ashing and Strip) process may be selected for etching back.
Subsequently, as shown in fig. 1d, a top sidewall layer 210 may be deposited over the entire semiconductor structure, the deposition process employing an atomic layer deposition process (ALD), and the top sidewall layer 210 may be, for example, an oxide.
Subsequently, as shown in fig. 1e, the bottom of the upper sidewall layer 210 may be etched away to form the upper sidewall spacers 200.
Subsequently, as shown in fig. 1f, the sacrificial pattern layer 340 may be etched down along the dimension defined by the upper sidewall 200, using the upper sidewall 200 as a mask, to form a sacrificial mandrel 350, wherein the etching may be performed by a conventional Ashing and Strip (Ashing and Strip) process; the etched sacrificial mandrel 350 may include two vertical portions 351 and a horizontal portion 352, wherein the vertical portions 351 are respectively located outside the sidewalls 140 of the adjacent bitline structures, the horizontal portion 352 connects the bottoms of the two vertical portions 351, and the upper sidewall 200 may be located outside the sidewalls 140 above the vertical portions 351.
Subsequently, as shown in fig. 1g, a first outside wall layer 411 may be deposited on the entire semiconductor structure, the first outside wall layer 411 may be, for example, silicon nitride.
Subsequently, as shown in fig. 1h, the bottom of the first outer sidewall layer 411 may be etched away to form a first outer sidewall 410, the first outer sidewall 410 being located outside the upper sidewall 200 and the vertical portion 351 of the sacrificial mandrel 350.
Subsequently, as shown in fig. 1i, the sacrificial mandrel 350 may be removed, thereby forming an air gap space 300' below the upper sidewall, and the sacrificial mandrel 350 may be removed, particularly, using a conventional Ashing and Strip (Ashing and Strip) process. As described above, since the sacrificial mold layer in the present disclosure uses spin-coating materials such as SOH, a common ashing process can be used without using wet etching processes and apparatuses when removing the sacrificial core mold 350, and the process can be performed in the same process chamber, thereby greatly saving process steps and apparatuses, and reducing production cost and manufacturing difficulty.
Subsequently, as shown in fig. 1j, a second outer sidewall 420 may be deposited on the entire semiconductor structure to seal the air gap 300', and the second outer sidewall 420 may be, for example, silicon nitride. The second outer sidewall 420 may include a vertical portion 421 and a horizontal portion 422, wherein the vertical portion 421 is located outside the first outer sidewall 410 and the horizontal portion 320 of the air gap 300, one end of the horizontal portion 422 is connected to the vertical portion 421, and the other end of the horizontal portion 422 is connected to the horizontal portion 422 of the second outer sidewall 420 of the adjacent bit line structure.
The semiconductor structure of another embodiment of the present disclosure may also be, for example, a DRAM, and the Line functional component may be an aluminum Metal Line (Al Metal Line), as shown in fig. 2a, which is only to replace the bit Line structure 100 in the first embodiment with an aluminum Metal Line structure 100 ', wherein the aluminum Metal Line structure 100 ' may be prepared by depositing an aluminum Metal layer 110 ', a titanium nitride layer 120 ' on the aluminum Metal layer 110 ', and a silicon nitride layer on the outermost side of the aluminum Metal Line structure in sequence, and sidewalls 130 ' of the aluminum Metal Line structure 100 ' are formed on both sides of the silicon nitride layer. Except for the aluminum metal line structure 100', the air gap structure and the manufacturing method of the present embodiment are the same as those of the bit line structure, and are not repeated and illustrated herein, and the air gap of the aluminum metal line structure finally prepared is shown in fig. 2b, where the same reference numerals are the same as those in the first embodiment.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to fall within the scope of the present disclosure.
Claims (15)
1. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of linear functional portions on the semiconductor substrate;
air gaps respectively positioned at the outer sides of the two side walls of the linear functional part;
wherein, the air gap comprises vertical part and horizontal part, constitutes "L" type vertical cross sectional shape.
2. The semiconductor structure of claim 1, wherein:
the sidewall includes an outermost silicon nitride layer.
3. The semiconductor structure of claim 1, wherein:
the air gap structure further comprises an upper side wall located above the air gap vertical portion.
4. The semiconductor structure of claim 3, wherein:
the upper side wall is made of oxide.
5. The semiconductor structure of claim 1, wherein:
the air gap structure further comprises an outer side wall positioned outside the air gap, and the inner side surface of the outer side wall defines the outer side surface of the air gap.
6. The semiconductor structure of claim 5, wherein:
the outer side walls comprise a first outer side wall and a second outer side wall;
the first outer side wall is positioned outside the vertical part of the air gap;
the second outer side wall comprises a vertical part and a horizontal part, wherein the vertical part is positioned on the outer side of the first outer side wall and the horizontal part of the air gap, one end of the horizontal part is connected with the vertical part into a whole, and the other end of the horizontal part is connected with the horizontal part of the second outer side wall of the adjacent bit line structure into a whole.
7. The semiconductor structure of claim 5, wherein:
the outer side wall is made of silicon nitride.
8. The semiconductor structure of any of claims 1-7, wherein:
the linear functional part is a bit line structure or a metal line structure.
9. The semiconductor structure of claim 8, wherein:
the semiconductor structure is a dynamic random access memory.
10. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, and forming a plurality of linear functional parts on the semiconductor substrate;
forming a sacrificial core mold at the lower part between the side walls of the adjacent linear functional parts, and forming an upper side wall at the upper part; the sacrificial core mold comprises two vertical parts and a horizontal part, the vertical parts are respectively positioned outside the side walls of the adjacent linear functional parts, and the horizontal part connects the bottoms of the two vertical parts; the upper side wall is positioned outside the side wall above the vertical part;
forming a first outer side wall on the outer sides of the upper side wall and the vertical part;
removing the sacrificial mandrel to form an air gap space;
and depositing and forming a second outer side wall on the whole semiconductor structure to seal the air gap space, thereby forming the air gap.
11. The method of manufacturing according to claim 10, wherein:
the lower part between the side walls of the adjacent linear functional parts is formed with a sacrificial core mould, the upper part is formed with an upper side wall, comprising,
filling a sacrificial mold layer between the side walls of the adjacent linear functional parts;
etching the sacrificial mold layer back to the height of the air gap;
depositing a top sidewall layer over the entire semiconductor structure;
etching and removing the bottom of the upper side wall layer to form an upper side wall;
the sacrificial mold layer is etched down to form a sacrificial mandrel.
12. The method of manufacturing according to claim 11, wherein:
the sacrificial mold layer is filled by adopting a spin coating or deposition process;
the sacrificial film layer is spin-on hard mask composition, spin-on carbon, spin-on SiGe or deposition formed SiGe.
13. The method of manufacturing according to claim 11, wherein:
and depositing an upper side wall layer on the whole semiconductor structure by adopting an atomic layer deposition process.
14. The method of manufacturing according to any one of claims 10 to 13, wherein:
and removing the sacrificial core mold by adopting an ashing stripping process.
15. The method of manufacturing according to any one of claims 10 to 13, wherein:
the linear functional part is a bit line structure or a metal line structure.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022179041A1 (en) * | 2021-02-25 | 2022-09-01 | 长鑫存储技术有限公司 | Semiconductor structure and method for forming same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103903994A (en) * | 2012-12-26 | 2014-07-02 | 爱思开海力士有限公司 | Semiconductor device including air gaps and method of fabricating the same |
| KR20150012033A (en) * | 2013-07-24 | 2015-02-03 | 에스케이하이닉스 주식회사 | Semiconductor device with air gap and method for manufacturing the same |
| US20200105867A1 (en) * | 2018-09-27 | 2020-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-Aligned Contact Air Gap Formation |
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2020
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103903994A (en) * | 2012-12-26 | 2014-07-02 | 爱思开海力士有限公司 | Semiconductor device including air gaps and method of fabricating the same |
| KR20150012033A (en) * | 2013-07-24 | 2015-02-03 | 에스케이하이닉스 주식회사 | Semiconductor device with air gap and method for manufacturing the same |
| US20200105867A1 (en) * | 2018-09-27 | 2020-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-Aligned Contact Air Gap Formation |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022179041A1 (en) * | 2021-02-25 | 2022-09-01 | 长鑫存储技术有限公司 | Semiconductor structure and method for forming same |
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