CN117013365A - Semiconductor optical amplifier and manufacturing method thereof - Google Patents

Semiconductor optical amplifier and manufacturing method thereof Download PDF

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Publication number
CN117013365A
CN117013365A CN202310828044.2A CN202310828044A CN117013365A CN 117013365 A CN117013365 A CN 117013365A CN 202310828044 A CN202310828044 A CN 202310828044A CN 117013365 A CN117013365 A CN 117013365A
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China
Prior art keywords
region
mesa
optical amplifier
semiconductor
light
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CN202310828044.2A
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Chinese (zh)
Inventor
单静春
李吴皓
李中坤
王定理
赵建宜
牛玉秀
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Accelink Technologies Co Ltd
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Accelink Technologies Co Ltd
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Priority to CN202310828044.2A priority Critical patent/CN117013365A/en
Publication of CN117013365A publication Critical patent/CN117013365A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2004—Confining in the direction perpendicular to the layer structure
    • H01S5/2009—Confining in the direction perpendicular to the layer structure by using electron barrier layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/024—Arrangements for thermal management
    • H01S5/02469—Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/50—Amplifier structures not provided for in groups H01S5/02 - H01S5/30
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The application relates to the technical field of communication, and provides a semiconductor optical amplifier and a manufacturing method thereof. The semiconductor amplifier comprises a substrate and a mesa structure formed by etching an epitaxial structure grown on the substrate; the mesa structure is divided into at least one matt region and at least one light emitting region; a current conducting structure is grown above the table top of the light emitting area and used for conducting current to reach the table top structure; a first current blocking structure is grown above the no light region for blocking current of the upper layer from reaching the mesa structure. The application increases the maximum power threshold of the output, thereby realizing the increase of the service life. And the whole heating of the chip is reduced through no light emission in the no light area, the heat transfer path is increased, the heat transfer effect is improved, and the reliability of the chip is further improved.

Description

Semiconductor optical amplifier and manufacturing method thereof
Technical Field
The application relates to the technical field of communication, in particular to a semiconductor optical amplifier and a manufacturing method thereof.
Background
The semiconductor optical amplifier (SOA, semiconductor optical amplifier) has the characteristics of multiple functions, small volume, low power consumption, convenience for monolithic integration with other semiconductor devices and the like, has unique and important functions in optical signal amplification and optical signal processing and optical switching applications, and is one of the important devices of an optical fiber communication network.
Reliability is well known as an important indicator of the quality of semiconductor chips. Reliability is the probability that a product will perform a given function within a given time under given conditions. With the development of science and technology, semiconductor chips have been widely used in the sophisticated fields of national defense and science and technology. The requirements for stability and reliability of the semiconductor chip are becoming more and more stringent. In the actual production and development process, the reliability level of the chip is generally required to be evaluated through a life test, and the reliability level of the chip is improved through quality feedback so as to ensure the quality of the chip. The lower the failure rate of the chip during the life test, the more reliable the chip can be demonstrated. Therefore, how to reduce the failure rate of the chip during the lifetime experiment becomes one of the important contents of the study. The failure rate of a chip can typically be reduced by both chip design and manufacturing aspects. In order to ensure that the aim is achieved, corresponding measures are adopted from the aspects of raw materials, chip design, equipment, process optimization design, environment and the like in general from the main links involved in chip production. But can be global, critical or chip design.
In the prior art, when the chip emits light, the internal temperature of the chip can rise, and when the internal and ambient temperatures of the chip are too high, the failure rate of the chip can be greatly increased, thereby reducing the reliability and the service life of the chip.
In the prior art, the SOA mostly adopts a buried heterojunction structure, and because the thickness of the active layer (about 0.15 μm) is smaller than the width (about 2 μm), the vertical divergence angle of the far field perpendicular to the junction plane direction is usually larger than the horizontal divergence angle of the far field perpendicular to the junction plane direction, and the light of the SOA is an elliptical light spot. However, the mode field of the single-mode fiber accords with Bessel function distribution and is a circular symmetrical light spot. The two are seriously mismatched in the mode field, so that the coupling efficiency is low, and the coupling efficiency directly influences the characteristics of high gain, low noise figure and the like required to be obtained by the optical signal. In order to efficiently couple input and output light into a single mode fiber having a core diameter of only 8-9 μm and being circularly symmetric, mode field matching between the single mode fiber and the SOA is particularly important.
In view of this, overcoming the drawbacks of the prior art is a problem to be solved in the art.
Disclosure of Invention
The application aims to solve the technical problems that the internal temperature of a chip is high in the prior art, and the reliability and the service life of the chip are affected.
The application adopts the following technical scheme:
in a first aspect, the present application provides a semiconductor optical amplifier comprising a substrate 1 and a mesa structure 21 etched from an epitaxial structure 2 grown on the substrate 1;
the mesa structure 21 is divided into at least one matt region 210 and at least one light emitting region 211;
a current conducting structure 3 is grown above the mesa of the light emitting region 211 for conducting current to the mesa structure 21;
a first current blocking structure 4 is grown over the matt region 210 for blocking the upper layer of current from reaching the mesa structure 21.
Preferably, the first current blocking structure 4 includes a first semiconductor layer 41 and a second semiconductor layer 42 grown on the first semiconductor layer 41; the first semiconductor layer 41 is made of a P-type material, and the second semiconductor layer 42 is made of an N-type material.
Preferably, the current conducting structure 3 comprises one or more semiconductor layers, and the doping types of the one or more semiconductor layers are the same.
Preferably, portions of the mesa structure 21 near both ends of the optical amplifier are divided into non-light areas 210, and portions of the mesa structure 21 near the center of the optical amplifier are divided into light emitting areas 211.
Preferably, the portion of the mesa structure 21 near both ends of the optical amplifier is divided into a first region 212 and the portion of the mesa structure 21 near the middle of the optical amplifier is divided into a second region 213 based on the distance from both ends of the optical amplifier;
the difference between the mesa width of the mesa structure 21 in the first region 212 and the mesa width in the second region 213 is greater than a first preset difference;
and at the connection position of the first region 212 and the second region 213, the mesa width of the mesa structure 21 is sequentially increased or decreased, so as to achieve smooth connection of the first region 212 and the second region 213 of the mesa structure 21.
The second current blocking structure 5 is further grown on both sides of the light emitting region 211, for blocking the current of the upper layer from reaching both sides of the mesa structure 21. The second current blocking structure 5 is obtained by etching away a part of the first current blocking structure 4 above the mesa of the light emitting region 211 after the first current blocking structure 4 is grown above the light emitting region 211.
Preferably, the epitaxial structure 2 includes at least one of a buffer layer 22, a lower cladding layer 23, an active layer 24, and a first upper cladding layer 25.
In a second aspect, the present application also provides a method for fabricating a semiconductor optical amplifier, growing an epitaxial structure 2 on a substrate 1, comprising:
growing a protective film 6 with a preset pattern on the epitaxial structure 2, and etching the surface of the epitaxial structure 2 with the protective film 6 to obtain a mesa structure 21 covered with the protective film 6;
and etching the protective film 6 in the no-light region 210, growing a plurality of semiconductor layers on the surface of the mesa structure 21, etching the protective film 6 in the light-emitting region 211 after the corresponding semiconductor layers are grown, and performing the growth of the subsequent semiconductor layers to obtain the current conducting structure 3 of the no-light region 210 and the first current blocking structure 4 of the light-emitting region 211.
Preferably, the step of growing a plurality of semiconductor layers on the surface of the mesa structure 21, etching the protective film 6 in the light emitting region 211 after the corresponding semiconductor layers are grown, and performing the subsequent growth of the semiconductor layers specifically includes:
and growing a first semiconductor layer 41 and a second semiconductor layer 42 on the surface of the mesa structure 21, etching the protective film 6 in the light-emitting region 211 after growing the second semiconductor layer 42, and continuing to grow a third semiconductor layer 43 to obtain the first current blocking structure 4 in the no light region 210 and the current conducting structure 3 in the light-emitting region 211.
Preferably, a second difference between the mesa width of the preset pattern in the first region 212 and the mesa width in the second region 213 is greater than a preset difference;
and at the connection position between the first area 212 and the second area 213, the mesa width of the preset pattern is sequentially increased or decreased.
According to the application, the non-light area and the light-emitting area are arranged, and the non-light area is provided with the current blocking structure, so that the area does not emit light and is only used as a transmission channel of the optical waveguide. When light passes through the area, the optical mode field of the light expands, the optical power density of the cavity surface is reduced, the critical power for optical catastrophe is increased, the maximum power threshold which can be output by the device is increased, and thus the service life is prolonged. And the whole heating of the chip is reduced through the non-luminescence of the partial area, the heat transfer path is increased, the heat transfer effect is improved, and the reliability of the chip is further improved.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view in partial perspective of a semiconductor optical amplifier according to an embodiment of the present application;
FIG. 2 is a schematic side view of an epitaxial structure in a semiconductor optical amplifier according to an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a non-light area in a semiconductor optical amplifier according to an embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of a light-emitting region in a semiconductor optical amplifier according to an embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a light-emitting region in yet another semiconductor optical amplifier provided in accordance with an embodiment of the present application;
FIG. 6 is a schematic cross-sectional view of a non-light area in yet another semiconductor optical amplifier provided by an embodiment of the present application;
FIG. 7 is a schematic top view of a mesa structure in a semiconductor optical amplifier according to an embodiment of the present application;
FIG. 8 is a schematic top view of a mesa structure in yet another semiconductor optical amplifier provided by an embodiment of the present application;
FIG. 9 is a schematic top view of a mesa structure in yet another semiconductor optical amplifier provided in accordance with an embodiment of the present application;
fig. 10 is a schematic structural diagram of a method for manufacturing a semiconductor optical amplifier according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of a method for manufacturing a semiconductor optical amplifier according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of a method for manufacturing a semiconductor optical amplifier according to another embodiment of the present application;
FIG. 13 is a schematic cross-sectional view of a non-light area in yet another semiconductor optical amplifier provided by an embodiment of the present application;
FIG. 14 is a schematic cross-sectional view of a light-emitting region in yet another semiconductor optical amplifier provided in accordance with an embodiment of the present application;
fig. 15 is a schematic view in partial perspective of yet another semiconductor optical amplifier provided in accordance with an embodiment of the present application.
The same reference numbers are used throughout the drawings to reference like elements or structures, wherein:
1. a substrate; 2. an epitaxial structure; 21. a mesa structure; 210. a matt region; 211. a light emitting region; 212. a first region; 213. a second region; 22. a buffer layer; 23. a lower cladding layer; 24. an active layer; 25. a first upper cladding layer; 3. a current conducting structure; 4. a first current blocking structure; 41. a first semiconductor layer; 42. a second semiconductor layer; 43. a third semiconductor layer; 5. a second current blocking structure; 6. a protective film.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the description of the present application, the terms "inner", "outer", "longitudinal", "transverse", "upper", "lower", "top", "bottom", etc. refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of describing the present application and do not require that the present application must be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
The terms "first," "second," and the like herein are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In addition, the technical features of the embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Example 1:
in order to solve the problem that the internal temperature of the chip is high and the reliability and the service life of the chip are affected in the prior art, the embodiment 1 of the application provides a semiconductor optical amplifier, as shown in fig. 1 and 2, which comprises a substrate 1 and a mesa structure 21 formed by etching an epitaxial structure 2 grown on the substrate 1; the mesa structure 21 forms a waveguide of the semiconductor optical amplifier.
The mesa structure 21 is divided into at least one matt region 210 and at least one light emitting region 211; a current conducting structure 3 is grown above the mesa of the light emitting region 211 for conducting current to the mesa structure 21; a first current blocking structure 4 is grown over the matt region 210 for blocking the upper layer of current from reaching the mesa structure 21. The mesa structure 21 may be divided into a mesa and a side surface in terms of structure, the current conducting structure 4 is grown over the mesa, and the first current blocking structure 4 is grown over the mesa and the side surface, covering the no light region 210.
It should be noted that, the epitaxial structure 2 shown in fig. 2 may be understood as a schematic structural diagram during the process of manufacturing the mesa structure 21, and the mesa structure 21 shown in fig. 1 is formed after the structure shown in fig. 2 is subjected to the corresponding etching operation, and after the etching is completed, the mesa structure 21 is consistent with the epitaxial structure 2, and in the following embodiment 2, the epitaxial structure 2 is also used as an alternative expression of the mesa structure 21. As shown in fig. 2, the epitaxial structure 2 includes at least one of a buffer layer 22, a lower cladding layer 23, an active layer 24, and a first upper cladding layer 25.
Fig. 1 is to be understood as a schematic view of a portion of a semiconductor optical amplifier, in which the mesa 21 is visible in each section of the semiconductor optical amplifier, fig. 1 only selects two sections of the no light region 210 and one section of the light emitting region 211 to present the mesa 21, a schematic view of a section of a corresponding semiconductor optical amplifier in the no light region 210 is shown in fig. 3, and a schematic view of a section of a corresponding semiconductor optical amplifier in the light emitting region 211 is shown in fig. 4.
The current conducting structure 3 may be directly grown over the mesa structure 21, or the current conducting structure 3 may be grown after the mesa structure 21 grows other semiconductor layers. In a preferred embodiment, as shown in fig. 5, a second current blocking structure 5 is further grown on both sides of the light emitting region 211, for blocking the current of the upper layer from reaching both sides of the mesa structure 21. Allowing current to travel downward from directly above the mesa structure 21, but not from both sides of the mesa structure 21. The second current blocking structure 5 is obtained by etching away a part of the first current blocking structure 4 above the mesa of the light emitting region 211 after growing the first current blocking structure 4 above the light emitting region 211.
In an actual application scenario, the material of the substrate 1 is InP, and the epitaxial structure 2 sequentially includes: an InP buffer layer 22 of N-type material, an InP lower cladding layer 23 of N-type material, an active layer 24 of InGaAsP material, and an InP first upper cladding layer 25 of P-type material. The active layer 24 may be a buried heterojunction structure or a ridge waveguide structure, and the buried heterojunction structure may be a planar active layer 24 buried heterostructure, such as a etched mesa buried structure, a double-trench planar buried structure, a stripe buried heterostructure, or the like, or a non-planar active layer 24 buried heterostructure, such as a V-groove substrate 1 or a channel substrate 1 buried structure, a mesa substrate 1 buried heterostructure, a buried crescent structure, or the like. The epitaxial structure 2 may be obtained by one or more MOCVD (metal organic chemical vapor deposition, metal organic vapor deposition) techniques.
In this embodiment, by providing the no light area 210 and the light emitting area 211, the no light area 210 is provided with the first current blocking structure 4, so that the area does not emit light, and only serves as a transmission channel of the optical waveguide. When light passes through the area, the optical mode field of the light expands, the optical power density of the cavity surface is reduced, the critical power for optical catastrophe is increased, the maximum power threshold which can be output by the device is increased, and thus the service life is prolonged. And the whole heating of the chip is reduced through the non-luminescence of the partial area, the heat transfer path is increased, the heat transfer effect is improved, and the reliability of the chip is further improved.
In a practical application scenario, the probability of optical catastrophe is larger near the two ends of the optical amplifier, and the probability of optical catastrophe is smaller near the center of the optical amplifier, so in a preferred embodiment, as shown in fig. 1, the portion of the mesa structure 21 near the two ends of the optical amplifier is divided into no light regions 210, and the portion of the mesa structure 21 near the center of the optical amplifier is divided into light emitting regions 211. To reduce heating of the chips across the amplifier and thereby further reduce the likelihood of optical catastrophe occurring. In alternative embodiments, the length of the matt region 210 may be 20 to 100 μm and the length of the light emitting region 211 may be 300 to 1300 μm.
The first current blocking structure 4 may be a plurality of the first semiconductor layers 41 and a plurality of the second semiconductor layers 42 which are alternately stacked, and the first semiconductor layers 41 and the second semiconductor layers 42 may be different in doping type. As shown in fig. 6, there is also an embodiment that: the first current blocking structure 4 includes a first semiconductor layer 41 and a second semiconductor layer 42 grown on the first semiconductor layer 41; the first semiconductor layer 41 is made of a P-type material, and the second semiconductor layer 42 is made of an N-type material. When current reaches the second semiconductor layer 42, the second semiconductor layer 42 is made of an N-type material, the first semiconductor layer 41 of the lower layer is made of a P-type material, so that a PN junction is formed, and due to unidirectional conduction of the PN junction, current cannot be transmitted from the N-type material of the upper layer to the P-type material of the lower layer, so that the current blocking effect is achieved, and no light is emitted from the light-emitting region 210.
The current conducting structure 3 includes one or more semiconductor layers, where the doping types of the one or more semiconductor layers are the same, i.e., the semiconductor layers may be all N-type materials or all P-type materials, or the semiconductor layer grown below is N-type materials, and the semiconductor layer grown above is P-type materials. Thereby forming a PN junction with unidirectional conduction, allowing current to be transmitted from the P-type material on the upper layer to the N-type material on the lower layer, and realizing current conduction. After the first current blocking structure 4 is grown, the top region of the mesa structure 21 is etched away, so that the second current blocking structures 5 located at two sides of the light emitting region 211 can be formed, and the current conducting structure 3 is grown again, thereby obtaining the complete semiconductor optical amplifier grown with the first current blocking structure 4, the second current blocking structure 5 and the current conducting structure. In this implementation, the second current blocking structure 5 includes a first semiconductor layer 41 and a second semiconductor layer 42 grown on the first semiconductor layer 41, as shown in fig. 14.
Whereas in actual use situations, current reaching the mesa structure 21 mainly means that current reaches the active layer 24 in the mesa structure 21, in an alternative embodiment a first upper cladding layer 25 of P-type material is grown over the active layer 24, in this embodiment the current conducting structure 3 comprises one or more semiconductor layers of P-type material, and the first current blocking structure 4 may comprise only one semiconductor layer of N-type material, acting together with the first upper cladding layer 25 to block current reaching the active layer 24.
The present embodiment also provides a preferred embodiment, as shown in fig. 7, 8 or 9, including: the portion of the mesa structure 21 near both ends of the optical amplifier is divided into a first region 212 and the portion of the mesa structure 21 near the middle of the optical amplifier is divided into a second region 213 based on the distance from both ends of the optical amplifier.
The difference between the mesa width of the mesa structure 21 in the first region 212 and the mesa width in the second region 213 is greater than a first preset difference; wherein the first preset difference is analyzed by a person skilled in the art according to the gain requirement and the noise requirement of the optical amplifier.
And at the connection position of the first region 212 and the second region 213, the mesa width of the mesa structure 21 is sequentially increased or decreased, so as to achieve smooth connection of the first region 212 and the second region 213 of the mesa structure 21.
In a practical application scenario, there are three implementations as shown in fig. 7, 8 and 9. When the mesa structure 21 shown in fig. 7 is used, the waveguide width near both ends of the optical amplifier becomes gradually large, and at this time, the light distribution thereof can be well confined in the active layer 24, the light field distribution thereof becomes large, the spot size becomes large, and the far field divergence angle thereof becomes small. When the mesa structure 21 shown in fig. 8 is used, the width of the waveguide near both ends of the optical amplifier becomes gradually smaller, and a part of the optical field penetrates into the outer cladding layer, so that the size of the near-field output light spot of the SOA becomes larger, and the far-field divergence angle becomes smaller, and the size of the optical spot approaches to the size of the mode spot in the optical fiber, so that the size of the light spot becomes larger, the far-field divergence angle is reduced, and the coupling efficiency of the SOA chip and the optical fiber is improved, and the chip has higher gain and lower noise index.
It should be noted that the division of the light emitting region 211 and the matt region 210 may be the same as the division of the first region 212 and the second region 213, for example, the first region 212 may be the matt region 210, the second region 213 may be the light emitting region 211, or different divisions may be used, which is not limited in the present application.
When the first region 212 is taken as the no light region 210 and the second region 213 is taken as the light emitting region 211, the semiconductor amplifier generated in the actual scene includes: sequentially epitaxially growing a multilayer epitaxial structure 2 on a semiconductor InP substrate 1, wherein the multilayer epitaxial structure sequentially comprises an N-type InP buffer layer 222, an N-type InP lower cladding layer 233, an InGaAsP active layer 244 and a P-type InP first upper cladding layer 25; etching the epitaxial structure 2 to obtain a mesa structure 21 as shown in fig. 1, wherein the length of the first region 212 is 20-100 μm, and the length of the second region 213 is 300-1300 μm; the width of the mesa structure 21 in the first region 212 is 0.5 to 2 μm or 2 to 4 μm, and the width of the mesa structure 21 in the second region 213 is 1 to 3 μm; in the first region 212, a P-type P-InP first barrier layer, an N-type N-InP second barrier layer, a P-type P-InP second upper cladding layer, and a P-type highly doped P-InGaAs ohmic contact layer are sequentially grown over the mesa structure 21; in the second region 213, a P-type P-InP second upper cladding layer and a P-type highly doped P-InGaAs ohmic contact layer are sequentially grown over the mesa structure 21.
It should be noted that, in this embodiment and the following embodiments, each of the dashed lines represents a corresponding structure in perspective view in fig. 1 and 15, and each of the dashed lines does not represent an actually existing structure in other drawings, but is used to mark a corresponding region division, as in fig. 7, 8 and 9, each of the dashed lines is used to represent the division of the first region 212 and the second region 213.
The matt region 210, the light emitting region 211, the first region 212 and the second region 213 do not represent the division of the mesa structure 21 into 4 regions, but the entire mesa structure 21 is divided into the matt region 210 and the light emitting region 211 according to one division criterion, and the entire mesa structure 21 is divided into the first region 212 and the second region 213 according to another division criterion, both of which are directed to the entire mesa structure.
Example 2:
the present application provides a method for manufacturing a semiconductor optical amplifier, which can be used for manufacturing the semiconductor optical amplifier described in embodiment 1, and it should be noted that the key points of the present application are that the method processes related to the substantial distinguishing features are produced, and other processes like manufacturing electrodes are not described in the following description of the present application because they do not belong to the improvement scope of the present application and also belong to the conventional prior art means. The method for manufacturing a semiconductor optical amplifier according to this embodiment includes growing an epitaxial structure 2 on a substrate 1, as shown in fig. 10, including:
in step 201, a protective film 6 with a preset pattern is grown on the epitaxial structure 2 to obtain a structure as shown in fig. 11, and etching is performed on the surface of the epitaxial structure 2 on which the protective film 6 is grown to obtain a mesa structure 21 covered with the protective film 6; a structure as shown in fig. 12 is obtained. The protective film 6 may be SiO X A film, wherein X is obtained by empirical analysis by a person skilled in the art, and typically X is 2, and the protective film 6 is SiO 2 And (3) a film.
In step 202, the protective film 6 in the no light area 210 is etched, a plurality of semiconductor layers are grown on the surface of the mesa structure 21, and after the corresponding semiconductor layers are grown, the protective film 6 in the light emitting area 211 is etched, and the subsequent semiconductor layer growth is performed, so as to obtain the current conducting structure 3 of the no light area 210 and the first current blocking structure 4 of the light emitting area 211. When the protective film 6 in the light-emitting region 211 is etched away, the semiconductor layer that has grown in the light-emitting region 211 is also etched away together with the protective film 6. Meanwhile, since the etched protection film 6 covers only the top region of the mesa structure, both sides of the mesa structure 21 are not covered, and thus the second current blocking structure 5 is generated at both sides of the mesa structure 21. So that current is transmitted downward from directly above the mesa structure 21, but not from both sides of the mesa structure 21.
Wherein, the step of growing a plurality of semiconductor layers on the surface of the mesa structure 21, and etching the protective film 6 in the light emitting region 211 after the corresponding semiconductor layers are grown, and performing the subsequent growth of the semiconductor layers specifically includes:
and growing a first semiconductor layer 41 and a second semiconductor layer 42 on the surface of the mesa structure 21, etching the protective film 6 in the light-emitting region 211 after growing the second semiconductor layer 42, and continuing to grow a third semiconductor layer 43 to obtain the first current blocking structure 4 in the no light region 210 and the current conducting structure 3 in the light-emitting region 211. The matt region 210 is shown in fig. 13, and the light emitting region 211 is shown in fig. 14.
The first semiconductor layer 41 is made of P-type material, the second semiconductor layer 42 is made of N-type material, the first semiconductor layer 41 and the second semiconductor layer 42 form the first current blocking structure 4, and the third semiconductor layer 43 is made of P-type material, so as to form the current conducting structure 3.
In a preferred embodiment, the difference between the mesa width of the preset pattern in the first region 212 and the mesa width in the second region 213 is greater than a second preset difference;
and at the connection position between the first area 212 and the second area 213, the mesa width of the preset pattern is sequentially increased or decreased. The second preset difference is analyzed by a person skilled in the art according to the gain requirement and the noise requirement of the optical amplifier. By controlling the preset pattern, the control of the mesa structure 21 obtained by etching is realized, so that the difference between the mesa width of the mesa structure 21 obtained by etching in the first region 212 and the mesa width in the second region 213 is larger than the first preset difference, thereby reducing the divergence angle, improving the coupling efficiency of the SOA chip and the optical fiber, and enabling the chip to have higher gain and lower noise index.
Based on this structure, siO was grown using PECVD (plasma enhanced chemical vapor deposition ) 2 Insulating layer andand opening a current injection window on the ridge by means of photoetching, etching and the like. Then deposit and grow SiO on the chip surface X Or SiN X Removing the dielectric film on the ridge and the electrode window by photoetching and etching, and then adopting an evaporation and sputtering method to manufacture upper and lower metal electrodes, wherein the electrode material is one or more of Ti, pt or Au. After the chip is dissociated, an optical film is usually deposited on the front and rear light emitting end surfaces in order to reduce the end surface reflection.
The specific fabrication method of the chip will be described below by taking an active layer 24 as an example of a buried heterojunction structure SOA. Fig. 2 shows an epitaxial structure 2 of an SOA according to the present application, in which a plurality of layers of epitaxial structures 2 are sequentially epitaxially grown on a semiconductor InP substrate 1, and the layers include an N-type InP buffer layer 22, an N-type InP lower cladding layer 23, an InGaAsP active layer 24, and a P-type InP first upper cladding layer 25. The specific manufacturing process of the SOA epitaxial structure 2 of the structure is that a lower cladding layer 23, an active layer 24 and a first upper cladding layer 25 are sequentially grown on a semiconductor substrate 1. Wherein the active layer 244 may be, but is not limited to, a buried heterojunction structure or a ridge waveguide structure, and in particular the corresponding epitaxial structure 2 may be obtained by one or more MOCVD techniques.
SiO with thickness around 2000A is grown on epitaxial structure 2 of FIG. 2 using PECVD X A film, and then a partially remaining SiO as shown in FIG. 11 is produced by means of photolithography and etching X And (3) a film. Retaining part of SiO X The top view of the SOA chip of the film is shown in FIG. 7, FIG. 8 or FIG. 9, according to the SiO retained X The width of the film is different to divide the chip into a first region 212 and a second region 213, wherein the length of the second region 213 is defined as L1, the length of the first region 212 is defined as L2 and L3 near different ends of the semiconductor amplifier, respectively, as shown in fig. 15, wherein the length of L1 ranges from 300 to 1300 μm, and the length of L2 and L3 ranges from 20 to 100 μm.
As can be seen, siO remains in the second region 213 and the first region 212 X The width of the film is different, the width of the oxide film of the second region 213 is larger or smaller than the width of the oxide film of the first region 212, when the width of the oxide film of the second region 213 is larger than the width of the oxide film of the first region 212, as shown in FIG. 7, when the width of the oxide film of the second region 21 is larger than the width of the oxide film of the first region3 is smaller than the oxide film width of the first region 212 as shown in FIG. 8, the first region 212 is formed of SiO at different ends X The film widths may be the same or different, and as shown in fig. 9, the oxide film width of the first region 212 at one end is larger than the oxide film width of the first region 212, and the oxide film width of the first region 212 at the other end is smaller than the oxide film width of the first region 212.
SiO of either the second region 213 or the first region 212 X The width of the film is in the range of 2-5 μm. Then ICP etching is carried out to remove SiO X The epitaxial layer outside the film covered region was etched to a depth of about 0.5 um. Subsequent use of Br-containing 2 The etching solution is subjected to wet etching, and the total depth of etching and etching reaches about 1.0 um. As shown in FIG. 12, due to SiO in the second region 213 and the first region 212, a side view of the chip after etching X The film widths are different so that after etching the widths of the active regions are also different, i.e. the sizes of W1, W2, W3 are different as shown in fig. 15, but they are all graded waveguides in the active regions, i.e. the change in width of the active layer 24 from the second region 213 to the first region 212 is graded. Note that the widths W1, W2, W3 of the active layer 24 in the second region 213 and the first region 212 are not one value and are gradually changed. Wherein the overall width of W1 is greater than or less than W2 and W3. W2 and W3 may be graded waveguides of the same width or graded waveguides of different widths, the width of which depends on SiO X Film width, etch and etch depth. The range of W1 is 1-3 μm, and the ranges of W2 and W3 are 0.5-2 μm or 2-4 μm.
Removing SiO covered by the first region 212 by photolithography and etching X Film, leaving only the SiO of the second region 213 X And (3) a film. The next step is to grow a P-type first barrier layer, which may be P-InP in particular, using MOCVD. The N-type second barrier layer is further grown, and can be N-InP. The SiO of the second region 213 is then removed by wet etching X The film is removed with BOE (Buffered Oxide Etch, buffered oxide etchant) solution. The N-type second barrier layer of the second region 213 is due to the previous SiO X The presence of a film on the SiO of the second region 213 X The film is removed during etching, without coatingOver active layer 24 in mesa 21. The N-type second barrier layer of the first region 212 is formed by removing SiO X A film forming a continuous N-type second barrier layer. On the basis of the above structure, the P-type second upper cladding layer is regrown, the specific material may be P-InP, and then the P-type ohmic contact layer is grown, specifically, highly doped P-InGaAs, and the entire epitaxial structure 2 is shown in fig. 15. As shown in fig. 13, the active layer 24 of the first region 212 has a P-N-P structure from top to bottom, and when a current is applied to the chip, the current from the second semiconductor layer 42 to the first semiconductor layer 41 is from N to P, which plays a role of blocking the current, so that the current cannot reach the active region, and thus the active layer 24 does not emit light. And the first upper cladding layer 25 of P-type and the second upper cladding layer (i.e. the third semiconductor layer 43) of P-type are arranged above the active layer 24 of the second region 213, and when current is applied to the chip, the current can be injected into the active layer 24 to emit light. In this configuration, the first region 212 serves only as an optical path without generating an electro-optic effect.
On the basis of this epitaxial structure 2, siO is grown using PECVD 2 And an insulating layer, and opening a current injection window on the ridge by means of photoetching, etching and the like. Then deposit and grow SiO on the chip surface X Or SiN X Removing the dielectric film on the ridge and the electrode window by photoetching and etching, and then adopting an evaporation and sputtering method to manufacture upper and lower metal electrodes, wherein the electrode materials are Ti, pt and Au. After the chip is dissociated, an optical film is usually deposited on the front and rear light-emitting end surfaces in order to reduce the end surface reflection.
In this embodiment, the light emitting region 211 and the no light region 210 are fabricated to realize local electro-optical conversion of the chip active layer 24, so as to further reduce chip heat generation and improve the lifetime of the chip. Meanwhile, the optimization of the far-field divergence angle of the chip is realized by utilizing the change of the optical waveguide size.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.

Claims (10)

1. A semiconductor optical amplifier, characterized by comprising a substrate (1) and a mesa structure (21) formed by etching an epitaxial structure (2) grown on the substrate (1);
the mesa structure (21) is divided into at least one matt region (210) and at least one light emitting region (211);
a current conducting structure (3) is grown above the mesa of the light emitting region (211) for conducting current to the mesa structure (21);
a first current blocking structure (4) is grown over the matt region (210) for blocking current from the upper layer to the mesa structure (21).
2. A semiconductor optical amplifier according to claim 1, characterized in that the first current blocking structure (4) comprises a first semiconductor layer (41) and a second semiconductor layer (42) grown on the first semiconductor layer (41); wherein the first semiconductor layer (41) is made of a P-type material, and the second semiconductor layer (42) is made of an N-type material.
3. A semiconductor optical amplifier according to claim 1, characterized in that the current conducting structure (3) comprises one or more semiconductor layers of the same doping type.
4. A semiconductor optical amplifier according to claim 1, characterized in that the part of the mesa (21) near both ends of the optical amplifier is divided into matt areas (210) and the part of the mesa (21) near the center of the optical amplifier is divided into light emitting areas (211).
5. A semiconductor optical amplifier according to claim 1, characterized in that the portion of the mesa (21) near both ends of the optical amplifier is divided into a first region (212) and the portion of the mesa (21) near the middle of the optical amplifier is divided into a second region (213) based on the distance from both ends of the optical amplifier;
a difference between a mesa width of the mesa structure (21) in the first region (212) and a mesa width in the second region (213) is greater than a first preset difference;
and at the connection position of the first region (212) and the second region (213), the mesa width of the mesa structure (21) is sequentially increased or decreased so as to realize smooth connection of the first region (212) and the second region (213) of the mesa structure (21).
6. A semiconductor optical amplifier according to any of claims 1-5, characterized in that the light emitting region (211) is further grown on both sides with a second current blocking structure (5) for blocking the upper layer of current from reaching both sides of the mesa structure (21); the second current blocking structure (5) is obtained by etching away a part of the structure of the first current blocking structure (4) above the table top of the light emitting area (211) after the first current blocking structure (4) grows above the light emitting area (211).
7. A semiconductor optical amplifier according to any of claims 1-5, characterized in that the epitaxial structure (2) comprises at least one of a buffer layer (22), a lower cladding layer (23), an active layer (24) and a first upper cladding layer (25).
8. A method of fabricating a semiconductor optical amplifier, characterized by growing an epitaxial structure (2) on a substrate (1), comprising:
growing a protective film (6) on the epitaxial structure (2), etching the protective film (6) to obtain a preset pattern, and etching the surface of the epitaxial structure (2) on which the protective film (6) is grown to obtain a mesa structure (21) covered with the protective film (6);
etching the protective film (6) in the no-light area (210), growing a plurality of semiconductor layers on the surface of the mesa structure (21), etching the protective film (6) in the light-emitting area (211) after the corresponding semiconductor layers are grown, and carrying out the growth of the subsequent semiconductor layers to obtain the current conducting structure (3) of the no-light area (210) and the first current blocking structure (4) of the light-emitting area (211).
9. The method for fabricating a semiconductor optical amplifier according to claim 8, wherein the step of growing a plurality of semiconductor layers on the surface of the mesa structure (21), and etching the protective film (6) in the light emitting region (211) after the corresponding semiconductor layers are grown, and performing the subsequent semiconductor layer growth comprises:
and growing a first semiconductor layer (41) and a second semiconductor layer (42) on the surface of the mesa structure (21), etching the protective film (6) in the light-emitting region (211) after growing the second semiconductor layer (42), and continuing to grow a third semiconductor layer (43) to obtain a first current blocking structure (4) in the no light region (210) and a current conducting structure (3) in the light-emitting region (211).
10. The method of fabricating a semiconductor optical amplifier according to claim 8, wherein a second difference between the mesa width of the predetermined pattern in the first region (212) and the mesa width in the second region (213) is greater than the predetermined difference;
and the widths of the table tops of the preset patterns are sequentially increased or decreased at the connection position of the first area (212) and the second area (213).
CN202310828044.2A 2023-07-06 2023-07-06 Semiconductor optical amplifier and manufacturing method thereof Pending CN117013365A (en)

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