CN117012805A - Terminal structure suitable for high-voltage power chip and manufacturing method - Google Patents
Terminal structure suitable for high-voltage power chip and manufacturing method Download PDFInfo
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- CN117012805A CN117012805A CN202310602819.4A CN202310602819A CN117012805A CN 117012805 A CN117012805 A CN 117012805A CN 202310602819 A CN202310602819 A CN 202310602819A CN 117012805 A CN117012805 A CN 117012805A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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Abstract
A termination structure for a high voltage power chip includes a plurality of concentric floating field limiting rings surrounding an active region and a transition region of the high voltage power chip, over which a passivation layer is covered. The application can improve the terminal reliability of the high-voltage high-power chip, improve the terminal efficiency, and simultaneously, consider the safe working area, has simple process and is suitable for large-scale product application. The application improves the terminal efficiency of the high-voltage power chip by optimizing the field ring design, and optimizes the safe working area while guaranteeing the reliability.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a terminal structure suitable for a high-voltage power chip and a manufacturing method thereof.
Background
High voltage high power devices are key devices for electrical power systems. In order to improve the current capacity of the chip, a vertical structural design is generally adopted, and thus, a terminal area needs to be arranged around the active area to ensure the reverse blocking capacity of the chip. Chip terminals have a variety of structures including field rings, field plates, junction termination extensions, negative bevels, composite or derivative terminals of these structures, and the like. For low voltage power devices, the blocking voltage and termination efficiency requirements can be met using only a single or a combination of termination structures. However, for a high-voltage chip with a higher withstand voltage level, a larger termination area is required, and the dynamic influence of the termination area will not be negligible in the case of both reliability and termination efficiency.
The simple equidistant field limiting ring terminal structure has large terminal area and low terminal efficiency. Junction termination extension structures are easy to design and manufacture, but strongly depend on the dose and energy of the implant, and if the doping concentration in the JTE is insufficient, the JTE region will be depleted at a lower voltage, causing the device to breakdown prematurely at the main junction (mesa edge), and if the doping concentration in the JTE region is too high, breakdown will also occur at the outermost edge of the JTE region. The method has a harsh requirement on the doping concentration range, a narrow process window, and is easily influenced by factors such as interface charges, so that the reliability of breakdown voltage is poor. The metal field plate in the field ring field plate structure can fix charges and prevent the charges from entering the oxide layer to affect the breakdown voltage. However, the design of the multi-stage field plate causes more steps and deep steps, and when the cleaning is not thorough, contamination residues and even leakage channels are formed. In particular, for silicon carbide devices, the ring width and ring spacing are relatively small, and conventional metal field plate processes are limited.
Disclosure of Invention
In order to overcome the defects of the prior art, the application provides a high-reliability terminal structure suitable for a high-voltage power chip and a manufacturing method thereof. The application improves the terminal efficiency of the high-voltage power chip by optimizing the field ring design, and optimizes the safe working area while guaranteeing the reliability.
The application adopts the following technical scheme:
a termination structure for a high voltage power chip includes a plurality of concentric floating field limiting rings surrounding an active region and a transition region of the high voltage power chip, over which a passivation layer is covered.
Further, the floating field limiter ring is located between the first surface of the body and the drift region, the floating field limiter ring surrounding the active region and the transition region structure.
Further, a first doped region of the second conductivity type and a second doped region of the first conductivity type are included between the first surface of the body and the drift region.
Further, the first doped region and the second doped region are concentric ring structures.
Further, the first doped region comprises a plurality of field ring regions.
Further, each field ring region comprises a plurality of field limiting rings, the ring widths and the ring distances in the field ring regions are constant, the ring widths of the field limiting rings decrease from the active region to the edge of the chip, and the ring distances of the field limiting rings increase.
Further, the first doped region includes a first main ring and a plurality of field ring regions.
Further, the first main ring and the field ring regions have the same doping concentration and doping depth, and the doping depth is not smaller than the doping depth of the well regions of the active region and the transition region.
Further, the loop width of the first main loop has an optimal value, which is related to the thickness of the substrate and the concentration of impurities in the loop. 10. The termination structure of claim 7, wherein the first main ring is spaced from the well region of the transition region by a distance of 1-1.2 um for silicon carbide devices and 5-40 um for silicon devices.
Further, the curvature radius of the inner ring of the first doped region, which is close to the transition region, at the corner position takes a value of 3-8 times the thickness of the drift region.
Further, the second doped region, having the first conductivity type, surrounds the side of the first doped region having the second conductivity type remote from the cell region.
Further, the passivation layer structure covering the field limiting ring comprises an oxide passivation layer, a silicon nitride passivation layer and a polyimide passivation layer.
Further, the silicon nitride passivation layer is made of a single-layer material and a multi-layer material.
Further, an oxide passivation layer having a base oxide layer, a silicon oxide layer and a doped thick oxide layer.
The application also relates to a manufacturing method of the high-voltage power chip with the high-reliability terminal structure, which comprises the following steps:
an epitaxial field termination layer and a drift layer are arranged on a substrate, and a trap region of an active region, a trap region of a transition region and a terminal field limiting ring are formed in the drift layer by one-time injection, so that a blocking ring is formed;
forming a passivation layer of a basic oxide layer;
forming an anode ohmic contact and a cathode ohmic contact;
forming a thick oxide passivation layer;
and forming a silicon nitride passivation layer and a polyimide passivation layer.
Compared with the prior art, the technical scheme of the application can realize the following beneficial technical effects:
1. the high-reliability terminal structure can still bear high voltage under the condition that positive charges exist in the oxide layer, and relatively high withstand voltage reliability is maintained.
2. The high-reliability terminal structure provided by the application has low sensitivity to doping implantation dose and simple manufacturing process.
3. Compared with the conventional field ring structure, the high-reliability terminal structure improves the terminal efficiency.
4. According to the high-reliability terminal structure, in the power chip turn-off process, the electric field distribution at the transition area is optimized, so that the concentration of hole current is reduced, the severity of current wires is reduced, and the safe working area of the chip is further improved.
Drawings
FIG. 1 is a schematic diagram showing a partial structure of an embodiment 1 of a high voltage power chip with high reliability terminals according to the present application;
FIG. 2 is a schematic diagram showing a partial structure of a high voltage power chip with high reliability terminals according to embodiment 2 of the present application;
FIG. 3 is a diagram showing the electric field and BV comparison between the high reliability terminal embodiment 1 and the common field ring structure terminal according to the present application;
FIG. 4 (a) is a diagram showing the electric field and BV comparison of the high reliability terminals of the present application in example 1 and example 2;
FIG. 4 (b) shows a plot of blocking voltage versus example 1 and example 2; FIG. 4 (c) is a graph showing the distribution of the highest electric field intensity in the body of example 1 and example 2;
FIG. 5 is a graph of blocking voltage and electric field for the case of varying implant dose for high reliability termination example 1 of the present application;
FIG. 6 is a graph of blocking voltage for the case of varying implant depth for high reliability termination example 1 of the present application;
FIG. 7 is a schematic diagram of a high reliability terminal embodiment 1 of the present application showing BV conditions in the case of oxide charge variation;
FIG. 8 is a graph showing the electric field distribution and ionization rate distribution of the high reliability terminals of the present application in example 1 and example 2;
fig. 8 (a) electric field distribution, and fig. 8 (b) ionization rate distribution.
FIG. 9 is a graph of blocking voltage and electric field for the case of varying implant dose for high reliability termination example 2 of the present application;
FIG. 10 is a graph of blocking voltage for the case of varying implant depth for high reliability termination example 2 of the present application;
FIG. 11 is a schematic diagram of a high reliability terminal embodiment 2 of the present application showing BV conditions in the case of oxide charge variation;
FIG. 12 is a graph showing the variation of the electric field in the case of the ring width bias of the first main ring according to the embodiment 2 of the high reliability terminal of the present application;
FIG. 13 is a flow chart of one embodiment of a method of manufacturing a high voltage power chip with high reliability terminals of the application;
reference numerals illustrate:
510. chip active region
520. Chip transition region
190. Chip termination region
100. Chip substrate
101. First surface of chip substrate
102. Second surface of chip substrate
131. Drift region having first conductivity type
191. A first doped region having a second conductivity type
192. Second doped region having first conductivity type
195. A first main loop with a terminal area close to the transition area
200. A field ring region having a termination region with n regions
132. Field stop layer having a first conductivity type
700. Collector region having a second conductivity type
Detailed Description
The objects, technical solutions and advantages of the present application will become more apparent by the following detailed description of the present application with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the application. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present application.
The method of the present application will be described in detail with reference to specific examples.
A first aspect of the present application provides a high reliability termination structure (190) for a high voltage power chip comprising a plurality of concentric floating field limiting rings surrounding a high voltage power chip active region and a transition region; a passivation layer is covered above the field limiting ring;
the floating field limiter ring is located between the first surface (101) of the body (100) and the drift region (131). The floating field limiter ring surrounds an active region (510) and a transition region structure (520).
Also included is a first doped region (191) of a second conductivity type and a second doped region (192) of the first conductivity type between the first surface (101) of the body (100) and the drift region (131).
The first doping region (191) and the second doping region (192) are in a concentric ring structure.
A first doped region (191) comprising n (greater than 1, less than 100) field ring regions (200).
The n field ring regions (200), wherein each field ring region is composed of m 1 ...m n The field limiting rings are formed. The ring width and the ring spacing of the field limiting rings in each field ring region can be the same or different. The ring width and the ring spacing of the field limiting rings between the n field ring regions may be the same or different. Preferably, the ring widths and the ring pitches in the field ring regions are constant, the ring widths of the n field ring regions decrease from the active region to the chip edge, and the ring pitches of the n field limiting rings increase. For silicon carbide devices, optionally, m 1 ...m n The values can be respectively 2 to 20. The ring width of the n field ring regions from the active region to the chip edge is reduced from 4um to 3um, and the ring spacing is increased from 1.2um to 7um. For silicon devices, optionally, m 1 ...m n The values can be respectively 2 to 15. The ring width of the n field ring regions is reduced from 40um to 5um from the active region to the chip edge, and the ring spacing is increased from 20um to 100um.
A first doped region (191) comprising a first main ring (195) and n (greater than 1, less than 100) field ring regions (200).
The first main ring (195) has the same doping concentration and doping depth as the n field ring regions (200), and the doping depth may be the same or deeper than the well regions of the active region (510) and the transition region (520).
The loop width of the first main loop (195) has an optimal value that is related to the substrate thickness and the substrate concentration and in-loop impurity concentration. When the ring width of the first main ring (195) takes an optimal value, the whole terminal shows high withstand voltage reliability under the condition that positive charges exist in the oxide layer, and is less influenced by fluctuation of the doping amount. Optionally, the first main ring (195) has a ring width that is 0.7 to 1.5 times the drift region thickness.
The first main ring (195) is at a distance of 1-1.2 um for silicon carbide devices and 5-40 um for silicon devices from the well region of the transition region (520).
The inner ring of the first doped region (191) near the transition region has a radius of curvature at the corner position of 3-8 times the thickness of the drift region.
And a second doped region (192) having the first conductivity type surrounding a side of the first doped region (191) having the second conductivity type remote from the cell region.
A passivation layer structure (400) covering the field limiting ring and comprising an oxide passivation layer (401), a silicon nitride passivation layer (Si X N Y O Z ) (402) and a Polyimide passivation layer (Polyimide) (403).
Silicon nitride passivation layer (Si) X N Y O Z ) (402) may be a single-layer material or a multi-layer material. The multi-layer material is a modified x, y and z configuration.
An oxide passivation layer (401) having a base oxide layer, a silicon oxide layer (4011) and a doped thick oxide layer (4012).
The application discloses a chip body, which comprises a first surface, a terminal field ring region, a stop ring with a first conductivity type, a field oxide passivation layer, a SiN passivation layer and a PI passivation layer. The field ring area has ring width following a certain decreasing rule, ring spacing following a certain increasing rule, and the first main ring has optimal ring width and ring spacing.
The terminal structure provided by the application is suitable for both high-voltage silicon carbide power devices and high-voltage silicon power devices.
The application also provides a manufacturing method of the high-reliability terminal structure suitable for the high-voltage power chip, when the high-voltage power chip is a silicon carbide high-voltage power chip, the method comprises the following steps:
epitaxially growing a defect conversion layer with a first conductivity type on a silicon carbide substrate with the first conductivity type, epitaxially growing a drift layer with the first conductivity type above the defect conversion layer, and continuing to epitaxially grow a field stop layer with the first conductivity type and a P collector layer with a second conductivity type; turning over the wafer; removing the substrate layer and the defect conversion layer by using a chemical mechanical polishing method; a well region of a cell region having a second conductivity type, a well region of a transition region, and a ring region of a terminal are simultaneously formed on a first surface of the drift layer. Specifically, an implantation window is formed on the first surface of the body region, ion implantation and junction pushing are carried out, a well region with a cell region of a second conductivity type, a well region with a transition region and a ring region of a terminal are formed at the same time, a second implantation window of an active region is formed on the first surface of which the first implantation and junction pushing are completed, high-dose ions of the first conductivity type are implanted in the exposed second implantation window, a source region and a cut-off ring region of the cell region are formed, a gate oxide layer and a field oxide layer are formed, a polysilicon gate layer is formed, an isolation oxide layer is formed, a third implantation window is formed again, and high-dose ions of the second conductivity type are implanted to form an emitter region; forming an emitter ohmic contact and an electrode; forming a terminal passivation layer structure; forming a collector ohmic contact and an electrode.
When the high voltage power chip is a silicon high voltage FRD chip, the application comprises the following steps:
forming a Buffer layer on the back surface of a silicon substrate with a first conductivity type through a Pocl3 process, turning over a wafer, forming a ring region with a terminal with a second conductivity type on the front surface, further forming a well region with the second conductivity type on the active region, forming a cut-off ring region with the first conductivity type at the edge of a chip, further forming a field oxide passivation layer and a thick isolation oxygen passivation layer, forming an anode ohmic contact region and a metal interconnection region, then forming a silicon nitride passivation layer and a polyimide passivation layer, turning over the wafer, and forming a cathode ohmic contact region and a metal interconnection layer. Finally, the service life control technology is realized through H injection, he injection or Pt injection technology and the like.
The high-voltage power chip is manufactured by the following method:
and (3) an epitaxial field termination layer and a drift layer are arranged on the substrate, a trap region of an active region, a trap region of a transition region and a terminal field limiting ring are formed in the drift layer by one-time injection, a stop ring is formed, a basic oxide layer passivation layer is formed, an anode ohmic contact is formed, a cathode ohmic contact is formed, a thick oxide layer passivation layer is formed, and a silicon nitride passivation layer and a polyimide passivation layer are formed.
Example 1
Referring to fig. 1, the present embodiment provides a terminal structure of a high voltage power chip, including: a plurality of concentric floating field confinement regions (190) surrounding the high voltage power chip active region (510) and the transition region (520); -a passivation layer (400) is covered over the field limiting ring region (190);
the body structure (100) has a first surface (101) and a second surface (102) opposite thereto.
A drift region (131) of a first conductivity type and a field stop layer (132) of the first conductivity type and a collector region (700) of the second conductivity type are formed in the body structure (100) adjacent to the second surface.
A termination field stop ring structure (190) is configured in the body structure (100), the floating field stop ring being located between the first surface (101) of the body (100) and the drift region (131). And, the floating field limiter ring surrounds the active region (510) and the transition region structure (520).
The termination field limiting ring structure (190) includes a first doped region (191) having a second conductivity type and a second doped region (192) having the first conductivity type.
The first doping region (191) and the second doping region (192) are of concentric ring structures, and the second doping region (192) is enclosed on one side of the first doping region (191) far away from the cell region.
The first doped region (191) at least partially surrounds the transition region (520).
The first doped region (191) is composed of n (greater than 1, less than 100) field ring regions (200). In this embodiment, n is 17.
The 17 field ring regions (200), wherein each field ring region is composed of m 1 ...m n The field limiting rings are formed. The ring width and the ring spacing of the field limiting rings in each field ring region can be the same or different. The ring width and the ring spacing of the field limiting rings between the n field ring regions may be the same or different. Preferably, the ring widths and the ring pitches in the field ring regions are constant, the ring widths of the n field ring regions decrease from the active region to the chip edge, and the ring pitches of the n field limiting rings increase. For silicon carbide devices, optionally, m 1 ...m n The values can be respectively 2 to 20. The ring width of the n field ring regions from the active region to the chip edge is reduced from 4um to 3um, and the ring spacing is increased from 1.2um to 7um.
The distance between the first doped region (191) and the well region of the transition region (520) is preferably 1-1.2 um.
The curvature radius of the inner ring of the first doping region (191) close to the transition region at the corner position is 4-8 times the thickness of the drift region.
The passivation layer structure (400) covering the field limiting ring comprises an oxide passivation layer (401), a silicon nitride passivation layer (Si X N Y O Z ) (402) and a Polyimide passivation layer (Polyimide) (403).
The silicon nitride passivation layer (Si X N Y O Z ) (402) may be a single-layer material or a multi-layer material. The multi-layer material is a modified x, y and z configuration.
The oxide passivation layer (401) is provided with a basic oxide layer, a silicon oxide layer (4011) and a doped thick oxide layer (4012).
Compared to a conventional field ring structure terminal of a fixed ring width and a ring pitch, this embodiment 1 realizes a higher blocking voltage at the same terminal size, as shown in fig. 3. In addition, the injection area of the present embodiment 1 is relatively small, and the leakage current level can be reduced. The termination structure described in this embodiment 1 has low sensitivity to the implantation window. As shown in fig. 5 and 6. In the termination structure of embodiment 1, when a fixed charge exists in the termination field oxide layer, the reliability is high, as shown in fig. 7.
Example 2
Referring to fig. 2, the present embodiment provides a terminal structure of a high-voltage power chip with high reliability for improving chip robustness, including:
a high reliability termination structure for a high voltage power chip includes a plurality of concentric floating field confinement regions (190) surrounding a high voltage power chip active region (510) and a transition region (520); -a passivation layer (400) is covered over the field limiting ring region (190);
the body structure (100) has a first surface (101) and a second surface (102) opposite thereto.
A drift region (131) of a first conductivity type and a field stop layer (132) of the first conductivity type and a collector region (700) of the second conductivity type are formed in the body structure (100) adjacent to the second surface.
A termination field stop ring structure (190) is configured in the body structure (100), the floating field stop ring being located between the first surface (101) of the body (100) and the drift region (131). And, the floating field limiter ring surrounds the active region (510) and the transition region structure (520).
The termination field limiting ring structure (190) includes a first doped region (191) having a second conductivity type and a second doped region (192) having the first conductivity type.
The first doping region (191) and the second doping region (192) are of concentric ring structures, and the second doping region (192) is enclosed on one side of the first doping region (191) far away from the cell region.
The first doped region (191) at least partially surrounds the transition region (520).
The first doped region (191) is comprised of a first main ring (195) and n (greater than 1, less than 100) field ring regions (200).
The first main ring (195) surrounds the transition region (520), is located outside the transition region (520), and is located inside the n field ring regions (200).
The inner ring of the first main ring (195) near the transition region has a drift region thickness with a radius of curvature of 3-8 times at the corner position.
The first main ring (195) and the n field ring regions (200) may have the same or different doping concentrations and doping depths.
The loop width of the first main loop (195) has an optimal value that is related to the substrate thickness and the substrate concentration and in-loop impurity concentration. When the ring width of the first main ring (195) takes an optimal value, the reliability is strongest in the case that positive charges exist in the oxide layer of the whole terminal, and compared with other ring width taking schemes, the scheme can reduce the electric field intensity of a transition region close to a cell region, and in the turn-off process, the degree of current filaments appearing at the transition region is reduced.
The first main ring (195) is preferably 1-1.2 um from the active region (510) well region or from the transition region implant well.
Of the 17 field ring regions (200), each field ring region is composed of m 1 ...m n A field ring composition, i.e. each field ring region contains m x (x is taken1-n) field rings having the same or different ring widths and the same or different ring spacings. In this embodiment, the same ring width and ring spacing are used in each field ring region, and each field ring region has different ring widths and ring spacings compared with each other. The ring width and the ring spacing in each field ring region are constant values, and the ring width of each field ring region is in a decreasing trend from the active region to the edge of the chip, and the ring spacing is in an increasing trend. The ring width of the present example decreases from 4um to 3um and the ring spacing increases from 1.2um to 7um.
The passivation layer structure (400) covering the field limiting ring comprises an oxide passivation layer (401), a silicon nitride passivation layer (Si X N Y O Z ) (402) and a Polyimide passivation layer (Polyimide) (403).
The silicon nitride passivation layer (Si X N Y O Z ) (402) may be a single-layer material or a multi-layer material. The multi-layer material is a modified x, y and z configuration.
The oxide passivation layer (401) is provided with a basic oxide layer, a silicon oxide layer (4011) and a doped thick oxide layer (4012).
Based on embodiment 1, the terminal structure is further optimized, and under the condition of not degrading blocking capability, the dynamic robustness of the chip is further improved, in embodiment 2, the distribution of holes in the transition region is reduced, the concentration of an electric field in the transition region is reduced, and then the impact ionization rate in the device turn-off process is reduced, as shown in fig. 8, so that the local temperature rise in the device turn-off process is favorably inhibited. The terminal structure described in this embodiment 2 has low sensitivity to the implantation window, as shown in fig. 9 and 10. In the termination structure of embodiment 1, when a fixed charge exists in the termination field oxide layer, the reliability is high, as shown in fig. 11. In addition, the bias simulation was performed on the width of the first loop width, and when the loop width was narrow, the electric field improvement effect was not obvious as close to that of example 1, and when the loop width was too wide, the electric field distribution effect on the whole terminal was obvious as shown in fig. 12.
Example 3
As shown in fig. 13, and also as shown in fig. 1, the present embodiment provides a method for manufacturing a high-voltage power chip, specifically, the method for manufacturing a high-voltage power chip in embodiment 1.
The method comprises the following steps:
in step S01, a substrate having a first conductivity type is provided.
And step S02, epitaxially growing a defect conversion layer with a first conductivity type on the substrate, epitaxially growing a drift layer with the first conductivity type on the defect conversion layer, and continuing to epitaxially grow a field stop layer with the first conductivity type and a P collector layer with a second conductivity type, wherein the first conductivity type ions are N-type ions or P-type ions.
Step S03, turning over the wafer.
In step S04, a Chemical Mechanical Planarization (CMP) technique is applied to remove the epitaxially grown defect conversion layer (this layer converts BPD defects to TED defects), and the substrate layer.
Step S05, an impurity region forming step.
And depositing a layer of silicon oxide on the first surface of the body region as an implanted shielding layer, and then performing photoetching to form an implantation window of the cell region and an annular implantation window of the terminal region.
And implanting ions of the second conductivity type, and simultaneously forming a well region of the cellular region, a well region of the transition region and a ring region of the terminal. When the first conductive type ions are N-type ions, the second conductive type ions are P-type ions; when the first conductivity type ions are P-type ions, the second conductivity type ions are N-type ions, and in the example of the present application, the second conductivity type ions are P-type ions. The P-type ion implanted in this example is aluminum (Al) ion, ion implantation is performed on a high temperature implanter at a temperature of 400-1000 ℃ and with a dose of 1E14-3E15 and an energy of 50-350KeV, and then ion junction pushing is performed appropriately at a temperature of 1400-1650 ℃.
And removing the silicon oxide shielding layer.
A field oxide layer is grown on the first surface where the implantation and the push junction have been completed and the active region is exposed by photolithography, while the transition region and the termination region are covered, according to the layout.
A high dose of ions of the first conductivity type are implanted in the exposed active region.
The N-type ions implanted in the application are aluminum (N) ions, the implantation of the ions is carried out at the dosage of 1E15-3E15 and the energy of 30-100KeV, and then, proper ion push junction is carried out.
Step S06 to step S07, a film formation step and an electrode formation step. The film forming step comprises the formation of a gate oxide layer, a field oxide layer, a gate polysilicon layer, an isolation oxide layer and a terminal passivation layer. The electrode forming step includes forming an emitter, a collector, and a gate. The present application will not be described in detail.
Example 4
The embodiment provides a manufacturing method of a silicon high-voltage FRD chip.
The method comprises the following steps:
in step S01, a silicon substrate having a first conductivity type is provided.
In step S02, a Buffer layer is formed on the back surface of the silicon substrate having the first conductivity type by a Pocl3 process.
Step S03, turning over the wafer.
In step S04, a ring region having a terminal of the second conductivity type is formed on the front surface. Specifically, a layer of silicon oxide is deposited on the first surface of the body region as an implanted shielding layer, and then photoetching is performed to form an annular implantation window of the termination region. And implanting and pushing the second conductive type ions to form a loop region of the terminal. When the first conductive type ions are N-type ions, the second conductive type ions are P-type ions; when the first conductivity type ion is a P-type ion, the second conductivity type ion is an N-type ion, and in the example of the present application, the second conductivity type ion is a P-type ion, specifically, a boron (B) ion.
And 5, forming a well region with the second conductivity type in the active region.
And 6, forming a cut-off ring region with the first conductivity type at the edge position of the chip. In the present example, the first conductivity type ion is an N-type ion, here specifically a phosphorus (Ph) ion.
And 7, forming a field oxygen passivation layer and a thick isolation oxygen passivation layer.
And 8, forming an anode ohmic contact region and a metal interconnection region.
Step 9, forming a silicon nitride passivation layer (Si X N Y O Z ) And Polyimide passivation layers (Polyimide).
Step 10, turning over the wafer.
And 11, forming a cathode ohmic contact region and a metal interconnection layer.
And step 12, finally, realizing a service life control technology through an H injection, he injection or Pt injection process and the like.
In summary, the present application provides a terminal structure suitable for a high voltage power chip, which includes a plurality of concentric floating field limiting rings surrounding an active region and a transition region of the high voltage power chip, and a passivation layer covering the field limiting rings. The application can improve the terminal reliability of the high-voltage high-power chip, improve the terminal efficiency, and simultaneously, consider the safe working area, has simple process and is suitable for large-scale product application. The application improves the terminal efficiency of the high-voltage power chip by optimizing the field ring design, and optimizes the safe working area while guaranteeing the reliability.
The above detailed description of the present application is merely illustrative or explanatory of the principles of the application and is not necessarily intended to limit the application. Accordingly, any modification, equivalent replacement, improvement, etc. made without departing from the spirit and scope of the present application should be included in the scope of the present application. Furthermore, the appended claims are intended to cover all such changes and modifications that fall within the scope and boundary of the appended claims, or equivalents of such scope and boundary.
Claims (16)
1. A termination structure for a high voltage power chip comprising a plurality of concentric floating field limiting rings surrounding an active region and a transition region of the high voltage power chip, the field limiting rings being covered with a passivation layer.
2. The termination structure for a high voltage power chip of claim 1, wherein the floating field limiter ring is located between the first surface of the body and the drift region, the floating field limiter ring surrounding the active region and the transition region structure.
3. The termination structure for a high voltage power chip of claim 1, comprising a first doped region of a second conductivity type and a second doped region of the first conductivity type between the first surface of the body and the drift region.
4. The termination structure of claim 3, wherein the first doped region and the second doped region are concentric ring structures.
5. The termination structure for a high voltage power chip of claim 4, wherein the first doped region comprises a plurality of field ring regions.
6. The termination structure of claim 5, wherein each field ring region includes a plurality of field limiting rings, the ring widths and ring spacing within each field ring region being constant, the ring widths of the plurality of field ring regions being in a decreasing trend from the active region to the chip edge, the ring spacing of the field limiting rings being in an increasing trend.
7. The termination structure for a high voltage power chip of claim 4, wherein the first doped region comprises a first main ring and a plurality of field ring regions.
8. The termination structure of claim 7, wherein the first main ring and the plurality of field ring regions have the same doping concentration and doping depth, the doping depth being not less than the well doping depth of the active region and the transition region.
9. The termination structure for a high voltage power chip according to claim 7, wherein the loop width of the first main loop has an optimum value that is related to the thickness of the substrate and the concentration of impurities in the loop.
10. The termination structure of claim 7, wherein the first main ring is spaced from the well region of the transition region by a distance of 1-1.2 um for silicon carbide devices and 5-40 um for silicon devices.
11. The termination structure for a high voltage power chip of claim 4, wherein the inner ring of the first doped region near the transition region has a radius of curvature at the corner position that is 3-8 times the thickness of the drift region.
12. The termination structure of claim 4, wherein the second doped region has a first conductivity type surrounding a side of the first doped region having a second conductivity type remote from the cell region.
13. The termination structure for a high voltage power chip of claim 12, wherein the passivation layer structure overlying the field limiting ring comprises an oxide passivation layer, a silicon nitride passivation layer, and a polyimide passivation layer.
14. The termination structure of claim 12, wherein the silicon nitride passivation layer is a single layer material and a multi-layer material.
15. The termination structure for a high voltage power chip of claim 13, wherein the oxide passivation layer has a base oxide layer, a silicon oxide layer and a doped thick oxide layer.
16. A method of manufacturing a high voltage power chip having a high reliability termination structure, comprising the steps of:
an epitaxial field termination layer and a drift layer are arranged on a substrate, and a trap region of an active region, a trap region of a transition region and a terminal field limiting ring are formed in the drift layer by one-time injection, so that a blocking ring is formed;
forming a passivation layer of a basic oxide layer;
forming an anode ohmic contact and a cathode ohmic contact;
forming a thick oxide passivation layer;
and forming a silicon nitride passivation layer and a polyimide passivation layer.
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