CN117012704A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
CN117012704A
CN117012704A CN202210461336.2A CN202210461336A CN117012704A CN 117012704 A CN117012704 A CN 117012704A CN 202210461336 A CN202210461336 A CN 202210461336A CN 117012704 A CN117012704 A CN 117012704A
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CN
China
Prior art keywords
layer
forming
mask
semiconductor device
dielectric layer
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Pending
Application number
CN202210461336.2A
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Chinese (zh)
Inventor
王江红
高大为
吴永玉
余晴
周鲁豪
何刚博
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Zhejiang Chuangxin Integrated Circuit Co ltd
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Zhejiang Chuangxin Integrated Circuit Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Zhejiang Chuangxin Integrated Circuit Co ltd filed Critical Zhejiang Chuangxin Integrated Circuit Co ltd
Priority to CN202210461336.2A priority Critical patent/CN117012704A/en
Publication of CN117012704A publication Critical patent/CN117012704A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of forming a semiconductor device, comprising: providing a substrate, wherein a dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer; forming a mask opening penetrating through the mask layer in the mask layer, wherein the top size of the mask opening is larger than the bottom size, and the side wall of the mask opening has an inclination angle; etching the dielectric layer along the mask opening by taking the mask layer as a mask to form a groove penetrating through the dielectric layer; and filling the groove to form an interconnection structure. The invention is beneficial to improving the running speed of the semiconductor device and the yield of the semiconductor device.

Description

Method for forming semiconductor device
Technical Field
The embodiment of the invention relates to the field of semiconductors, in particular to a method for forming a semiconductor device.
Background
With the rapid development of semiconductor device fabrication technology, the number of components contained in an integrated circuit is increasing, and the demands on the integration level and performance of the integrated circuit are becoming higher and higher. In order to improve the integration level and reduce the manufacturing cost, the critical dimensions of the components are continuously reduced, and the number of components in a unit area of a chip is continuously increased.
The electrical connection of the electrical circuit typically requires the use of an interconnect structure. The formation of the interconnection structure generally requires that an opening is formed in the dielectric layer, and then a conductive material is filled in the opening to form the interconnection structure.
However, the existing process of forming the interconnect structure easily affects the yield of the device.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor device, and improves the yield of the semiconductor device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein a dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer; forming a mask opening penetrating through the mask layer in the mask layer, wherein the top size of the mask opening is larger than the bottom size, and the side wall of the mask opening has an inclination angle; etching the dielectric layer along the mask opening by taking the mask layer as a mask to form a groove penetrating through the dielectric layer; and filling the groove to form an interconnection structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor device provided by the embodiment of the invention, the top dimension of the mask opening is larger than the bottom dimension, the side wall has an inclination angle, and the dielectric layer is etched along the mask opening to form a groove; in the embodiment of the invention, the mask opening with the top size larger than the bottom size and the side wall with the inclined angle is formed, so that the pattern of the mask opening is transferred to the medium layer in the step of etching the medium layer along the mask opening, a groove with the larger top size can be obtained, the process window for taking residues generated by etching out of the groove is favorably increased in the process of etching the medium layer, the probability that the residues generated by etching accumulate at the top corner of the groove is correspondingly reduced, the filling performance of an interconnection structure is favorably improved, the probability that the interconnection structure is incomplete in filling and a cavity is formed is reduced, the running speed of a semiconductor device is further improved, and the yield of the semiconductor device is improved.
Drawings
Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor device;
fig. 5 to 9 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor device according to the present invention.
Detailed Description
As known from the background art, the existing process of forming the interconnection structure easily affects the yield of the device. Now, in conjunction with a method for forming a semiconductor device, the reason why the existing process for forming an interconnection structure easily affects the yield of the device is analyzed.
Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor device.
Referring to fig. 1, a substrate 10 is provided, a dielectric layer 20 is formed on the substrate 10, and a mask layer 40 is formed on the dielectric layer 20.
Referring to fig. 2, a mask opening 41 penetrating the mask layer 40 is formed in the mask layer 40, and sidewalls of the mask opening 41 are perpendicular to a bottom surface of the mask layer 40.
Referring to fig. 3, dielectric layer 20 is etched along mask opening 41 with mask layer 40 as a mask to form trench 23 extending through dielectric layer 20.
Referring to fig. 4, trenches 23 are filled to form interconnect structure 50.
It has been found that, by using the mask layer 40 as a mask, the pattern of the mask opening 41 is transferred into the dielectric layer 20, and since the sidewall of the mask opening 41 is perpendicular to the bottom surface of the mask layer 40, the top dimension of the formed trench 23 is smaller, so that the process window for taking the residues generated by etching out of the trench 23 in the process of etching the dielectric layer 20 is smaller, and the residues generated by etching are easily accumulated at the top corner of the trench 23 (as shown by the dotted circle in fig. 3), thereby affecting the filling of the subsequent interconnection structure 50.
Specifically, since residues generated by etching accumulate at the top corners of the trenches 23, the process window when filling the trenches 23 is reduced, and the trenches 23 are not filled yet in the process of filling the trenches 23, the interconnect structures 50 at the tops of the trenches 23 are in contact with each other, so that the interconnect structures 50 are not completely filled and voids (void) are formed, thereby affecting the yield of the semiconductor device.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein a dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer; forming a mask opening penetrating through the mask layer in the mask layer, wherein the top size of the mask opening is larger than the bottom size, and the side wall of the mask opening has an inclination angle; etching the dielectric layer along the mask opening by taking the mask layer as a mask to form a groove penetrating through the dielectric layer; and filling the groove to form an interconnection structure.
In the method for forming the semiconductor device provided by the embodiment of the invention, the top dimension of the mask opening is larger than the bottom dimension, the side wall has an inclination angle, and the dielectric layer is etched along the mask opening to form a groove; in the embodiment of the invention, the mask opening with the top size larger than the bottom size and the side wall with the inclined angle is formed, so that the pattern of the mask opening is transferred to the medium layer in the step of etching the medium layer along the mask opening, a groove with the larger top size can be obtained, the process window for taking residues generated by etching out of the groove is favorably increased in the process of etching the medium layer, the probability that the residues generated by etching accumulate at the top corner of the groove is correspondingly reduced, the filling performance of an interconnection structure is favorably improved, the probability that the interconnection structure is incompletely filled and a cavity is formed is reduced, and the yield of a semiconductor device is further improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 5 to 9, schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor device according to the present invention are shown.
Referring to fig. 5, a substrate 100 is provided, a dielectric layer 200 is formed on the substrate 100, and a mask layer 400 is formed on the dielectric layer 200.
The substrate 100 is used to provide a process platform for the formation process of semiconductor devices. Among them, semiconductor devices include planar field effect (MOS) transistors, fin field effect transistors (finfets), and gate-all-around (GAA) transistors.
In this embodiment, taking a transistor structure as an example of a planar field effect transistor, the substrate 100 is correspondingly a substrate.
In this embodiment, the base 100 is a silicon substrate. In other embodiments, the material of the base may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the base may be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.
In this embodiment, a gate structure 120 is formed on the substrate 100, and source/drain doped layers 110 are formed in the substrate 100 at two sides of the gate structure 120.
Specifically, the substrate 100 between the source and drain doped layers 110 on both sides of the same gate structure 120 is used to provide a channel of a transistor.
In other embodiments, the semiconductor device may also be a three-dimensional transistor, such as a fin field effect transistor and a fully-surrounding gate transistor; correspondingly, the base comprises a substrate and a channel structure positioned above the substrate; the gate structure spans the channel structure, and the source-drain doped layer 110 is formed in the channel structure at two sides of the gate structure 120.
The material of the channel structure includes silicon, silicon germanium, silicon carbide, or a group iii-v semiconductor material. The material of the channel structure depends on the channel conductivity type and performance requirements of the transistor. As an example, the material of the channel structure is silicon.
The gate structure 120 is used to control the turning on or off of the channel of the transistor.
In this embodiment, the gate structure 120 is a polysilicon gate structure. In other embodiments, the gate structure may also be a metal gate structure.
The source-drain doped layer 110 serves as a source or drain of a transistor.
Specifically, the doping type of the source-drain doping layer 110 is the same as the channel conductivity type of the corresponding transistor.
In this embodiment, an isolation structure (not shown) covering the sidewall of the trench structure is also formed in the substrate 100. In this embodiment, the isolation structure is a shallow trench isolation (shallow trench isolation, STI) structure for achieving isolation between different devices, for example, in a CMOS manufacturing process, an STI structure is typically formed between an NMOS transistor and a PMOS transistor. As an example, the material of the isolation structure is silicon oxide.
Dielectric layer 200 is used to provide a process platform for subsequently formed trenches and also to isolate subsequently formed interconnect structures from one another.
In this embodiment, the dielectric layer 200 includes a filling layer 210 and a planarization layer 220 on the filling layer 210, wherein the top of the filling layer 210 is higher than the top of the gate structure 120.
The filling layer 210 fills the side portion of the gate structure 120 and covers the gate structure 120 and the substrate 100, and is used for filling the height difference between the gate structure 120 and the substrate 100, so as to provide a better platform for forming the planarization layer 220.
In this embodiment, the filling layer 210 material includes a high density plasma (High Density Plasma, HDP) material, and the gap filling property of the HDP material is good, which is beneficial to well filling the gaps with height differences, so as to form the filling layer 210 with high film quality.
The planarization layer 220 is used for covering the filling layer 210 to form a mesa with higher flatness, so as to provide a better mesa for subsequent processing.
In this embodiment, the material of the planarization layer 220 includes tetraethyl orthosilicate (Tetra Ethyl Ortho Silicate, TEOS), and a relatively flat top surface can be obtained when the TEOS is formed, so that the planarization layer 220 with a relatively high top surface flatness can be formed.
The mask layer 400 is subsequently patterned, so that the patterned mask layer 400 is used as an etching mask for subsequently etching the dielectric layer 200.
In this embodiment, the material of the mask layer 400 includes a photosensitive material.
The pattern opening can be obtained by exposing the photosensitive material, the process is simple and easy to operate, and in the exposure process, mask openings with different shapes can be obtained by adjusting process parameters, for example, the mask opening which is required to be formed later and has a top size larger than a bottom size and a side wall with an inclined angle can be obtained.
Specifically, in this embodiment, the material of the mask layer 400 includes photoresist.
It should be noted that the thickness of the mask layer 400 should not be too large or too small. If the thickness of the mask layer 400 is too large, the difficulty of the subsequent process for forming the mask opening (for example, the difficulty of the subsequent exposure process) is easily increased, and unnecessary process waste is also easily caused; if the thickness of the mask layer 400 is too small, the mask opening formed later is difficult to form a morphology with a top dimension larger than a bottom dimension and a sidewall having an inclination angle, so that the subsequent process of etching the dielectric layer 200 along the mask opening is easy to be affected, and a trench meeting the process requirement is difficult to be formed, thereby affecting the formation quality of the interconnection structure. For this purpose, in the present embodiment, the thickness of the mask layer 400 isTo->
In this embodiment, an anti-reflection layer 300 is further formed between the dielectric layer 200 and the mask layer 400, so as to eliminate or alleviate exposure reflection, thereby effectively improving the lithography accuracy in the subsequent exposure process.
Specifically, in this embodiment, the anti-reflective layer 300 includes a plasma enhanced oxide (PE-oxide) layer (not shown), and a bottom anti-reflective coating (BARC) layer on the PE oxide layer.
Referring to fig. 6, a mask opening 410 penetrating the mask layer 400 is formed in the mask layer 400, the top dimension of the mask opening 410 is larger than the bottom dimension and the sidewalls have an inclination angle.
In this embodiment, the mask opening 410 with a top size larger than a bottom size and an inclined angle on the sidewall is formed, so that in the step of etching the dielectric layer 200 along the mask opening 410, the pattern of the mask opening 410 is transferred into the dielectric layer 200, so that a trench with a larger top size can be obtained, which is beneficial to increasing the process window for taking the residues generated by etching out of the trench in the process of etching the dielectric layer 200, and correspondingly reducing the probability of accumulating the residues generated by etching at the top corner of the trench, thereby being beneficial to improving the filling performance of the subsequently formed interconnection structure, reducing the probability of incomplete filling and void formation of the interconnection structure, and further improving the yield of the semiconductor device.
In this embodiment, the mask layer 400 is made of a photosensitive material, and accordingly, a mask opening 410 penetrating the mask layer 400 is formed in the mask layer 400 by using an exposure process.
Specifically, during exposure, by adjusting process parameters (e.g., adjusting exposure energy or focal length), a mask opening 410 having a top dimension greater than a bottom dimension and sidewalls having an oblique angle can be obtained.
It should be noted that, the angle α between the sidewall of the mask opening 410 and the bottom surface of the mask layer 400 should not be too large or too small. If the included angle α between the sidewall of the mask opening 410 and the bottom surface of the mask layer 400 is too large, the top dimension of the mask opening 410 is smaller, and then the pattern of the mask opening 410 is transferred into the dielectric layer 200, so that it is difficult to obtain a trench with a larger top dimension, thereby causing poor effect of increasing the process window of taking the residues generated by etching out of the trench, and correspondingly causing poor effect of reducing the probability of accumulating residues generated by etching at the top corner of the trench, and further affecting the filling performance of the subsequent interconnection structure; if the included angle α between the sidewall of the mask opening 410 and the bottom surface of the mask layer 400 is too small, the top dimension of the mask opening 410 is too large, and then the pattern of the mask opening 410 is transferred to the dielectric layer 200, which easily results in the oversized opening dimension of the formed trench, so that the gate structure 120 at the side of the trench is easily damaged, and after the interconnection structure is formed, the problem of short circuit between the interconnection structure and the gate structure 120 is easily caused. For this reason, in the present embodiment, the included angle α between the sidewall of the mask opening 410 and the bottom surface of the mask layer 400 is 45 ° to 80 °.
In this embodiment, the mask opening 410 is formed above the gate structure 120 and/or above the source/drain doped layer 110, so that the trench exposing the gate structure 120 and the trench exposing the source/drain doped layer 110 can be formed by etching the dielectric layer 200 along the mask opening 410, and the electrical property of the gate structure 120 and the source/drain doped layer 110 can be led out after the interconnection structure is formed in the trench.
Referring to fig. 7, the dielectric layer 200 is etched along the mask opening 410 with the mask layer 400 as a mask, forming a trench 230 penetrating the dielectric layer 200.
Trench 230 provides a spatial location for subsequent formation of an interconnect structure.
In this embodiment, the pattern of the mask opening 410 is transferred to the dielectric layer 200, and the top dimension of the trench 230 is larger than the bottom dimension, which is favorable for increasing the process window for taking the residues generated by etching out of the trench 230 in the process of etching the dielectric layer 200 to form the trench 230, and correspondingly reducing the probability of accumulating the residues generated by etching at the top corner of the trench 230, thereby being favorable for improving the filling performance of the subsequently formed interconnection structure, reducing the probability of incomplete filling and void formation of the interconnection structure, and further improving the yield of the semiconductor device.
In this embodiment, an anisotropic dry etching process is used to etch the dielectric layer 200 along the mask opening 410.
The dry etching process has the characteristic of anisotropic etching, and the dry etching has more etching directionality, thereby being beneficial to improving the shape quality and the dimensional accuracy of the side wall of the groove 230.
In this embodiment, the trench 230 includes: a gate plug trench 240 penetrating the dielectric layer on top of the gate structure 120 and exposing the top of the gate structure 120, and a source drain plug trench 250 penetrating the dielectric layer on top of the source drain doped layer 110 and exposing the top of the source drain doped layer 110.
Gate plug trenches 240 are used to provide spatial locations for forming gate plugs and source drain plug trenches 250 are used to provide spatial locations for forming source drain plugs.
In this embodiment, the aspect ratio of the trench 230 is greater than or equal to 5:1, thus the trench 230 can penetrate through the thicker dielectric layer 200 and be positioned at the top of the gate structure 120 or the source-drain doped layer 110 more accurately, meanwhile, the depth-width ratio of the trench 230 is larger, so that the difficulty of taking residues generated by etching out of the trench 230 in the process of etching the dielectric layer 200 to form the trench 230 is larger, the embodiment is particularly suitable for the process with larger depth-width ratio of the trench 230, the probability that residues generated by etching accumulate at the corner of the top of the trench 230 is reduced, the filling performance of the subsequently formed interconnection structure is improved, the probability that the interconnection structure is incompletely filled and a cavity is formed is reduced, and the yield of a semiconductor device is further improved.
Referring to fig. 8 and 9 in combination, the trench 230 is filled to form an interconnect structure 510.
Interconnect structure 510 is used to make electrical connection of the front-end devices and the back-end interconnect structure.
Specifically, in this embodiment, the interconnect structure 510 includes a gate plug in the gate plug trench 240 and a source drain plug in the source drain plug trench 250.
The gate plug is used for electrically leading out the gate structure 120, so as to realize the electrical connection between the gate structure 120 and the back-end interconnection structure.
The source-drain plugs are used for electrically leading out the source-drain doped layer 110, so as to realize the electrical connection between the source-drain doped layer and the back-end interconnection structure.
In this embodiment, the material of the interconnect structure 510 includes tungsten, cobalt, or ruthenium.
The filling property of tungsten, cobalt or ruthenium is good, the interconnection structure 510 with high film quality can be formed, and the conductivity of tungsten, cobalt or ruthenium is good, so that the interconnection structure 510 with good conductivity can be formed.
Specifically, referring to fig. 8, filling the trench 230, the step of forming the interconnect structure 510 includes: a layer 500 of interconnect structure material is formed filling the trench 230 and covering the top of the dielectric layer 200.
The interconnect structure material layer 500 is used to directly form an interconnect structure 510.
In this embodiment, the interconnect structure material layer 500 is formed using a chemical vapor deposition process.
The chemical vapor deposition process has good deposition effect, high gap filling capability, high-quality interconnection structure material layer 500 formation, and reduced voids in the film.
Referring to fig. 9, the step of filling the trench 230, forming the interconnect structure 510 further includes: the interconnect structure material layer 500 is planarized, the interconnect structure material layer 500 is removed above the top of the dielectric layer 200, and the interconnect structure material layer 500 filled in the trench 230 remains as the interconnect structure 510.
The interconnect structure material layer 500 is formed first, and then the interconnect structure material layer 500 is planarized to obtain the interconnect structure 510, which is favorable for making the top surface of the interconnect structure 510 relatively flat, and correspondingly obtaining a platform with relatively high flatness, thereby providing a relatively good process platform for other subsequent process steps.
It should be noted that, in other embodiments, the mask opening may be formed only above the gate structure according to the process requirement; accordingly, the interconnect structure includes only the gate plug located in the gate plug trench.
In other embodiments, the mask opening may be formed only above the source-drain doped layer according to the process requirement; accordingly, the interconnect structure is located only in the source-drain plug trench.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (13)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein a dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer;
forming a mask opening penetrating through the mask layer in the mask layer, wherein the top size of the mask opening is larger than the bottom size, and the side wall of the mask opening has an inclination angle;
etching the dielectric layer along the mask opening by taking the mask layer as a mask to form a groove penetrating through the dielectric layer;
and filling the groove to form an interconnection structure.
2. The method of forming a semiconductor device of claim 1, wherein in the step of forming the trench, a top dimension of the trench is greater than a bottom dimension.
3. The method of forming a semiconductor device according to claim 1, wherein a material of the mask layer comprises a photosensitive material;
and forming a mask opening penetrating through the mask layer in the mask layer by adopting an exposure process.
4. The method of forming a semiconductor device of claim 3, wherein the material of the mask layer comprises a photoresist.
5. The method of forming a semiconductor device according to claim 1, wherein in the step of providing a substrate, a thickness of the mask layer isTo->
6. The method of forming a semiconductor device of claim 1, wherein said dielectric layer is etched along said mask opening using an anisotropic dry etch process.
7. The method of forming a semiconductor device according to claim 1, wherein in the step of forming a mask opening penetrating the mask layer in the mask layer, an angle between a sidewall of the mask opening and a bottom surface of the mask layer is 45 ° to 80 °.
8. The method of forming a semiconductor device of claim 1, wherein filling the trench, the step of forming an interconnect structure comprises: forming an interconnection structure material layer which fills the groove and covers the top of the dielectric layer;
and flattening the interconnection structure material layer, removing the interconnection structure material layer higher than the top of the dielectric layer, and reserving the interconnection structure material layer filled in the groove as the interconnection structure.
9. The method of forming a semiconductor device according to claim 1, wherein in the step of providing a substrate, a gate structure is formed on the substrate, and active drain doped layers are formed in the substrate on both sides of the gate structure;
in the step of forming a mask opening penetrating through the mask layer in the mask layer, the mask opening is formed above the gate structure and/or above the source-drain doped layer;
etching the dielectric layer along the mask opening, and forming the groove, wherein the groove comprises: a gate plug trench penetrating through the dielectric layer at the top of the gate structure and exposing the top of the gate structure, and/or a source drain plug trench penetrating through the dielectric layer at the top of the source drain doping layer and exposing the top of the source drain doping layer;
in the step of forming the interconnection structure, the interconnection structure includes; and the gate plug is positioned in the gate plug groove and/or the source and drain plug is positioned in the source and drain plug groove.
10. The method of forming a semiconductor device of claim 9, wherein in the step of providing a substrate, the dielectric layer comprises a fill layer, and a planarization layer on the fill layer, a top of the fill layer being higher than a top of the gate structure.
11. The method of forming a semiconductor device of claim 10, wherein the material of the fill layer comprises a high density plasma dielectric material; the material of the flat layer comprises tetraethyl orthosilicate.
12. The method of forming a semiconductor device of claim 1, wherein the material of the interconnect structure comprises tungsten, cobalt, or ruthenium.
13. The method of forming a semiconductor device of claim 1, wherein in the step of etching the dielectric layer along the mask opening to form a trench through the dielectric layer, an aspect ratio of the trench is greater than or equal to 5:1.
CN202210461336.2A 2022-04-28 2022-04-28 Method for forming semiconductor device Pending CN117012704A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210461336.2A CN117012704A (en) 2022-04-28 2022-04-28 Method for forming semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210461336.2A CN117012704A (en) 2022-04-28 2022-04-28 Method for forming semiconductor device

Publications (1)

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CN117012704A true CN117012704A (en) 2023-11-07

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Country Status (1)

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