CN117012714A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN117012714A
CN117012714A CN202210452405.3A CN202210452405A CN117012714A CN 117012714 A CN117012714 A CN 117012714A CN 202210452405 A CN202210452405 A CN 202210452405A CN 117012714 A CN117012714 A CN 117012714A
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CN
China
Prior art keywords
source
gate
layer
forming
drain
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CN202210452405.3A
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Chinese (zh)
Inventor
王彦
邱晶
顾飞丹
涂武涛
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210452405.3A priority Critical patent/CN117012714A/en
Publication of CN117012714A publication Critical patent/CN117012714A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate; forming a gate structure, a source drain region, a source drain contact layer and a first dielectric layer, wherein the gate structure, the source drain region, the source drain contact layer and the first dielectric layer are positioned on a substrate, the first dielectric layer exposes the top surfaces of the gate structures and the source drain contact layers, and the top surfaces of the source drain contact layers are higher than the top surfaces of the gate structures; forming an etching stop layer covering each gate structure and each source-drain contact layer, wherein the thickness of the etching stop layer on the gate structure is the same as that of the etching stop layer on the source-drain contact layer; forming a second dielectric layer on the etching stop layer; etching the second dielectric layer to form a connecting through hole crossing part of the grid structure and part of the source-drain contact layer, wherein the connecting through hole exposes the surface of the etching stop layer; etching the etching stop layer under the connecting through hole until the grid structure and the source-drain contact layer are exposed; a connection plug is formed in the connection via. The method for forming the semiconductor structure reduces the defects of the device structure and improves the performance of the device.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure.
Background
With the development of semiconductor technology, the size of semiconductor devices is continuously reduced, and the design of three-dimensional structures such as Fin field effect transistors (Fin FETs) is a focus of attention in the art. A fin field effect transistor generally has a plurality of fins extending vertically upward from a substrate, channels of the fin field effect transistor being formed in the fins, a gate structure being formed on the fins, and active and drain regions being formed in the fins on both sides of the gate structure.
In a finfet, a Gate Contact (Gate Contact) is located on the Gate structure to control source to drain current and is connected to an upper plug. Typically, the gate contact is located outside the active area of the transistor, requiring additional space.
In recent years, the industry has achieved significant savings in operating area by placing the gate contact layer directly over the active area of the transistor by the method of COAG (Contact Over Active Gate).
However, in the prior art, defects are easily introduced during the process of forming the gate contact layer, resulting in poor device performance.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure, which reduces defects generated in the process of forming a gate contact layer, thereby improving the performance of a device.
In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate; forming a plurality of gate structures on the substrate, source and drain regions on two sides of each gate structure, a plurality of source and drain contact layers on the source and drain regions, and a first dielectric layer on the substrate, wherein the first dielectric layer exposes top surfaces of each gate structure and each source and drain contact layer, and the top surfaces of the source and drain contact layers are higher than the top surfaces of the gate structures; forming an etching stop layer covering the top surfaces of the gate structures and the source-drain contact layers, wherein the thickness of the etching stop layer on the gate structures is the same as that of the etching stop layer on the source-drain contact layers; forming a second dielectric layer on the etching stop layer; etching the second dielectric layer, forming a connecting through hole crossing part of the grid structure and part of the source-drain contact layer in the second dielectric layer, wherein the connecting through hole comprises a first sub through hole and a second sub through hole which are mutually communicated, the first sub through hole is positioned on part of the grid structure, the second sub through hole is positioned on part of the source-drain contact layer, and the connecting through hole exposes out of the surface of the etching stop layer; etching the etching stop layer under the connecting through hole until the top surfaces of the grid structure and the source-drain contact layer are exposed; and forming a connection plug in the connection through hole.
Optionally, the method for forming the semiconductor structure further includes: forming a gate through hole positioned on part of the gate structure and a source drain through hole positioned on part of the source drain contact layer in the second dielectric layer; forming a gate plug in the gate through hole and a source-drain plug in the source-drain through hole.
Optionally, the source-drain through hole, the gate through hole and the connection through hole are formed simultaneously; the source-drain plug, the gate plug and the connecting plug are formed at the same time.
Optionally, the method for forming the source-drain plug, the gate plug and the connection plug includes: depositing a source drain plug material layer, a gate plug material layer and a connecting plug material layer in the source drain through hole, the gate through hole and the connecting through hole; and flattening the source-drain plug material layer, the grid plug material layer and the connecting plug material layer to form a source-drain plug, a grid plug and a connecting plug.
Optionally, the deposition process of the source-drain plug material layer comprises a chemical vapor deposition process; the deposition process of the gate plug material layer comprises a chemical vapor deposition process; the deposition process of the connecting plug material layer comprises a chemical vapor deposition process.
Optionally, after forming the gate plug and the connection plug, the source-drain via is formed.
Optionally, the method for forming the source-drain plug, the gate plug and the connection plug includes: forming a grid through hole and a connecting through hole in the second dielectric layer; depositing a gate plug material layer and a connection plug material layer in the gate through holes and the connection through holes; flattening the gate plug material layer and the connecting plug material layer to form a gate plug and a connecting plug; after forming the gate plug and the connecting plug, forming source and drain through holes in the second dielectric layer; depositing a source-drain plug material layer in the source-drain through hole; and flattening the source-drain plug material layer to form a source-drain plug.
Optionally, the material of the source drain plug material layer includes tungsten.
Optionally, the deposition process of the source drain plug material layer comprises a selective tungsten deposition process.
Optionally, after forming the source-drain plug and the connection plug, the gate via is formed.
Optionally, the method for forming the gate structure, the source drain region, the source drain contact layer and the first dielectric layer includes: forming a gate structure on the substrate, source and drain regions on two sides of the gate structure, and an initial first dielectric layer surrounding the gate structure; forming a source-drain contact layer positioned on the surface of the source-drain region in the initial first dielectric layer; and thinning the initial first dielectric layer until the top surfaces of the gate structure and the source-drain contact layer are exposed, so as to form the first dielectric layer.
Optionally, the first dielectric layer is partially located between the gate structure and the source-drain contact layer, and a top surface of the first dielectric layer is lower than a top surface of the gate structure, so that a gap located on the first dielectric layer is located between the gate structure and the source-drain contact layer.
Optionally, after the etching stop layer is formed, the gap is closed, so as to form a cavity layer between the gate structure and the source-drain contact layer.
Optionally, the thickness of the etching stop layer ranges from 100 angstroms to 200 angstroms.
Optionally, the material of the source-drain contact layer includes cobalt.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the etching stop layers and the second dielectric layers which cover the top surfaces of the gate structures and the source-drain contact layers are formed, so that in the process of forming the connecting through holes which cross part of the gate structures and part of the source-drain contact layers, the etching processes of the second dielectric layers on the gate structures and the source-drain contact layers can be stopped on the etching stop layers, the process window is larger, and the additional damage to the source-drain electric connection layers caused by the difference of the heights of the gate structures and the source-drain contact layers is avoided. Meanwhile, the gate structure and the structure on the source-drain contact layer are the same and are both composed of the etching stop layer and the second dielectric layer, so that in the subsequent process of forming the connecting through hole, the etching process of the second dielectric layer on the gate structure and the source-drain contact layer is uniform, and the etching damage to the source-drain connecting layer is reduced. In addition, the thickness of the etching stop layer on the gate structure is the same as that of the etching stop layer on the source-drain contact layer, so that the same etching degree of the etching stop layer on the gate structure and the etching stop layer on the source-drain contact layer can be ensured in the subsequent etching process of continuing to etch the etching stop layer, the problem of local over etching is avoided, the damage to the source-drain contact layer is reduced, the structural defect is reduced, the stability of a device is improved, and the performance of the device is improved.
Further, the method of forming a semiconductor structure further includes forming a cavity layer between the gate structure and the source-drain contact layer. The cavity layer has a smaller dielectric constant, so that the cavity layer is positioned between the gate structure and the source-drain contact layer, and parasitic capacitance between the gate structure and the source-drain contact layer can be well reduced, thereby improving RC delay.
Drawings
Fig. 1-3 are schematic cross-sectional views of a semiconductor structure formation process;
fig. 4 to 12 are schematic structural views of a forming process of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background art, in the prior art, defects are easily introduced during the process of forming the gate contact layer, resulting in poor device performance.
Fig. 1-3 are cross-sectional views of a semiconductor structure formation process.
Referring to fig. 1, a substrate 100 is provided; forming a plurality of gate structures 101 on the substrate 100, source and drain regions 102 on two sides of each gate structure 101, a plurality of source and drain contact layers 104 on the source and drain regions 102, and a first dielectric layer 103 on the substrate 100; forming an etching stop layer 105 on the top surface of the source-drain contact layer 104 and the first dielectric layer 103; a second dielectric layer 106 is formed on the etch stop layer 105.
The etch stop layer 105 is used to ensure an etch stop of the via hole on the source drain contact layer 104.
The material of the source-drain contact layer 104 includes cobalt.
Referring to fig. 2, the second dielectric layer 106, the etching stop layer 105 and the first dielectric layer 103 are etched to form a gate via 111 on a portion of the gate structure 101 and a connection via 110 crossing a portion of the gate structure 101 and a portion of the source drain contact layer 104, wherein the gate via 111 exposes the surface of the gate structure 101, and the connection via 110 exposes the surface of the gate structure 101 and the source drain contact layer 104.
Referring to fig. 3, a gate plug 121 and a connection plug 120 are formed in the gate via 111 and the connection via 110.
Since the source-drain contact layer 104 is higher than the gate structure 101, the thickness of the source-drain contact layer 104 to be etched is smaller than the thickness of the gate structure 101 to be etched in the process of simultaneously forming the gate via 111 and the connection via 110, and in addition, since the gate structure 101 is lower, the etching stop layer 105 needs to be completely etched in the process of etching the structure on the surface of the gate structure 101, so that the etching stop layer 105 on the surface of the source-drain contact layer 104 is also etched through, and then the top surface of the source-drain contact layer 104 is easily damaged (as shown at a in fig. 2), causing cobalt deficiency and cobalt pollution, thereby introducing defects and degrading the device performance.
In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, by forming an etching stop layer covering top surfaces of each gate structure and each source drain contact layer, and a second dielectric layer on the etching stop layer, so that in a process of subsequently forming a connection via hole crossing a portion of the gate structure and a portion of the source drain contact layer, even though heights of the gate structure and the source drain contact layer are different, a process of etching the second dielectric layer can be relatively uniform, and a process of etching the second dielectric layer can be stopped on the etching stop layer. In addition, the thickness of the formed etching stop layer on the grid structure is the same as that of the formed etching stop layer on the source-drain contact layer, so that the problem of partial over etching is avoided in the subsequent etching process of continuing to etch the etching stop layer, the additional damage to the source-drain contact layer is avoided, the structural defect is reduced, the stability of a device is improved, and the performance of the device is improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 12 are schematic structural views of a forming process of a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided; a plurality of gate structures 202 are formed on the substrate 200, source and drain regions 201 are formed on both sides of each gate structure 202, and an initial first dielectric layer 205 surrounds the gate structures 202.
The substrate 200 includes a base (not shown), and a number of fin structures (not shown) located on the base. Each of the gate structures 202 spans a top portion and a portion of a sidewall surface of the fin structure.
The material of the substrate 200 includes silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like. Specifically, in this embodiment, the material of the substrate 200 is silicon.
In this embodiment, the surface of the gate structure 202 further has a sidewall structure (not labeled) for protecting the gate structure 202, where the sidewall structure includes a first sidewall 203 and a second sidewall 204 located on the surface of the first sidewall 203, and the second sidewall 204 is further located on the surface of the substrate 200.
Specifically, the material of the first side wall 203 includes silicon oxide; the material of the second sidewall 204 includes silicon nitride.
In this embodiment, the method for forming the gate structure 202, the source drain region 201, the sidewall structure, and the initial first dielectric layer 205 includes: forming a dummy gate (not shown) on the substrate 200; forming source and drain regions 201 in the substrate 200 at both sides of the dummy gate; forming a side wall material layer (not shown) on the side wall and the top surface of the pseudo gate; forming a first initial dielectric material layer (not shown) on the substrate 200 to surround the dummy gate and the sidewall material layer; removing the dummy gate to form a gate opening; depositing an initial gate (not shown) within the gate opening; flattening the initial gate and the sidewall material layer to form a gate structure 202 and a sidewall structure; a second initial layer of dielectric material (not shown) continues to be deposited over the first initial layer of dielectric material, the first initial layer of dielectric material and the second initial layer of dielectric material constituting an initial first layer of dielectric 205.
In this embodiment, the top surface of the initial first dielectric layer 205 is higher than the top surface of the gate structure 202.
In this embodiment, the material of the initial first dielectric layer 205 includes silicon oxide.
Referring to fig. 5, a source-drain contact layer 207 is formed on the surface of the source-drain region 201 in the initial first dielectric layer 205, and the top surface of the source-drain contact layer 207 is higher than the top surface of the gate structure 202.
The source/drain contact layer 207 electrically connects the source/drain region 201 and an upper plug (not shown).
In this embodiment, the surface of the source-drain contact layer 207 has a contact sidewall 208, and the contact sidewall 208 is used to control the height of the source-drain contact layer 207.
In this embodiment, the initial first dielectric layer 205, the source-drain contact layer 207 and the contact sidewall 208 have the same height.
Specifically, the method for forming the source-drain contact layer 207 and the contact sidewall 208 includes: forming a first via (not shown) in the initial first dielectric layer 205, where the first via exposes the surface of the source drain region 201; depositing a side wall material layer (not shown) on the side wall of the first through hole; depositing a source-drain contact material layer (not shown) within the first via; and flattening the side wall material layer and the source and drain contact material layer until the surface of the initial first dielectric layer 205 is exposed, so as to form a source and drain contact layer 207 and a contact side wall 208.
In this embodiment, the material of the contact sidewall 208 includes silicon nitride.
In this embodiment, the material of the source-drain contact layer 207 includes cobalt.
Referring to fig. 6, the initial first dielectric layer 205 is thinned until the top surfaces of the gate structure 202 and the source-drain contact layer 207 are exposed, so as to form a first dielectric layer 206.
The effect of the initial first dielectric layer 205 is to expose the top of the gate structure 202 and the source drain contact layer 207, thereby facilitating the subsequent formation of an etch stop layer on the surfaces of the gate structure 202 and the source drain contact layer 207.
The first dielectric layer 206 is partially between the gate structure 202 and the source drain contact layer 207, and a top surface of the first dielectric layer 206 between the gate structure 202 and the source drain contact layer 207 is lower than a top surface of the gate structure 202, such that a gap 260 is provided between the gate structure 202 and the source drain contact layer 207 on the first dielectric layer 206. The void 260 is formed during the thinning process of the initial first dielectric layer 205.
Since the void 260 provides space for a subsequently formed cavity layer, it is advantageous to reduce parasitic capacitance between the gate structure 202 and the source-drain contact layer 207.
In this embodiment, the process of thinning the initial first dielectric layer 205 includes a dry etching process.
Referring to fig. 7, an etch stop layer 210 is formed to cover the top surfaces of each of the gate structures 202 and each of the source-drain contact layers 207, wherein the thickness of the etch stop layer 210 on the gate structures 202 is the same as the thickness on the source-drain contact layers 207; a second dielectric layer 220 is formed over the etch stop layer 210.
Since the etching stop layer 210 and the second dielectric layer 220 are formed to cover the top surfaces of the gate structures 202 and the source-drain contact layers 207, in the subsequent process of forming the connection via hole crossing part of the gate structures 202 and part of the source-drain contact layers 207, the existence of the etching stop layer 210 can stop the etching process of the second dielectric layer 220 on the gate structures 202 and the source-drain contact layers 207 on the etching stop layer 210, so that the process window is larger, the etching uniformity is better, and the additional damage to the source-drain connection layers due to the difference in the heights of the gate structures 202 and the source-drain contact layers 207 is avoided.
In addition, since the thickness of the etching stop layer 210 on the gate structure 202 is the same as the thickness of the etching stop layer 210 on the source-drain contact layer 207, in the subsequent etching process of continuing to etch the etching stop layer 210, the etching degree of the etching stop layer 210 on the gate structure 202 and the etching stop layer 207 can be ensured to be the same, so that the problem of local over etching is avoided, the damage to the source-drain contact layer 207 is reduced, the structural defect is reduced, the stability of the device is improved, and the performance of the device is improved.
In this embodiment, the thickness of the etching stop layer 210 ranges from 100 a to 200 a, so that the source-drain contact layer 207 can be effectively protected from damage during the subsequent formation of the connection via.
In addition, after the etch stop layer 210 is formed, the void 260 is closed to form a cavity layer 250 between the gate structure 202 and the source-drain contact layer 207.
Since the cavity layer 250 is sealed with air, the dielectric constant of the cavity layer 250 is small, and therefore, the cavity layer is located between the gate structure 202 and the source-drain contact layer 207, parasitic capacitance between the gate structure 202 and the source-drain contact layer 207 can be well reduced, and RC delay can be improved.
In this embodiment, the material of the etching stop layer 210 includes silicon nitride.
In this embodiment, the method for forming the etching stop layer 210 includes a non-orthographic deposition process. The non-orthographic deposition process may directly seal the void 260 without filling the void 260, thereby forming the cavity layer 250.
In this embodiment, the material of the second dielectric layer 220 includes silicon oxide.
Referring to fig. 8 to 10, fig. 8 is a schematic cross-sectional view along AA 'of fig. 10, fig. 9 is a schematic cross-sectional view along BB' of fig. 10, and fig. 10 is a top view along P of fig. 8 and 9.
After the second dielectric layer 220 is formed, the second dielectric layer 220 is etched, a connection via 221 crossing a portion of the gate structure 202 and a portion of the source-drain contact layer 207 is formed in the second dielectric layer 220, the connection via 221 includes a first sub-via (not labeled) and a second sub-via (not labeled) that are mutually penetrated, the first sub-via is located on a portion of the gate structure 202, the second sub-via is located on a portion of the source-drain contact layer 207, and the connection via 221 exposes a surface of the etching stop layer 210.
The connection via 221 provides a space for a connection plug to be formed later.
Since the etching stop layer 210 and the second dielectric layer 220 are formed to cover the top surfaces of the gate structures 202 and the source-drain contact layers 207, during the formation of the connection via 221 crossing over a portion of the gate structures 202 and a portion of the source-drain contact layers 207, the etching process of the second dielectric layer 220 on the gate structures 202 and the source-drain contact layers 207 can be stopped on the etching stop layer 210, so that the process window is larger, and additional damage to the source-drain connection layers due to the difference in the heights of the gate structures 202 and the source-drain contact layers 207 is avoided. Meanwhile, since the structures on the gate structure 202 and the source-drain contact layer 207 are the same and are both composed of the etching stop layer 210 and the second dielectric layer 220, in the subsequent process of forming the connection via 221, the etching process of the second dielectric layer 220 on the gate structure 202 and the source-drain contact layer 207 can be relatively uniform, and the etching damage to the source-drain connection layer is reduced, thereby reducing structural defects, improving the stability of the device and improving the performance of the device.
In this embodiment, the method for forming the semiconductor structure further includes, while forming the connection via 221: a gate via 222 is formed in the second dielectric layer 220 over a portion of the gate structure 202 and a source drain via 223 is formed over a portion of the source drain contact layer 207. The gate via 222 and the source drain via 223 provide space for gate plugs and source drain plugs to be formed later.
Note that, for ease of understanding, the second dielectric layer 220, the first dielectric layer 206, and the etch stop layer 210 are omitted in fig. 10, and only coverage areas of the substrate 200, the gate structure 202, the source-drain contact layer 207, and the connection via 221, the gate via 222, and the source-drain via 223 are illustrated.
With continued reference to fig. 10, the substrate 200 includes a base 211 and a plurality of fin structures 212 disposed on the base 211. Each of the gate structures 202 spans a top portion and a portion of a sidewall surface of the fin structure 212.
In this embodiment, the layout of the connection via 221 and the gate via 222 adopts a structure of COAG (Contact Over Active Gate), that is, the connection via 221 and the gate via 222 are located directly above the gate structure 202 covered by the transistor active area, so that a large amount of working area is saved and the integration level of the semiconductor device is improved.
Specifically, the method for forming the connection via 221, the gate via 222, and the source drain via 223 includes: forming a patterned layer (not shown) on the second dielectric layer 220, wherein the patterned layer exposes a portion of the gate structure 202 and the source drain contact layer 207 surface; and etching the second dielectric layer 220 by using the patterned layer as a mask until the surface of the etching stop layer 210 is exposed, so as to form a connection via 221, a gate via 222 and a source drain via 223 in the second dielectric layer 220.
In this embodiment, the process of etching the second dielectric layer 220 includes a dry etching process.
Referring to fig. 11 and 12, fig. 11 coincides with the view direction of fig. 8, and fig. 12 coincides with the view direction of fig. 9.
Etching the etch stop layer 210 under the connection via 221, the gate via 222, and the source drain via 223 until the top surfaces of the gate structure 202 and the source drain contact layer 207 are exposed; a connection plug 241 is formed in the connection via 221, a gate plug 242 is formed in the gate via 222, and a source/drain plug 243 is formed in the source/drain via 223.
Since the thickness of the etching stop layer 210 on the gate structure 202 is the same as the thickness on the source-drain contact layer 207, in the process of continuing to etch the etching stop layer 210 until the gate structure 202 and the source-drain contact layer 207 are exposed, the etching degree of the etching stop layer 210 on the gate structure 202 and the source-drain contact layer 207 can be ensured to be the same, so that the problem of local over-etching is avoided, the damage to the source-drain contact layer 207 is reduced, the structural defect is reduced, the stability of the device is improved, and the performance of the device is improved.
In this embodiment, the source and drain plugs 243, the gate plugs 242, and the connection plugs 241 are formed simultaneously.
Specifically, the method for forming the source-drain plug 243, the gate plug 242 and the connection plug 241 includes: depositing a source-drain plug material layer (not shown), a gate plug material layer (not shown), and a connection plug material layer (not shown) within the source-drain via 223, the gate via 222, and the connection via 221; and flattening the source/drain plug material layer, the gate plug material layer and the connecting plug material layer until the surface of the second dielectric layer 220 is exposed, so as to form a source/drain plug 243, a gate plug 242 and a connecting plug 241.
The source-drain plugs 243 connect the source-drain contact layer 207 to an upper electrical interconnect structure (not shown); the gate plugs 242 connect the gate structures 202 to upper level electrical interconnect structures; the connection plug 241 connects the gate structure 202 to the source-drain contact layer 207 so that both have the same potential while connecting both to an upper electrical interconnect structure.
In this embodiment, the deposition process of the source-drain plug material layer includes a chemical vapor deposition process; the deposition process of the gate plug material layer comprises a chemical vapor deposition process; the deposition process of the connecting plug material layer comprises a chemical vapor deposition process.
In this embodiment, the materials of the source drain plug 243, the gate plug 242, and the connection plug 241 include tungsten.
In another embodiment, the source-drain vias are formed after forming the gate plugs and the connection plugs.
Specifically, the method for forming the connection through hole, the gate through hole, the source drain plug, the gate plug and the connection plug comprises the following steps: forming a grid through hole and a connecting through hole in the second dielectric layer; depositing a gate plug material layer and a connection plug material layer in the gate through holes and the connection through holes; flattening the gate plug material layer and the connecting plug material layer to form a gate plug and a connecting plug; forming a third dielectric layer on the gate plug and the connection plug after forming the gate plug and the connection plug; forming source and drain through holes in the third dielectric layer and the second dielectric layer, wherein the source and drain through holes expose the surface of the source and drain contact layer; depositing a source-drain plug material layer in the source-drain through hole; and flattening the source-drain plug material layer to form a source-drain plug.
In other embodiments, the third dielectric layer may not be formed, and the source-drain vias in the second dielectric layer may be directly formed after the gate plugs and the connection plugs are formed.
In this embodiment, the material of the source drain plug material layer includes tungsten.
The deposition process of the source drain plug material layer comprises a selective tungsten deposition process. The selective tungsten deposition process can enable the electric contact effect between the formed source and drain plugs and other structures to be better, so that the performance of the device is optimized.
In another embodiment, the gate via is formed after the source-drain plug and the connection plug are formed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of gate structures on the substrate, source and drain regions on two sides of each gate structure, a plurality of source and drain contact layers on the source and drain regions, and a first dielectric layer on the substrate, wherein the first dielectric layer exposes top surfaces of each gate structure and each source and drain contact layer, and the top surfaces of the source and drain contact layers are higher than the top surfaces of the gate structures;
forming an etching stop layer covering the top surfaces of the gate structures and the source-drain contact layers, wherein the thickness of the etching stop layer on the gate structures is the same as that of the etching stop layer on the source-drain contact layers;
forming a second dielectric layer on the etching stop layer;
etching the second dielectric layer, forming a connecting through hole crossing part of the grid structure and part of the source-drain contact layer in the second dielectric layer, wherein the connecting through hole comprises a first sub through hole and a second sub through hole which are mutually communicated, the first sub through hole is positioned on part of the grid structure, the second sub through hole is positioned on part of the source-drain contact layer, and the connecting through hole exposes out of the surface of the etching stop layer;
etching the etching stop layer under the connecting through hole until the top surfaces of the grid structure and the source-drain contact layer are exposed;
and forming a connection plug in the connection through hole.
2. The method of forming a semiconductor structure of claim 1, further comprising: forming a gate through hole positioned on part of the gate structure and a source drain through hole positioned on part of the source drain contact layer in the second dielectric layer; forming a gate plug in the gate through hole and a source-drain plug in the source-drain through hole.
3. The method of forming a semiconductor structure of claim 2, wherein the source-drain via, gate via, and connection via are formed simultaneously; the source-drain plug, the gate plug and the connecting plug are formed at the same time.
4. The method of forming a semiconductor structure of claim 3, wherein forming the source drain plug, gate plug and connection plug comprises: depositing a source drain plug material layer, a gate plug material layer and a connecting plug material layer in the source drain through hole, the gate through hole and the connecting through hole; and flattening the source-drain plug material layer, the grid plug material layer and the connecting plug material layer to form a source-drain plug, a grid plug and a connecting plug.
5. The method of forming a semiconductor structure of claim 4, wherein the deposition process of the source drain plug material layer comprises a chemical vapor deposition process; the deposition process of the gate plug material layer comprises a chemical vapor deposition process; the deposition process of the connecting plug material layer comprises a chemical vapor deposition process.
6. The method of forming a semiconductor structure of claim 2, wherein the source-drain vias are formed after forming gate plugs and connecting plugs.
7. The method of forming a semiconductor structure of claim 6, wherein forming the source drain plug, gate plug and connection plug comprises: forming a grid through hole and a connecting through hole in the second dielectric layer; depositing a gate plug material layer and a connection plug material layer in the gate through holes and the connection through holes; flattening the gate plug material layer and the connecting plug material layer to form a gate plug and a connecting plug; after forming the gate plug and the connecting plug, forming source and drain through holes in the second dielectric layer; depositing a source-drain plug material layer in the source-drain through hole; and flattening the source-drain plug material layer to form a source-drain plug.
8. The method of forming a semiconductor structure of claim 7, wherein a material of said source drain plug material layer comprises tungsten.
9. The method of forming a semiconductor structure of claim 8, wherein the deposition process of the source drain plug material layer comprises a selective tungsten deposition process.
10. The method of forming a semiconductor structure of claim 2, wherein the gate via is formed after forming a source-drain plug and a connection plug.
11. The method of forming a semiconductor structure of claim 1, wherein forming the gate structure, source drain regions, source drain contact layers, and first dielectric layer comprises: forming a gate structure on the substrate, source and drain regions on two sides of the gate structure, and an initial first dielectric layer surrounding the gate structure; forming a source-drain contact layer positioned on the surface of the source-drain region in the initial first dielectric layer; and thinning the initial first dielectric layer until the top surfaces of the gate structure and the source-drain contact layer are exposed, so as to form the first dielectric layer.
12. The method of forming a semiconductor structure of claim 1, wherein the first dielectric layer is partially between the gate structure and the source drain contact layer and a top surface of the first dielectric layer is lower than a top surface of the gate structure such that there is a void between the gate structure and the source drain contact layer that is located on the first dielectric layer.
13. The method of forming a semiconductor structure of claim 12, wherein after forming the etch stop layer, the void is closed to form a cavity layer between the gate structure and the source drain contact layer.
14. The method of claim 1, wherein the etch stop layer has a thickness in the range of 100 a to 200 a.
15. The method of forming a semiconductor structure of claim 1, wherein a material of said source drain contact layer comprises cobalt.
CN202210452405.3A 2022-04-27 2022-04-27 Method for forming semiconductor structure Pending CN117012714A (en)

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