CN116995632B - PVT insensitive current limiting protection circuit - Google Patents
PVT insensitive current limiting protection circuit Download PDFInfo
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- CN116995632B CN116995632B CN202311267231.4A CN202311267231A CN116995632B CN 116995632 B CN116995632 B CN 116995632B CN 202311267231 A CN202311267231 A CN 202311267231A CN 116995632 B CN116995632 B CN 116995632B
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- 238000005070 sampling Methods 0.000 claims abstract description 41
- 239000003990 capacitor Substances 0.000 claims description 68
- 238000001514 detection method Methods 0.000 abstract description 23
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000001737 promoting effect Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
Abstract
The invention discloses a PVT insensitive current limiting protection circuit, comprising: the power tube M1, the sampling tube M2, the clamping module, the clock generation module, the reference voltage generation module and the current limiting control module, wherein a source electrode of the power tube M1 and a source electrode of the sampling tube M2 are connected with a power supply voltage VIN, a drain electrode of the power tube M1 and a drain electrode of the sampling tube M2 are connected with an input end of the clamping module, and a grid electrode of the power tube M1 and a grid electrode of the sampling tube M2 are connected with an output end of the current limiting control module; the clamping module is connected with the clock generation module, and the output end of the clamping module and the output end of the reference voltage generation module are connected with the input end of the current-limiting control module; the clamping module consists of an operational amplifier negative feedback circuit and a self-zeroing stable operational amplifier auxiliary loop which are connected. The current limiting protection circuit can reduce input offset voltage, so that high-precision detection current insensitive to PVT is obtained.
Description
Technical Field
The invention belongs to the technical field of power management integrated circuits, and particularly relates to a PVT insensitive current limiting protection circuit.
Background
The load switch is widely applied to intelligent electric meters, industrial automatic control systems and portable electronic products, and plays a role in switching on and off a circuit. When the load of the current-limiting switch suddenly becomes smaller or short-circuits, the output current increases sharply, which can cause damage to the power tube, so that the current-limiting circuit is required to limit the output current within a reasonable range.
With the continuous development and progress of technology, many portable electronic products have higher and higher requirements on the precision of current limiting, for example: smart phones, cameras, etc. The existing technology for improving the precision of the current-limiting protection circuit is to make the drain voltages of the power tube and the sampling transistor equal by using an operational amplifier and an adjusting tube clamp, so as to improve the current-limiting precision, however, the input offset voltage of the operational amplifier changes along with the change of external environments such as power supply voltage, input common mode voltage, process, temperature and the like, and cannot be corrected by trimming; and because of the existence of offset voltage, the source-drain voltage drops of the power tube and the sampling tube are unequal, the inconsistency of the source-drain voltage can influence the precision of the sampling current, and the sampling precision is seriously influenced when the power tube and the sampling tube are in a linear region, thereby influencing the current limiting precision.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides the current-limiting protection circuit insensitive to PVT, which is insensitive to power supply voltage, input common-mode voltage and process, and greatly improves the current-limiting precision of the current-limiting protection circuit.
In order to achieve the technical purpose, the invention adopts the following technical scheme: a PVT insensitive current limiting protection circuit comprising: the power tube M1, the sampling tube M2, the clamping module, the clock generation module, the reference voltage generation module and the current limiting control module, wherein a source electrode of the power tube M1 and a source electrode of the sampling tube M2 are connected with a power supply voltage VIN, a drain electrode of the power tube M1 and a drain electrode of the sampling tube M2 are connected with an input end of the clamping module, and a grid electrode of the power tube M1 and a grid electrode of the sampling tube M2 are connected with an output end of the current limiting control module; the clamping module is connected with the clock generation module, and the output end of the clamping module and the output end of the reference voltage generation module are both connected with the input end of the current-limiting control module;
the clamping module consists of a connected operational amplifier negative feedback circuit and a self-zeroing stable operational amplifier auxiliary loop, the input end of the operational amplifier negative feedback circuit is respectively connected with the drain electrode of the power tube M1 and the drain electrode of the sampling tube M2, and the output end of the operational amplifier negative feedback circuit is connected with the input end of the current-limiting control module; and the self-zeroing stable operational amplifier auxiliary loop is connected with the clock generation module.
Further, the operational amplifier negative feedback circuit includes: the output end of the first transconductance amplifier G1 is connected with one end of the first resistor R1 and the grid electrode of the first switching tube M3 respectively, the other end of the first resistor R1 is grounded, the source electrode of the first switching tube M3 is connected with the inverting input end of the first transconductance amplifier G1, and the drain electrode of the first switching tube M3 is connected with the input end of the current-limiting control module.
Further, the non-inverting input end of the first transconductance amplifier G1 is connected with the drain electrode of the power tube M1, and the inverting input end of the first transconductance amplifier G1 is connected with the drain electrode of the sampling tube M2.
Further, the self-zeroing stable op-amp auxiliary loop comprises: the second transconductance amplifier G2, the first operational amplifier A1, the second resistor R2, the third resistor R3, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8, one end of the second resistor R2 is connected with a positive input end of the first transconductance amplifier G1, the other end of the second resistor R2 is respectively connected with an upper polar plate of the first capacitor C1 and one end of the first switch S1, the other end of the first switch S1 is respectively connected with one end of the third switch S3 and a left polar plate of the second capacitor C2, the other end of the third switch S3 is connected with a positive input end of the first transconductance amplifier G1, the other end of the second capacitor C2 is respectively connected with a positive input polar plate of the fifth switch C5 and the other end of the fourth switch S5, the other end of the fourth switch C5 is respectively connected with an inverting polar plate of the fourth capacitor C5, the fourth output polar plate of the seventh switch C5 is respectively connected with the positive input end of the fourth switch C1, the fourth capacitor C2 is connected with the positive polar plate of the fourth input end of the fourth switch C1, the fourth capacitor C2 is connected with the fourth polar plate is connected with the positive polar plate of the fourth polar plate is respectively; one end of the third resistor R3 is connected with the inverting input end of the first transconductance amplifier G1, the other end of the third resistor R3 is connected with the lower electrode plate of the first capacitor C1 and one end of the second switch S2, the other end of the second switch S2 is connected with one end of the fourth switch S4 and the left electrode plate of the third capacitor C3, the other end of the fourth switch S4 is connected with the non-inverting input end of the first transconductance amplifier G1, the right electrode plate of the third capacitor C3 is connected with the non-inverting input end of the first operational amplifier A1 and one end of the sixth switch S6, the inverting output end of the first operational amplifier A1 and the other end of the sixth switch S6 are connected with one end of the eighth switch S8, the other end of the eighth switch S8 is connected with the lower electrode plate of the fourth capacitor C4 and the upper electrode plate of the sixth capacitor C6 and the inverting input end of the second transconductance amplifier G2, and the lower electrode plate of the sixth capacitor C6 is grounded; the output end of the second transconductance amplifier G2 is connected with the output end of the first transconductance amplifier G1.
Further, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are all controlled by the control signals F1 and F2 output by the clock generating module, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are controlled by the control signal F1, and the first switch S1, the second switch S2, the seventh switch S7, and the eighth switch S8 are controlled by the control signal F2.
Further, the control signals F1 and F2 are square wave signals with the same frequency and different phases, and have one turn-on and one turn-off control in one control period, and the switch controlled by the control signal F1 is not turned on simultaneously with the switch controlled by the control signal F2.
Further, the current limiting control module includes: the non-inverting input end of the second operational amplifier A2 is respectively connected with one end of the fourth resistor R4 and the drain electrode of the first switching tube M3, and the other end of the fourth resistor R4 is grounded; the inverting input end of the second operational amplifier A2 is connected with the output end of the reference voltage generation module, and the output end of the second operational amplifier A2 is respectively connected with the grid electrode of the power tube M1 and the grid electrode of the sampling tube M2.
Further, the reference voltage generation module includes: the non-inverting input end of the third operational amplifier A3 is respectively connected with one end of the fifth resistor R5 and the drain electrode of the second switching tube M4, the other end of the fifth resistor R5 is respectively connected with the input end of the current-limiting control module and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded; the source of the second switching tube M4 is connected to the power voltage VIN, and the inverting input terminal of the third operational amplifier A3 receives the bandgap reference voltage VBG.
Further, the other end of the fifth resistor R5 is connected to the inverting input terminal of the second operational amplifier A2.
Compared with the prior art, the invention has the following beneficial effects: the clamping module in the PVT insensitive current limiting protection circuit adopts a framework of combining the operational amplifier negative feedback main loop and the self-zeroing stable operational amplifier auxiliary loop, the input offset voltage of the first operational amplifier caused by the external environment influences of common mode voltage, power supply voltage, process, temperature and the like is sampled in real time, the input offset voltage is reduced by hundreds of times, the reduced offset voltage is very small, the precision of sampling current is hardly influenced, and therefore the PVT insensitive high-precision detection current is obtained.
Drawings
FIG. 1 is a schematic diagram of a PVT insensitive current limiting protection circuit according to the present invention;
FIG. 2 is a schematic circuit diagram of a clamping module according to the present invention;
FIG. 3 is a schematic circuit diagram illustrating the connection of the current limit control module according to the present invention;
fig. 4 is a schematic circuit diagram of a reference voltage generating module according to the present invention.
Detailed Description
The technical scheme of the invention is further explained below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a PVT insensitive current limiting protection circuit according to the present invention, the current limiting protection circuit includes: the power tube M1, the sampling tube M2, the clamping module, the clock generation module, the reference voltage generation module and the current limiting control module are connected with the power voltage VIN at the source electrode of the power tube M1 and the source electrode of the sampling tube M2, and are used for receiving input signals; the drain electrode of the power tube M1 and the drain electrode of the sampling tube M2 are connected with the input end of the clamping module, the output current IOUT is provided through the drain end of the power tube M1, and the detection current ISEN is provided through the drain end of the sampling tube M2; the grid electrode of the power tube M1 and the grid electrode of the sampling tube M2 are connected with the output end of the current-limiting control module and are used for receiving a control signal VC output by the current-limiting control module; the clamping module is connected with the clock generation module, and the clock generation module is used for providing a clock signal for the clamping module; the output end of the clamping module and the output end of the reference voltage generating module are connected with the input end of the current limiting control module. The grid electrode of the power tube M1 is connected with the grid electrode of the sampling tube M2 and is used for sampling the output current of the power tube M1 in an equal proportion; the clamping module is used for accurately clamping the drain terminal voltage of the power tube M1 and the sampling tube M2 so as to obtain an accurate detection current ISEN; the reference voltage generation module is used for providing a reference voltage VREF which is insensitive to the process, the power supply voltage and the temperature and is generated by the band gap reference voltage; the current limiting control module converts the detection current ISEN into detection voltage VSEN and compares the detection voltage VSEN with reference voltage VREF, so that feedback adjustment of a control signal VC of the current limiting control module is realized, and the output current IOUT is controlled.
The clamping module consists of an operational amplifier negative feedback circuit and a self-zeroing stable operational amplifier auxiliary loop which are connected, wherein the input end of the operational amplifier negative feedback circuit is respectively connected with the drain electrode of the power tube M1 and the drain electrode of the sampling tube M2, and the output end of the operational amplifier negative feedback circuit is connected with the input end of the current limiting control module; the self-zeroing stable operational amplifier auxiliary loop is connected with the clock generation module. Because the clamping module adopts the combined framework of the operational amplifier feedback circuit and the self-zeroing operational amplifier auxiliary loop, the self-zeroing stable operational amplifier auxiliary loop can reduce the input offset voltage of the operational amplifier feedback circuit and also can eliminate the input offset voltage of the self-zeroing operational amplifier auxiliary loop, thereby realizing the PVT insensitive high-precision clamping function and promoting the power tube M1 and the sampling tube M2 to have consistent drain voltage so as to improve the sampling current precision and the current limiting precision.
As shown in fig. 2, the operational amplifier negative feedback circuit of the present invention includes: the output end of the first transconductance amplifier G1 is respectively connected with one end of the first resistor R1 and the grid electrode of the first switching tube M3, the other end of the first resistor R1 is grounded, the source electrode of the first switching tube M3 is connected with the inverting input end of the first transconductance amplifier G1, and the drain electrode of the first switching tube M3 is connected with the input end of the current limiting control module and used for providing detection current ISEN; the invention introduces a self-zeroing stable operational amplifier auxiliary loop on the basis that the positive input end of a first transconductance amplifier G1 is connected with the drain electrode of a power tube M1, the negative feedback circuit is used for clamping the voltage of the drain end of the power tube M1 and the drain end of the sampling tube M2 to cause clamping errors of the drain end of the power tube M1 and the drain end of the sampling tube M2, so that the precision of sampling current is reduced, and the current limiting precision is reduced, and the self-zeroing stable operational amplifier auxiliary loop comprises: the second transconductance amplifier G2, the first operational amplifier A1, the second resistor R2, the third resistor R3, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8, one end of the second resistor R2 is connected with a positive input end of the first transconductance amplifier G1, the other end of the second resistor R2 is respectively connected with an upper polar plate of the first capacitor C1 and one end of the first switch S1, the other end of the first switch S1 is respectively connected with one end of the third switch S3 and a left polar plate of the second capacitor C2, the other end of the third switch S3 is connected with a positive input end of the first transconductance amplifier G1, the other end of the second capacitor C2 is respectively connected with a positive input polar plate of the fifth switch C5 and the other end of the fourth switch S5, the other end of the fourth switch C5 is respectively connected with an inverting polar plate of the fourth capacitor C5, the fourth output polar plate of the seventh switch C5 is respectively connected with the positive input end of the fourth switch C1, the fourth capacitor C2 is connected with the positive polar plate of the fourth input end of the fourth switch C1, the fourth capacitor C2 is connected with the fourth polar plate is connected with the positive polar plate of the fourth polar plate is respectively; one end of the third resistor R3 is connected with the inverting input end of the first transconductance amplifier G1, the other end of the third resistor R3 is connected with the lower electrode plate of the first capacitor C1 and one end of the second switch S2, the other end of the second switch S2 is connected with one end of the fourth switch S4 and the left electrode plate of the third capacitor C3, the other end of the fourth switch S4 is connected with the non-inverting input end of the first transconductance amplifier G1, the right electrode plate of the third capacitor C3 is connected with the non-inverting input end of the first operational amplifier A1 and one end of the sixth switch S6, the inverting output end of the first operational amplifier A1 and the other end of the sixth switch S6 are connected with one end of the eighth switch S8, the other end of the eighth switch S8 is connected with the lower electrode plate of the fourth capacitor C4 and the upper electrode plate of the sixth capacitor C6 and the inverting input end of the second transconductance amplifier G2, and the lower electrode plate of the sixth capacitor C6 is grounded; the output end of the second transconductance amplifier G2 is connected with the output end of the first transconductance amplifier G1.
In the invention, the on-off of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 are controlled by control signals F1 and F2 output by a clock generation module, the third switch S3, the fourth switch S4, the fifth switch S5 and the sixth switch S6 are controlled by the control signal F1, and the first switch S1, the second switch S2, the seventh switch S7 and the eighth switch S8 are controlled by the control signal F2. The control signals F1 and F2 are square wave signals of the same frequency and different phases, and have one turn-on and one turn-off control in one control period, and the switch controlled by the control signal F1 is not turned on at the same time as the switch controlled by the control signal F2.
For convenience of description, a stage in which the switches S3, S4, S5, S6 controlled by the control signal F1 are turned on and the switches S1, S2, S7, S8 controlled by the control signal F2 are turned off is referred to as an F1 stage, and a stage in which the switches S3, S4, S5, S6 controlled by the control signal F1 are turned off and the switches S1, S2, S7, S8 controlled by the control signal F2 are turned on is referred to as an F2 stage. In the F1 stage, the left plates of the second capacitor C2 and the third capacitor C3 are reset to VOUT voltage, the voltage difference between the right plates of the second capacitor C2 and the third capacitor C3 is the output differential mode voltage VC of the first operational amplifier A1, and if the input offset voltage of the first operational amplifier A1 is Vos1 and the gain is a, (-vc+vos1) ×a=vc, the simplification is obtained: vc=vos1/(1+a), the differential mode voltage VC is stored in the form of charges on the right plates of the second capacitor C2 and the third capacitor C3; in the F2 stage, the input differential signal VOUT-VA reaches the left plates of the second capacitor C2 and the third capacitor C3 through the second resistor R2, the third resistor R3, the first switch S1, and the second switch S2, and since the right plates of the second capacitor C2 and the third capacitor C3 store the differential mode voltage VC for offset correction in the F1 stage, the differential output voltage of the first operational amplifier A1 can be calculated as:
VOUT,A1 = (VOUT - VA + Vos1 -VC)*A
substituting the differential mode voltage VC of the F1 stage to obtain:
VOUT,A1 = [VOUT - VA + Vos1/(1+A)]*A
thus, the equivalent input offset voltage is:
Vos,eff = Vos1/(1+A)
since the gain of the first operational amplifier A1 is large, the input offset voltage Vos1 is reduced to a small level, which is almost negligible. The differential output voltage VOUT of the first operational amplifier A1, the upper plates of the fifth capacitor C5 and the sixth capacitor C6 exist in the form of charges, and are used for continuously providing input for the second transconductance amplifier G2 during the stage F1; and the fourth capacitor C4 is a filter capacitor.
The input offset voltage of the first operational amplifier A1 can be basically eliminated through the switch switching schemes of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8, and meanwhile, the self-zeroing stable operational amplifier auxiliary loop amplifies the same input signal VOUT-VA as the first transconductance amplifier G1, so that the input signal VOUT-VA is amplified by the first transconductance amplifier G1 and the self-zeroing stable operational amplifier auxiliary loop simultaneously; the input offset voltage of the first transconductance amplifier G1 is amplified only by the first transconductance amplifier G1, and the self-zeroing stable operational amplifier auxiliary loop can reduce the input offset voltage of the first transconductance amplifier G1 to the valueWherein, the method comprises the steps of, wherein,is the transconductance of the first transconductance amplifier G1, A is the gain of the first operational amplifier A1, +.>Is the transconductance of the second transconductance amplifier G2,/>The input offset voltage of the first transconductance amplifier G1 is not added when the self-zeroing stable operational amplifier loop is not added, so that the input offset voltage is reduced by the addition of the self-zeroing stable operational amplifier auxiliary loop>Multiple times.
As shown in fig. 3, the current limiting control module in the present invention includes: the non-inverting input end of the second operational amplifier A2 is respectively connected with one end of the fourth resistor R4 and the drain electrode of the first switch tube M3, and is connected with the fourth resistor R4 through the second operational amplifier A2 to receive the detection current ISEN, and the other end of the fourth resistor R4 is grounded; the inverting input end of the second operational amplifier A2 is connected with the output end of the reference voltage generation module and is used for receiving the reference voltage VREF generated by the reference voltage generation module; the output end of the second operational amplifier A2 is respectively connected with the grid electrode of the power tube M1 and the grid electrode of the sampling tube M2. The detection current ISEN is converted into a detection voltage VSEN through a fourth resistor R4, when the output current IOUT of the power tube M1 is increased, the detection current ISEN and the detection voltage VSEN are increased simultaneously, and when the VSEN is greater than VREF, the second operational amplifier A2 increases the output control signal VC, so that the output current IOUT of the power tube M1 is reduced.
As shown in fig. 4, the reference voltage generating module in the present invention includes: the inverting input end of the third operational amplifier A3 receives the band gap reference voltage VBG, the non-inverting input end of the third operational amplifier A3 is respectively connected with one end of the fifth resistor R5 and the drain electrode of the second switching tube M4, the other end of the fifth resistor R5 is respectively connected with the input end of the current limiting control module and one end of the sixth resistor R6, the sixth resistor R6 is used for converting received reference current into reference voltage VREF, and the other end of the sixth resistor R6 is grounded; the source of the second switching tube M4 is connected to the power voltage VIN, and the other end of the fifth resistor R5 is connected to the inverting input terminal of the second operational amplifier A2. In the reference voltage generating module, the third operational amplifier A3, the second switching tube M4, the fifth resistor R5, and the sixth resistor R6 form a negative feedback circuit, and the non-inverting input terminal voltage VFB and the inverting input terminal voltage VBG of the third operational amplifier A3 are equal when stable, so that the reference current iref=vbg/(r5+r6) flowing through the resistor R5 and the resistor R6, and the output reference voltage vref=vbg×r6/(r5+r6).
In one embodiment of the present invention, the reference voltage VREF is further adjusted by adjusting the resistance value of the fifth resistor R5 or the resistance value of the sixth resistor R6.
The working principle of the PVT insensitive current limiting protection circuit is as follows:
the input offset voltage of the first operational amplifier A1 can be eliminated through the switch switching schemes of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8, and meanwhile, the self-zeroing stable operational amplifier auxiliary loop amplifies the same input signal VOUT-VA as the first transconductance amplifier G1, so that the input signal VOUT-VA is amplified by the first transconductance amplifier G1 and the self-zeroing stable operational amplifier auxiliary loop simultaneously; the input offset voltage of the first transconductance amplifier G1 is amplified only by the first transconductance amplifier G1, thereby obtaining that the input offset voltage of the first transconductance amplifier G1 is reducedThe input offset voltage close to 0 is multiplied and insensitive to PVT, so that the accurate clamping of the drain end of the power tube M1 and the drain end of the sampling tube M2 is realized, and the high-precision detection current is obtained:
ISEN = IOUT/R4
the detection current ISEN flows through the fourth resistor R4 through the first switching tube M3, and a detection voltage VSEN is generated at one end of the fourth resistor R4; the non-inverting input terminal of the second operational amplifier A2 receives the detection voltage VSEN, and the inverting input terminal receives the reference voltage VREF; when the detection current ISEN is smaller, the detection voltage VSEN is smaller than the reference voltage VREF, and at this time, the second operational amplifier A2 does not adjust the control signal VC; when the detection current ISEN increases to a value that is greater than the reference voltage VREF, the second operational amplifier A2 adjusts the control signal VC, pulls the control signal VC high, and reduces the detection current ISEN and the output current IOUT, at this time, the second operational amplifier A2 works in a negative feedback circuit, the detection voltage VSEN and the reference voltage VREF are equal, and VREF=ISEN×R0; the current limiting control module forms a negative feedback circuit, and vbg=vfb, and the fifth resistor R5 and the sixth resistor R6 form a voltage dividing network, so that the following can be obtained: vref=r6×vbg/(r6+r5), and it can be seen from the above that the output current iout=k×r6×vbg/[ r4× (r5+r6) ], where K is the ratio of the width to length ratio of the power tube M1 and the sampling tube M2, VBG is the bandgap reference voltage, it can be designed into a zero temperature coefficient, R4 does not introduce a temperature coefficient, and a high-precision current limiting value insensitive to PVT can be obtained by the size of the fourth resistor R4.
The PVT insensitive current limiting protection circuit adopts the operational amplifier negative feedback circuit and the self-zeroing stable operational amplifier auxiliary loop, so that the problem that the input offset voltage of the clamping operational amplifier changes along with the process, the power supply voltage and the temperature is solved, and the high-precision detection current is obtained.
The above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, and all technical solutions belonging to the concept of the present invention are within the scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (7)
1. A PVT insensitive current limiting protection circuit comprising: the power tube M1, the sampling tube M2, the clamping module, the clock generation module, the reference voltage generation module and the current limiting control module, wherein a source electrode of the power tube M1 and a source electrode of the sampling tube M2 are connected with a power supply voltage VIN, a drain electrode of the power tube M1 and a drain electrode of the sampling tube M2 are connected with an input end of the clamping module, and a grid electrode of the power tube M1 and a grid electrode of the sampling tube M2 are connected with an output end of the current limiting control module; the clamping module is connected with the clock generation module, and the output end of the clamping module and the output end of the reference voltage generation module are both connected with the input end of the current-limiting control module;
the clamping module consists of a connected operational amplifier negative feedback circuit and a self-zeroing stable operational amplifier auxiliary loop, the input end of the operational amplifier negative feedback circuit is respectively connected with the drain electrode of the power tube M1 and the drain electrode of the sampling tube M2, and the output end of the operational amplifier negative feedback circuit is connected with the input end of the current-limiting control module; the self-zeroing stable operational amplifier auxiliary loop is connected with the clock generation module;
the operational amplifier negative feedback circuit comprises: the output end of the first transconductance amplifier G1 is respectively connected with one end of the first resistor R1 and the grid electrode of the first switching tube M3, the other end of the first resistor R1 is grounded, the source electrode of the first switching tube M3 is connected with the inverting input end of the first transconductance amplifier G1, and the drain electrode of the first switching tube M3 is connected with the input end of the current-limiting control module;
the self-zeroing stable operational amplifier auxiliary loop comprises: the second transconductance amplifier G2, the first operational amplifier A1, the second resistor R2, the third resistor R3, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8, one end of the second resistor R2 is connected with a positive input end of the first transconductance amplifier G1, the other end of the second resistor R2 is respectively connected with an upper polar plate of the first capacitor C1 and one end of the first switch S1, the other end of the first switch S1 is respectively connected with one end of the third switch S3 and a left polar plate of the second capacitor C2, the other end of the third switch S3 is connected with a positive input end of the first transconductance amplifier G1, the other end of the second capacitor C2 is respectively connected with a positive input polar plate of the fifth switch C5 and the other end of the fourth switch S5, the other end of the fourth switch C5 is respectively connected with an inverting polar plate of the fourth capacitor C5, the fourth output polar plate of the seventh switch C5 is respectively connected with the positive input end of the fourth switch C1, the fourth capacitor C2 is connected with the positive polar plate of the fourth input end of the fourth switch C1, the fourth capacitor C2 is connected with the fourth polar plate is connected with the positive polar plate of the fourth polar plate is respectively; one end of the third resistor R3 is connected with the inverting input end of the first transconductance amplifier G1, the other end of the third resistor R3 is connected with the lower electrode plate of the first capacitor C1 and one end of the second switch S2, the other end of the second switch S2 is connected with one end of the fourth switch S4 and the left electrode plate of the third capacitor C3, the other end of the fourth switch S4 is connected with the non-inverting input end of the first transconductance amplifier G1, the right electrode plate of the third capacitor C3 is connected with the non-inverting input end of the first operational amplifier A1 and one end of the sixth switch S6, the inverting output end of the first operational amplifier A1 and the other end of the sixth switch S6 are connected with one end of the eighth switch S8, the other end of the eighth switch S8 is connected with the lower electrode plate of the fourth capacitor C4 and the upper electrode plate of the sixth capacitor C6 and the inverting input end of the second transconductance amplifier G2, and the lower electrode plate of the sixth capacitor C6 is grounded; the output end of the second transconductance amplifier G2 is connected with the output end of the first transconductance amplifier G1.
2. The PVT-insensitive current-limiting protection circuit of claim 1, wherein the non-inverting input of the first transconductance amplifier G1 is connected to the drain of the power tube M1, and the inverting input of the first transconductance amplifier G1 is connected to the drain of the sampling tube M2.
3. The PVT-insensitive current-limiting protection circuit according to claim 1, wherein the on/off of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are controlled by the control signals F1 and F2 output by the clock generating module, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are controlled by the control signal F1, and the first switch S1, the second switch S2, the seventh switch S7, and the eighth switch S8 are controlled by the control signal F2.
4. A PVT-insensitive current-limiting protection circuit according to claim 3, wherein the control signals F1 and F2 are square wave signals of the same frequency and different phases, and there is and only one on and one off control in one control period, and the switch controlled by the control signal F1 is not simultaneously turned on with the switch controlled by the control signal F2.
5. The PVT-insensitive current-limiting protection circuit of claim 1, wherein the current-limiting control module comprises: the non-inverting input end of the second operational amplifier A2 is respectively connected with one end of the fourth resistor R4 and the drain electrode of the first switching tube M3, and the other end of the fourth resistor R4 is grounded; the inverting input end of the second operational amplifier A2 is connected with the output end of the reference voltage generation module, and the output end of the second operational amplifier A2 is respectively connected with the grid electrode of the power tube M1 and the grid electrode of the sampling tube M2.
6. The PVT-insensitive current-limiting protection circuit of claim 5, wherein the reference voltage generation module comprises: the non-inverting input end of the third operational amplifier A3 is respectively connected with one end of the fifth resistor R5 and the drain electrode of the second switching tube M4, the other end of the fifth resistor R5 is respectively connected with the input end of the current-limiting control module and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded; the source of the second switching tube M4 is connected to the power voltage VIN, and the inverting input terminal of the third operational amplifier A3 receives the bandgap reference voltage VBG.
7. A PVT-insensitive current-limiting protection circuit according to claim 6, wherein the other end of the fifth resistor R5 is connected to the inverting input of the second operational amplifier A2.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111404375A (en) * | 2020-02-20 | 2020-07-10 | 上海南芯半导体科技有限公司 | Inductive current sampling circuit and implementation method thereof |
| CN114978054A (en) * | 2022-06-20 | 2022-08-30 | 圣邦微电子（北京）股份有限公司 | Self-stabilizing zero operational amplifier |
| CN115268549A (en) * | 2022-09-28 | 2022-11-01 | 成都芯翼科技有限公司 | Circuit for reducing input-output voltage difference of LDO (low dropout regulator) and low dropout regulator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111404375A (en) * | 2020-02-20 | 2020-07-10 | 上海南芯半导体科技有限公司 | Inductive current sampling circuit and implementation method thereof |
| CN114978054A (en) * | 2022-06-20 | 2022-08-30 | 圣邦微电子（北京）股份有限公司 | Self-stabilizing zero operational amplifier |
| CN115268549A (en) * | 2022-09-28 | 2022-11-01 | 成都芯翼科技有限公司 | Circuit for reducing input-output voltage difference of LDO (low dropout regulator) and low dropout regulator |
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