CN217216505U - Operational amplifier circuit - Google Patents
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- CN217216505U CN217216505U CN202220838487.0U CN202220838487U CN217216505U CN 217216505 U CN217216505 U CN 217216505U CN 202220838487 U CN202220838487 U CN 202220838487U CN 217216505 U CN217216505 U CN 217216505U
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Abstract
The utility model discloses an operational amplifier circuit, include: the circuit comprises an input stage circuit, an output stage circuit, a first compensation capacitor and a first capacitor expansion circuit; the input stage circuit is provided with a first input end and a second input end for receiving differential input signals, and a first current channel corresponding to the first input end and a second current channel corresponding to the second input end; the first end of the first compensation capacitor is coupled to the first current channel of the input stage circuit, and the second end of the first compensation capacitor is coupled to the output stage circuit; the first capacitance expansion circuit is coupled between the input stage circuit and the output stage circuit and is coupled to the first compensation capacitor through a cuttable metal film resistor. The utility model discloses can be favorable to reducing the stock in the gain stability multiple that can follow-up mode through laser cutting comes the adjustment system, can save required mask version in the manufacturing process simultaneously to reduce and repair the cost.
Description
Technical Field
The utility model relates to an integrated circuit technical field, concretely relates to operational amplifier circuit.
Background
Integrated operational amplifiers have gained rapid development since the 60's of the 20 th century. Originally, the integrated operational amplifier is mainly used for various operations of analog signals, such as proportion, summation, difference, integration, differentiation and the like, and with the development of technology, the integrated operational amplifier has been widely applied to processing and generating circuits of analog signals, and can be used for forming unit modules commonly used in various radio frequency and analog integrated circuits, such as active filters, trans-impedance amplifiers and the like.
According to the characteristic of the operational amplifier closed-loop negative feedback amplifying circuit, the product of the bandwidth and the amplification factor of the closed-loop negative feedback voltage amplifying circuit is the gain bandwidth product, and the value is usually fixed.
The micro power consumption operational amplifier has a relatively low gain-bandwidth product due to power consumption, but when the micro power consumption operational amplifier is applied to a signal amplification structure, the operational amplifier has a relatively narrow bandwidth due to the high gain of the operational amplifier. Meanwhile, since the application range of general operational amplifiers is wide, the unit gain stability of the operational amplifier is a requirement of most customers.
The existing solution is to change the bandwidth by changing Tape out (Tape out) or Mask (Mask), but this method of changing the original layout to adjust the gain stability multiple of the operational amplifier is relatively high in cost and occupies a large amount of stock.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides an operational amplifier circuit can be favorable to reducing the stock in the gain stability multiple that follow-up mode through laser cutting adjusted the system, can save required mask version in the manufacturing process simultaneously to reduce the trimming cost.
According to a first aspect of the present disclosure, there is provided an operational amplifier circuit comprising: the circuit comprises an input stage circuit, an output stage circuit, a first compensation capacitor and a first capacitor expansion circuit;
the input stage circuit is provided with a first input end and a second input end for receiving differential input signals, and a first current channel corresponding to the first input end and a second current channel corresponding to the second input end;
a first end of the first compensation capacitor is coupled to a first current channel of the input stage circuit, and a second end of the first compensation capacitor is coupled to the output stage circuit;
the first capacitance expansion circuit is coupled between the input stage circuit and the output stage circuit and is coupled to the first compensation capacitor through a cuttable metal film resistor.
Optionally, the operational amplifier circuit further comprises: and the first compensation resistor is connected between the second end of the first compensation capacitor and the output stage circuit.
Optionally, the first capacitance extension circuit comprises at least one third compensation capacitance;
each of the at least one third compensation capacitor is connected in parallel with the first compensation capacitor through a cuttable metal thin film resistor.
Optionally, at least one end of each of the at least one third compensation capacitor is connected to the first compensation capacitor through a cuttable metal thin film resistor.
Optionally, the first capacitance extension circuit comprises at least one fourth compensation capacitance;
each of the at least one fourth compensation capacitor is connected in parallel with the first compensation resistor through a cuttable metal film resistor.
Optionally, at least one end of each of the at least one fourth compensation capacitor is connected to the first compensation resistor through a cuttable metal thin film resistor.
Optionally, the operational amplifier circuit further comprises: a second compensation capacitor and a second capacitor expansion circuit;
a first end of the second compensation capacitor is coupled to a second current channel of the input stage circuit, and a second end of the second compensation capacitor is coupled to the output stage circuit;
the second capacitance expansion circuit is coupled between the input stage circuit and the output stage circuit and is coupled to the second compensation capacitor through a cuttable metal film resistor.
Optionally, the operational amplifier circuit further comprises: and the second compensation resistor is connected between the second end of the second compensation capacitor and the output stage circuit.
Optionally, the second capacitance extension circuit comprises at least one fifth compensation capacitance;
each fifth compensation capacitor in the at least one fifth compensation capacitor is connected with the second compensation capacitor in parallel through a cuttable metal thin film resistor.
Optionally, at least one end of each of the at least one fifth compensation capacitor is connected to the second compensation capacitor through a cuttable metal thin film resistor.
Optionally, the second capacitance extension circuit comprises at least one sixth compensation capacitance;
each of the at least one sixth compensation capacitor is connected in parallel with the second compensation resistor through a cuttable metal thin film resistor.
Optionally, at least one end of each of the at least one sixth compensation capacitor is connected to the second compensation resistor through a cuttable metal thin film resistor.
The beneficial effects of the utility model include at least:
the embodiment of the utility model provides a through set up compensation electric capacity and corresponding electric capacity expander circuit in the operational amplifier circuit, and adopt the metal film resistance that can cut to connect compensation electric capacity and electric capacity expander circuit, and then based on the cuttability of this metal film resistance, make follow-up mode that can directly pass through laser cutting metal film resistance change the size of the compensation electric capacity between input stage circuit and the output stage circuit, reach the mesh that changes the gain bandwidth product of operational amplifier circuit, thereby the equivalent realizes the adjustment to the bandwidth of operational amplifier circuit under equal magnification, be favorable to improving the applicable scene of every operational amplifier circuit, and then reduce the stock. Simultaneously the utility model discloses need not extra mask version and extra switching device at the bandwidth adjustment in-process to the operational amplifier circuit, signal path still less, the repair cost is lower.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
Fig. 1 shows a circuit configuration schematic of a test circuit of an operational amplifier according to the prior art;
FIG. 2 shows a circuit schematic of an operational amplifier according to the prior art;
fig. 3 is a schematic diagram of an operational amplifier circuit according to a first embodiment of the present invention;
fig. 4 is a schematic diagram illustrating an operational amplifier circuit according to a second embodiment of the present invention;
fig. 5 is a schematic diagram illustrating an operational amplifier circuit according to a third embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a structure of the operational amplifier circuit in fig. 3 after laser trimming.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
In this application, the MOSFET comprises a first terminal, a second terminal and a control terminal, and in the on-state of the MOSFET a current flows from the first terminal to the second terminal. The first end, the second end and the control end of the P-type MOSFET are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the N-type MOSFET are respectively a drain electrode, a source electrode and a grid electrode.
Fig. 1 shows a schematic circuit diagram of a test circuit of an operational amplifier according to the prior art. As shown in fig. 1, the test circuit includes an auxiliary operational amplifier U1. The non-inverting input terminal of the auxiliary operational amplifier U1 is connected to the output terminal of the operational amplifier under test DUT via the resistor R3, the non-inverting input terminal is grounded, and the output terminal is used for outputting the test voltage VL. The resistor R4 has a first terminal connected to the inverting input terminal of the auxiliary operational amplifier and the intermediate node of the resistor R3, and a second terminal receiving the reference voltage Vref. The auxiliary operational amplifier U1 and the operational amplifier under test DUT form a negative feedback closed loop system.
The test circuit further includes an input resistor Ri1 and a resistor R1 connected between the inverting input terminal of the operational amplifier DUT under test and ground, an input resistor Ri2 and a resistor R2 connected between the non-inverting input terminal of the operational amplifier DUT under test and ground, a switch S1 connected in parallel across the resistor R1 and a switch S2 connected in parallel across the resistor R2, and a feedback resistor RF1 and a feedback resistor RF 2. The feedback resistor RF1 has a first terminal connected to the output terminal of the auxiliary operational amplifier U1 and a second terminal connected to the intermediate node between the input resistor Ri1 and the resistor R1. The feedback resistor RF2 has a first terminal connected to the intermediate node between the input resistor Ri2 and the resistor R2, and a second terminal connected to ground.
Fig. 2 shows a circuit schematic of an operational amplifier according to the prior art, and as shown in fig. 2, the operational amplifier 100 includes an input stage circuit 110 and an output stage circuit 120. The input stage circuit 110 includes transistors Mn1-Mn4 and a transistor Mp1, the transistors Mn1 and Mn2 forming a differential transistor pair, first terminals of the transistors Mn1 and Mn2 are connected to each other, control terminals of the transistors Mn1 and Mn2 respectively receive the differential input signals VIN and VIP, a second terminal of the transistor Mn1 is connected to a first terminal of the transistor Mn3, a second terminal of the transistor Mn2 is connected to a first terminal of the transistor Mn4, the transistors Mn3 and Mn4 forming a cascode transistor pair, and second terminals of the transistors Mn3 and Mn4 are connected to ground. The first terminal of the transistor Mp1 is connected to the power supply voltage VCC, the second terminal of the transistor Mp1 is connected to the first terminals of the transistor Mn1 and the transistor Mn2, the control terminal of the transistor Mp1 receives the bias voltage Vb, and the transistor Mp1 is used for providing bias current for the transistors Mn1-Mn 4. The output stage circuit 120 comprises a transistor Mp2 and a transistor Mn5, wherein the transistor Mp2 and the transistor Mn5 are sequentially connected in series between a power supply voltage VCC and ground, a control terminal of the transistor Mp2 receives a bias voltage Vb, a control terminal of the transistor Mn5 is connected with a first terminal of a transistor Mn4, and a first terminal of the transistor Mn5 is used for providing a differential amplified signal Vout. In order to improve the loop stability of the operational amplifier 100, the operational amplifier 100 further includes a compensation capacitor Cc, a first end of the compensation capacitor Cc and a first end of the transistor Mn4 are connected to the node a, and a second end of the compensation capacitor Cc and a first end of the transistor Mn5 are connected to the node B. The loop setup of the operational amplifier is generally achieved by charging the compensation capacitor and parasitic circuits in the circuit to the required voltage and then based on negative feedback.
For example, the bandwidth of the operational amplifier circuit can be conveniently adjusted, the operational amplifier circuit in fig. 2 is further improved, and the size of the compensation capacitor in the circuit is changed in a laser trimming mode, so that different gain bandwidth products are obtained, the bandwidth of the operational amplifier circuit under the same amplification factor can be equivalently adjusted, the applicable scene of each operational amplifier circuit is improved, the inventory is favorably reduced, and the trimming cost is lower.
Example one
As shown in fig. 3, an operational amplifier circuit 200 according to an embodiment of the present invention includes: an input stage circuit 210, an output stage circuit 220, a first compensation capacitor Ccp, a first capacitance extension circuit 230, a second compensation capacitor Ccn, and a second capacitance extension circuit 240. The input stage circuit 210 is configured to receive the differential input signals VIN and VIP and convert the differential input signals VIN and VIP into a difference signal. The output stage circuit 220 is connected to the input stage circuit 210, and is configured to obtain a differential amplified signal Vout according to the difference signal. The first compensation capacitor Ccp and/or the second compensation capacitor Ccn are used to improve operational amplifier 200 loop stability.
The input stage circuit 210 has first and second inputs receiving differential input signals VIN and VIP, and a first current path corresponding to the first input and a second current path corresponding to the second input. In this embodiment, the specific circuit structure of the input stage circuit 210 can be understood by referring to the description of the input stage circuit 110 shown in fig. 2, and is not described herein again.
It should be understood that the first input terminal and the second input terminal of the input stage circuit 210 correspond to the control terminals of the transistor Mn2 and the transistor Mn1, respectively; a first current channel in the input stage circuit 210 corresponds to a current channel formed by a transistor Mn2 and a transistor Mn4 which are connected in series between the second terminal of the transistor Mp1 and the reference ground, wherein a connection node between the transistor Mn2 and the transistor Mn4 is denoted as a node a; and a second current path in the input stage circuit 210 corresponds to a current path formed by a transistor Mn1 and a transistor Mn3 which are connected in series between the second terminal of the transistor Mp1 and the reference ground, wherein a connection node between the transistor Mn1 and the transistor Mn3 is denoted as a node B. In the embodiment, the control terminal of the transistor Mp2 is connected to the node a, and the control terminal of the transistor Mn5 is connected to the node B.
The output stage circuit 220 includes a transistor Mp2 and a transistor Mn5 connected in series between the supply voltage VCC and a ground reference. The first terminal of the transistor Mp2 is connected to the power supply voltage VCC, the second terminal of the transistor Mp2 and the first terminal of the transistor Mn5 are both connected to the output node Vout of the operational amplifier circuit 200, and the second terminal of the transistor Mn5 is connected to the ground reference.
A first terminal of the first compensation capacitor Ccp is coupled to the first current path of the input stage circuit 210, and a second terminal of the first compensation capacitor Ccp is coupled to the output stage circuit 220. In this embodiment, a first end of the first compensation capacitor Ccp and the first current path of the input stage circuit 210 are coupled to the node a, and a second end of the first compensation capacitor Ccp is coupled to the output node Vout through the first compensation resistor Rmp and the output stage circuit 220.
The first capacitance extension circuit 230 is coupled between the input stage circuit 210 and the output stage circuit 220, and is coupled to the first compensation capacitance Ccp through a cuttable metal thin film resistor. In this embodiment, the first capacitance expanding circuit 230 is connected in parallel to two ends of the first compensation capacitor Ccp. Specifically, the first capacitance extension circuit 230 includes at least one third compensation capacitance Ctp1, each third compensation capacitance Ctp1 of the at least one third compensation capacitance Ctp1 is connected in parallel with the first compensation capacitance Ccp through a cuttable metal thin film resistor.
In this embodiment, at least one end of each third compensation capacitor Ctp1 of the at least one third compensation capacitor Ctp1 is connected to the first compensation capacitor Ccp through a cuttable metal film resistor. For example, one end of each third compensation capacitor Ctp1 of the at least one third compensation capacitor Ctp1 is connected to one end of the first compensation capacitor Ccp through a cuttable metal thin film resistor R11, and the other end of each third compensation capacitor Ctp1 may be directly connected to the other end of the first compensation capacitor Ccp; or one end of each third compensation capacitor Ctp1 in the at least one third compensation capacitor Ctp1 may be connected with one end of the first compensation capacitor Ccp through a cuttable metal film resistor R11, and the other end of each third compensation capacitor Ctp1 may be connected with the other end of the first compensation capacitor Ccp through a cuttable metal film resistor R12.
A first terminal of the second compensation capacitor Ccn is coupled to the second current path of the input stage circuit 210, and a second terminal of the second compensation capacitor Ccn is coupled to the output stage circuit 220. In this embodiment, the first terminal of the second compensation capacitor Ccn and the second current path of the input stage circuit 210 are coupled to the node B, and the second terminal of the second compensation capacitor Ccn is coupled to the output node Vout through the second compensation resistor Rmn and the output stage circuit 220.
The second capacitor extension circuit 240 is coupled between the input stage circuit 210 and the output stage circuit 220, and is coupled to the second compensation capacitor Ccn through a cuttable metal film resistor. In this embodiment, the second capacitance extension circuit 240 is connected in parallel to two ends of the second compensation capacitor Ccn. Specifically, the second capacitance extension circuit 240 includes at least one fifth compensation capacitance Ctn1, each fifth compensation capacitance Ctn1 of the at least one fifth compensation capacitance Ctn1 being connected in parallel with the second compensation capacitance Ccn through a cuttable metal thin-film resistor.
In this embodiment, at least one end of each fifth compensation capacitor Ctn1 of the at least one fifth compensation capacitor Ctn1 is connected to the second compensation capacitor Ccn through a cuttable metal thin film resistor. For example, one end of each fifth compensation capacitor Ctn1 of the at least one fifth compensation capacitor Ctn1 is connected to one end of the second compensation capacitor Ccn through a cuttable metal thin film resistor R13, and the other end of each fifth compensation capacitor Ctn1 may be directly connected to the other end of the second compensation capacitor Ccn; or one end of each fifth compensation capacitor Ctn1 in the at least one fifth compensation capacitor Ctn1 may be connected to one end of the second compensation capacitor Ccn through a cuttable metal thin-film resistor R13, and the other end of each fifth compensation capacitor Ctn1 may be connected to the other end of the second compensation capacitor Ccn through a cuttable metal thin-film resistor R14.
It should be noted that the drawings in the present application are only a simple drawing for showing the equivalent of the metal thin film resistance as the resistance, and a specific metal wire may be used in the actual chip design. Based on the operational amplifier circuit structure in this embodiment, when the bandwidth of the operational amplifier circuit 200 needs to be modified subsequently, the metal film resistor R11 and/or R12 and the metal film resistor R13 and/or R14 may be cut off directly on a formed chip by laser cutting, so as to achieve the purpose of changing the capacitance value of the compensation capacitor connected to the operational amplifier circuit 200, thereby adjusting the bandwidth of the operational amplifier circuit 200, which is convenient and fast, and is beneficial to improving the applicable scenarios of the operational amplifier circuit, thereby reducing the inventory and lowering the modification cost.
Based on the connection relationship between the first compensation capacitor Ccp and the at least one third compensation capacitor Ctp1, and between the second compensation capacitor Ccn and the at least one fifth compensation capacitor Ctn1 in the present embodiment, after the metal film resistor between the first compensation capacitor Ccp and any third compensation capacitor Ctp1 is cut off to break the electrical connection relationship between the first compensation capacitor Ccp and any third compensation capacitor Ctp1, and the metal film resistor between the second compensation capacitor Ccn and any fifth compensation capacitor Ctn1 is cut off to break the electrical connection relationship between the second compensation capacitor Ccn and any fifth compensation capacitor Ctn1, as shown in fig. 6, the capacitance value of the compensation capacitor connected in the operational amplifier circuit 200 becomes smaller, and the gain bandwidth and the bandwidth of the operational amplifier circuit 200 can be increased. That is to say, the operational amplifier circuit 200 in this embodiment can realize the adjustment of the bandwidth from small to large in the subsequent laser trimming manner. However, it should be noted that, because the corresponding pole-zero change of the circuit is not large, the operational amplifier circuit 200 cannot achieve unity gain stability when the capacitance value of the compensation capacitor is reduced, and the system needs to be fixedly applied in a negative feedback system and the gain of the system is larger than a specific value required to stabilize the applied system.
It is understood that, in some possible embodiments of the present invention, only the first compensation capacitor Ccp may be disposed in the operational amplifier circuit 200, and at this time, the control terminal of the transistor Mp2 is connected to the control terminal of the transistor Mp1, and the control terminal of the transistor Mn5 is connected to the node a. Based on the circuit structure of the operational amplifier circuit, when the bandwidth of the operational amplifier circuit 200 needs to be modified subsequently, the metal thin film resistor R11 and/or R12 can be cut off by laser cutting, so as to change the capacitance of the compensation capacitor connected to the operational amplifier circuit, and further change the bandwidth of the operational amplifier circuit. Therefore, the circuit structure should also be within the scope of the present invention.
Example two
The circuit structure of the operational amplifier circuit 300 disclosed in the present embodiment is shown in fig. 4.
The circuit structure of the operational amplifier circuit 300 in this embodiment is substantially the same as the circuit structure of the operational amplifier circuit 200 disclosed in the first embodiment. As shown in fig. 4, the operational amplifier circuit 300 according to the embodiment of the present invention also includes: an input stage circuit 310, an output stage circuit 320, a first compensation capacitor Ccp, a first capacitance extension circuit 330, a second compensation capacitor Ccn, and a second capacitance extension circuit 340. The circuit structure of the input stage circuit 310 can be understood with reference to the description of the input stage circuit 210 in the first embodiment, the circuit structure of the output stage circuit 320 can be understood with reference to the description of the output stage circuit 220 in the first embodiment, and the first compensation capacitor Ccp and the second compensation capacitor Ccn can be understood with reference to the corresponding description in the first embodiment, which is not repeated herein.
The difference is that in the present embodiment, the first capacitance expanding circuit 330 is connected in parallel to two ends of the first compensation resistor Rmp. Specifically, the first capacitance extension circuit 330 includes at least one fourth compensation capacitance Ctp2, each fourth compensation capacitance Ctp2 of the at least one fourth compensation capacitance Ctp2 being connected in parallel with the first compensation resistance Rmp through a cuttable metal thin-film resistance. That is, between the input stage circuit 310 and the output stage circuit 320, the first compensation capacitor Ccp and the first capacitance extension circuit 330 are connected in series, and meanwhile, any two fourth compensation capacitors Ctp2 of the at least one fourth compensation capacitor Ctp2 are connected in parallel.
In this embodiment, at least one end of each fourth compensation capacitor Ctp2 of the at least one fourth compensation capacitor Ctp2 is connected to the first compensation resistor Rmp through a cuttable metal thin film resistor. For example, one end of each fourth compensation capacitor Ctp2 of the at least one fourth compensation capacitor Ctp2 is connected to one end of the first compensation resistor Rmp through a cuttable metal thin film resistor R21, and the other end of each fourth compensation capacitor Ctp2 is directly connected to the other end of the first compensation resistor Rmp; or one end of each fourth compensation capacitor Ctp2 in the at least one fourth compensation capacitor Ctp2 may be connected to one end of the first compensation resistor Rmp through a cuttable metal thin-film resistor R21, and the other end of each fourth compensation capacitor Ctp2 may be connected to the other end of the first compensation resistor Rmp through a cuttable metal thin-film resistor R22.
In this embodiment, the second capacitance expanding circuit 340 is connected in parallel to two ends of the second compensation resistor Rmn. Specifically, the second capacitance extension circuit 340 includes at least one sixth compensation capacitance Ctn2, each sixth compensation capacitance Ctn2 of the at least one sixth compensation capacitance Ctn2 being connected in parallel with the second compensation resistance Rmn through a cuttable metal thin-film resistance. That is, between the input stage circuit 310 and the output stage circuit 320, the second compensation capacitor Ccn and the second capacitor extension circuit 340 are connected in series, and any two sixth compensation capacitors Ctn2 of the at least one sixth compensation capacitor Ctn2 are connected in parallel.
In this embodiment, at least one end of each sixth compensation capacitor Ctn2 in the at least one sixth compensation capacitor Ctn2 is connected to the second compensation resistor Rmn through a cuttable metal thin film resistor. For example, one end of each sixth compensation capacitor Ctn2 of the at least one sixth compensation capacitor Ctn2 is connected to one end of the second compensation resistor Rmn through a cuttable metal thin film resistor R23, and the other end of each sixth compensation capacitor Ctn2 is directly connected to the other end of the second compensation resistor Rmn; or one end of each sixth compensation capacitor Ctn2 in the at least one sixth compensation capacitor Ctn2 may be connected to one end of the second compensation resistor Rmn through a cuttable metal thin-film resistor R23, and the other end of each sixth compensation capacitor Ctn2 may be connected to the other end of the second compensation resistor Rmn through a cuttable metal thin-film resistor R24.
It can be understood that, based on the connection relationship between the first compensation capacitor Ccp and the at least one fourth compensation capacitor Ctp2 and between the second compensation capacitor Ccn and the at least one sixth compensation capacitor Ctn2 in this embodiment, after the metal film resistor between the first compensation capacitor Ccp and any fourth compensation capacitor Ctp2 is cut off to disconnect the electrical connection relationship between the first compensation capacitor Ccp and any fourth compensation capacitor Ctp2, and the metal film resistor between the second compensation capacitor Ccn and any sixth compensation capacitor Ctn2 is cut off to disconnect the electrical connection relationship between the second compensation capacitor Ccn and any sixth compensation capacitor Ctn2, the capacitance value of the compensation capacitor connected in the operational amplifier circuit 300 becomes larger, and the gain bandwidth and the bandwidth of the operational amplifier circuit 300 can be reduced. That is to say, the operational amplifier circuit 300 in the present embodiment can adjust the bandwidth from large to small in a subsequent laser trimming manner.
EXAMPLE III
The circuit structure of the operational amplifier circuit 400 disclosed in this embodiment is shown in fig. 5.
As shown in fig. 5, the circuit structure of the operational amplifier circuit 400 in this embodiment is a combination of the operational amplifier circuits 200 and 300 disclosed in the first and second embodiments. Specifically, the embodiment of the present invention discloses an operational amplifier circuit 400 including: an input stage circuit 410, an output stage circuit 420, a first compensation capacitor Ccp, a first capacitance extension circuit 430, a second compensation capacitor Ccn, and a second capacitance extension circuit 440. The circuit structure of the input stage circuit 410 can be understood with reference to the description of the input stage circuit 210 in the first embodiment, the circuit structure of the output stage circuit 420 can be understood with reference to the description of the output stage circuit 220 in the first embodiment, and the first compensation capacitor Ccp and the second compensation capacitor Ccn can be understood with reference to the corresponding description in the first embodiment, which is not repeated herein.
The difference is that in the present embodiment, the first capacitance extension circuit 430 includes at least one third compensation capacitor Ctp1 connected in parallel to two ends of the first compensation capacitor Ccp and at least one fourth compensation capacitor Ctp2 connected in parallel to two ends of the first compensation resistor Rmp. The structure of the at least one third compensation capacitor Ctp1 can be understood by referring to the corresponding description in the first embodiment, and the structure of the at least one fourth compensation capacitor Ctp2 can be understood by referring to the corresponding description in the second embodiment, which is not repeated herein.
In this embodiment, the second capacitance extension circuit 440 includes at least one fifth compensation capacitor Ctn1 connected in parallel to two ends of the second compensation capacitor Ccn and at least one sixth compensation capacitor Ctn2 connected in parallel to two ends of the second compensation resistor Rnp. The structure of the at least one fifth compensation capacitor Ctn1 can be understood with reference to the corresponding description in the foregoing first embodiment, and the structure of the at least one sixth compensation capacitor Ctn2 can be understood with reference to the corresponding description in the foregoing second embodiment, which is not repeated herein.
It is understood that the operational amplifier circuit 400 in the present embodiment can realize at least one of the adjustment of the bandwidth from large to small and from small to large in the subsequent laser trimming manner.
To sum up, the embodiment of the utility model provides a through set up compensation electric capacity and corresponding electric capacity expander circuit in operational amplifier circuit, and adopt the metal film resistance that can cut to connect compensation electric capacity and electric capacity expander circuit, and then based on the cuttability of this metal film resistance, make follow-up can directly change the size of the compensation electric capacity between input stage circuit and the output stage circuit through the mode of laser cutting metal film resistance, reach the mesh that changes operational amplifier circuit's gain bandwidth product, thereby the equivalence realizes the adjustment to the bandwidth of operational amplifier circuit under equal magnification, be favorable to improving the applicable scene of every operational amplifier circuit, and then reduce the stock. Simultaneously the utility model discloses need not extra mask version and extra switching device at the bandwidth adjustment in-process to the operational amplifier circuit, signal path still less, the repair cost is lower.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious changes and modifications may be made without departing from the scope of the present invention.
Claims (12)
1. An operational amplifier circuit, comprising: the circuit comprises an input stage circuit, an output stage circuit, a first compensation capacitor and a first capacitor expansion circuit;
the input stage circuit is provided with a first input end and a second input end for receiving differential input signals, and a first current channel corresponding to the first input end and a second current channel corresponding to the second input end;
a first end of the first compensation capacitor is coupled to a first current channel of the input stage circuit, and a second end of the first compensation capacitor is coupled to the output stage circuit;
the first capacitance extension circuit is coupled between the input stage circuit and the output stage circuit and is coupled to the first compensation capacitor through a cuttable metal film resistor.
2. The operational amplifier circuit of claim 1, further comprising: and the first compensation resistor is connected between the second end of the first compensation capacitor and the output stage circuit.
3. The operational amplifier circuit according to any one of claims 1 and 2, wherein the first capacitance extension circuit comprises at least one third compensation capacitance;
each of the at least one third compensation capacitor is connected in parallel with the first compensation capacitor through a cuttable metal thin film resistor.
4. The operational amplifier circuit as claimed in claim 3, wherein at least one end of each of the at least one third compensation capacitor is connected to the first compensation capacitor through a cuttable metal thin film resistor.
5. The operational amplifier circuit of claim 2, wherein the first capacitance extension circuit comprises at least one fourth compensation capacitance;
each of the at least one fourth compensation capacitor is connected in parallel with the first compensation resistor through a cuttable metal film resistor.
6. The operational amplifier circuit as claimed in claim 5, wherein at least one end of each of the at least one fourth compensation capacitor is connected to the first compensation resistor through a cuttable metal thin film resistor.
7. The operational amplifier circuit of claim 1, further comprising: a second compensation capacitor and a second capacitor expansion circuit;
a first end of the second compensation capacitor is coupled to a second current channel of the input stage circuit, and a second end of the second compensation capacitor is coupled to the output stage circuit;
the second capacitance expansion circuit is coupled between the input stage circuit and the output stage circuit and is coupled to the second compensation capacitor through a cuttable metal film resistor.
8. The operational amplifier circuit of claim 7, further comprising: and the second compensation resistor is connected between the second end of the second compensation capacitor and the output stage circuit.
9. The operational amplifier circuit according to any one of claims 7 and 8, wherein the second capacitance extension circuit comprises at least one fifth compensation capacitance;
each of the at least one fifth compensation capacitor is connected in parallel with the second compensation capacitor through a cuttable metal thin film resistor.
10. The operational amplifier circuit as claimed in claim 9, wherein at least one end of each of the at least one fifth compensation capacitor is connected to the second compensation capacitor through a cuttable metal thin film resistor.
11. The operational amplifier circuit of claim 8, wherein the second capacitance extension circuit comprises at least one sixth compensation capacitance;
each of the at least one sixth compensation capacitor is connected in parallel with the second compensation resistor through a cuttable metal thin film resistor.
12. The operational amplifier circuit as claimed in claim 11, wherein at least one end of each of the at least one sixth compensation capacitor is connected to the second compensation resistor through a cuttable metal thin film resistor.
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| US11789131B1 (en) * | 2022-12-06 | 2023-10-17 | Aeva, Inc. | Techniques for using an electro-optical phase locked loop in a LIDAR system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11789131B1 (en) * | 2022-12-06 | 2023-10-17 | Aeva, Inc. | Techniques for using an electro-optical phase locked loop in a LIDAR system |
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