CN113411055B - Bias current control device, radio frequency amplifier, electronic device and chip - Google Patents
Bias current control device, radio frequency amplifier, electronic device and chip Download PDFInfo
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- CN113411055B CN113411055B CN202110951870.7A CN202110951870A CN113411055B CN 113411055 B CN113411055 B CN 113411055B CN 202110951870 A CN202110951870 A CN 202110951870A CN 113411055 B CN113411055 B CN 113411055B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal
Abstract
The application relates to a bias current control device, a radio frequency amplifier, an electronic device and a chip. Wherein, a bias current control device includes: the current detector is connected with a preset radio frequency amplifier output stage and copies the bias current of the radio frequency amplifier output stage as a mirror bias current according to a preset proportion; the feedback current generator copies the mirror image bias current as a feedback current according to a preset proportion; and the bias voltage generator generates a bias voltage for the output stage of the radio frequency amplifier according to the feedback current and the reference voltage.
Description
Technical Field
The present application relates to the field of wireless communication technologies, and in particular, to a bias current control device, a radio frequency amplifier, an electronic device, and a chip.
Background
At present, a transistor or a resistance voltage division method is adopted in a traditional radio frequency amplifier biasing method, with the development of an integrated circuit process, the length of a transistor channel is reduced, and the influence of the threshold voltage of a common-gate tube on the current of a cascode configuration common-source tube is large due to the channel length modulation effect. And the mass production of the radio frequency amplifier shows that the consistency of the bias current is poor. In order to ensure the consistency of the bias current, a digital Fuse current is adopted to calibrate and adjust the current in a technical means, so that the integration cost and the test cost of a chip are higher.
Disclosure of Invention
Based on this, the present application provides a bias current control device including: the current detector is connected with a preset radio frequency amplifier output stage and copies the bias current of the radio frequency amplifier output stage as a mirror bias current according to a preset proportion; the feedback current generator copies the mirror image bias current as a feedback current according to a preset proportion; and the bias voltage generator generates a bias voltage for the output stage of the radio frequency amplifier according to the feedback current and the reference voltage.
Optionally, the current detector and the rf amplifier output stage form a first mirror current source circuit, the rf amplifier output stage includes a source current terminal of the first mirror current source circuit, and the current detector includes a mirror current terminal of the first mirror current source circuit.
Further, the current detector comprises a mirror circuit of the preset radio frequency amplifier output stage.
Optionally, the feedback current generator comprises: and the source current end of the first mirror current source circuit is connected with the current detector, and the mirror current end of the first mirror current source circuit is connected with the bias voltage generator.
Optionally, the bias voltage generator comprises: and the first operational amplifier generates the bias voltage according to the difference value between the feedback voltage generated by the feedback current and the reference voltage.
Optionally, the bias current control device further includes: a reference voltage generator for generating the reference voltage.
Optionally, the reference voltage generator includes a second mirror current source circuit and a third mirror current source circuit connected to each other, where a source current end of the second mirror current source circuit is connected to a mirror current end of the third mirror current source circuit, and a source current end of the third mirror current source circuit is connected to a mirror current end of the second mirror current source circuit.
Optionally, the bias current control device may further include: a first choke inductance connected to the RF amplifier output stage.
Optionally, the bias current control device may further include: and the matching circuit is connected with the output stage of the radio frequency amplifier.
The present application also provides a radio frequency amplifier comprising: an output stage; any of the foregoing bias current control devices connected to the output stage.
The present application further provides an electronic device, comprising: any one of the foregoing bias current control devices, or the foregoing radio frequency amplifier.
The present application further provides a chip, comprising: any one of the foregoing bias current control devices, or the foregoing radio frequency amplifier.
By using the bias current control device, the radio frequency amplifier, the electronic equipment and the chip, the bias current of the output stage of the radio frequency amplifier can be relatively accurately detected by taking the mirror circuit of the output stage of the radio frequency amplifier as a current detector, and the bias current can be copied into the mirror bias current according to a preset proportion. And the mirror bias current may be copied to the feedback current in a predetermined ratio using a feedback current generator including a mirror current source circuit. The bias current of the output stage of the radio frequency amplifier can be copied into the feedback current relatively accurately by using the method. And the bias voltage generator can control the bias current of the output stage of the radio frequency amplifier to be a preset current value according to the feedback current.
In the above scheme, the bias current, the mirror bias current and the feedback current of the output stage of the rf amplifier generated by the apparatus may be the positive temperature coefficient current. Therefore, when the temperature rises, the transconductance of the transistor of the radio frequency amplifier can be ensured to be compensated. And the phenomenon that the gain of the amplifier is reduced when the temperature is increased is improved, and the performance of the amplifier at high temperature is guaranteed.
On the other hand, at normal temperature, the consistency of the bias current control device, the radio frequency amplifier, the electronic device and the chip which are produced in batch can be relatively high. The product yield and the mass production stability are improved.
In the above scheme, since the signal is transferred through at least one mirror current circuit, the bias current generated by the above scheme can be less affected by the transistor process. Meanwhile, the bias current control device is realized by a pure analog circuit, the topological structure is relatively simple, and the realization cost is relatively low.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without exceeding the protection scope of the present application.
Fig. 1 shows a schematic of the topology of a bias current control device according to an embodiment of the present application.
Fig. 2 shows a schematic topology of a bias current control device according to another embodiment of the present application.
Fig. 3 shows a schematic diagram of the composition of a radio frequency amplifier according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 shows a schematic of the topology of a bias current control device according to an embodiment of the present application.
The apparatus 1000 may be used for bias current control of the rf amplifier output stage 11. Alternatively, the radio frequency amplifier output stage 11 may comprise at least one three-terminal transistor. The three-terminal transistor included in the rf amplifier output stage 11 may be a unipolar transistor or a bipolar transistor. For example, the at least one transistor may include a transistor. The triode can be an NPN type triode or a PNP type triode. The at least one transistor may also include a field effect transistor. The field effect transistor can be an N-channel field effect transistor or a P-channel field effect transistor.
As shown in the example embodiment, the rf amplifier output stage 11 may include two three-terminal transistors, a three-terminal transistor N1 and a three-terminal transistor N2, respectively. Wherein the three-terminal transistor N1 and the three-terminal transistor N2 may both be N-channel field effect transistors. The three-terminal transistor N1 and the three-terminal transistor N2 may be connected in series. Alternatively, other topologies for the rf amplifier output stage 11 may be used.
As shown in fig. 1, the apparatus 1000 may include: a current detector 12, a feedback current generator 13 and a bias voltage generator 14.
Wherein the current detector 12 may be connected to the rf amplifier output stage 11. And the bias current IDD of the output stage 11 of the rf amplifier can be copied as the mirror bias current ISense in a preset ratio.
Alternatively, the current detector 12 may include at least one three-terminal transistor. Wherein the at least one three-terminal transistor included in the current detector 12 may be mirrored with the at least one three-terminal transistor included in the rf amplifier output stage 11. As shown in the exemplary embodiment, the current detector 12 includes a three-terminal transistor N22 that mirrors the three-terminal transistor N2 included in the rf amplifier output stage 11. The two transistors are the same three-terminal transistors, and the topological connection of the two transistors is the same or similar and is in a symmetrical state. And both connect the same or similar input stimuli. So that the operating states of both can be made the same. Similarly, the current detector 12 includes a three-terminal transistor N11 mirrored to the three-terminal transistor N1 included in the rf amplifier output stage 11.
Further, the current detector 12 may include a mirror circuit of the radio frequency amplifier output stage 11. I.e. the current detector 12 may comprise the same or similar circuit topology as the rf amplifier output stage 11, while both may be connected to the same or similar input stimuli. The mirror bias current ISense of the current detector 12 and the bias current IDD of the rf amplifier output stage 11 are mirror images of each other. The two are equal or in a preset proportional relationship. Alternatively, the three-terminal transistor included in the current detector 12 and the three-terminal transistor included in the radio frequency amplifier output stage 11 may be the same transistor. At this time, the mirror bias current ISense of the current detector 12 is equal to the bias current IDD of the rf amplifier output stage 11.
As shown in the exemplary embodiment, the current detector 12, which is identical to the rf amplifier output stage 11, may also include two three-terminal transistors N11 and N22. Wherein the three-terminal transistors N11 and N22 may be N-channel fets similar to the three-terminal transistors N1 and N2, respectively. Alternatively, the three-terminal transistor N11 may be the same transistor as the three-terminal transistor N1, and the three-terminal transistor N22 may also be the same transistor as the three-terminal transistor N2.
As shown in the example embodiment, the topological connection between the three-terminal transistors N11 and N22 may be the same as the topological connection between the three-terminal transistors N1 and N2, in a symmetrical configuration. For example, in an example embodiment, the gate of the three-terminal transistor N11 and the gate of the three-terminal transistor N1 may be connected to each other, in common, to the bias voltage driver VG 1. The gate of the three-terminal transistor N22 and the gate of the three-terminal transistor N2 may be connected to each other and commonly connected to a bias voltage driver VG 2. The source of the three-terminal transistor N1 is connected to signal ground, and the source of the three-terminal transistor N11 may also be connected to signal ground. The drain of the three-terminal transistor N1 is connected to the source of the terminal transistor N2, and the drain of the three-terminal transistor N11 may also be connected to the source of the three-terminal transistor N22. The drain of the three-terminal transistor N2 may serve as the output terminal of the rf amplifier output stage 11. The drain of the three-terminal transistor N22 may serve as the output terminal of the current detector 12, outputting the mirror bias current ISense.
As shown in the exemplary embodiment, since the circuit configuration of the current detector 12 is identical to the topology of the rf amplifier output stage 11. Meanwhile, the input excitation connected with the two is also identical, and the method comprises the following steps: bias voltage driver VG1, bias voltage driver VG2, and input signal RFIN. Thus, the working states of the two are the same, and the working parameters are the same and similar. Namely, the mirror bias current ISense flowing through the current detector 12 and the bias current IDD of the rf amplifier output stage 11 are in a predetermined proportional relationship. The predetermined ratio depends on the difference between the transmission characteristics of the three-terminal transistors N1, N2 and N11, N22. Optionally, the three-terminal transistors N1 and N2, N11 and N22 may be packaged in the same chip, so that the parameters of the four three-terminal transistors may be relatively consistent, and the predetermined ratio may be close to 1.
Optionally, a resistor R1 may be included between the gate of the three-terminal transistor N11 and the gate of the three-terminal transistor N1, and a resistor R2 may be included between the gate of the three-terminal transistor N22 and the gate of the three-terminal transistor N2.
As shown in fig. 1, the feedback current generator 13 may be connected to the current detector 12. And the mirror bias current ISense can be copied as the feedback current Iref at a preset ratio. Alternatively, the preset ratio may be 1: 1. alternatively, the feedback current generator 13 may include a first mirror current source circuit. The mirror bias current ISense can be copied as the feedback current Iref using a first mirror current source circuit. Wherein the source current terminal 131 of the first mirrored current source circuit may be connected to the output terminal of the current detector 12. The mirror current terminal 132 of the first mirror current source circuit may be connected to the bias voltage generator 14, and output a feedback current Iref to the bias voltage generator 14.
Alternatively, the first mirror current source circuit may include three-terminal transistors P1 and P2. The three-terminal transistors P1 and P2 may be unipolar transistors or bipolar transistors. The three-terminal transistors P1 and P2 may be N-channel fets or P-channel fets. The three-terminal transistors P1 and P2 may be NPN transistors or PNP transistors. Alternatively, the three-terminal transistors P1 and P2 may be other types of transistors.
As shown in the example embodiment, the three-terminal transistors P1 and P2 may be both P-channel field effect transistors. In example embodiments, the gate of the three-terminal transistor P1 and the gate of the three-terminal transistor P2 may be connected to each other. The source of the three-terminal transistor P1 and the source of the three-terminal transistor P2 may be commonly connected to a power supply VDD. The drain and gate of three-terminal transistor P1 may be shorted to each other. A drain of the three-terminal transistor P1 may serve as a source current terminal of the first mirror current source circuit, and a drain of the three-terminal transistor P2 may serve as a mirror current terminal of the first mirror current source circuit. Alternatively, the first mirror current source circuit may also adopt other topologies.
As shown in fig. 1, the bias voltage generator 14 may be connected between the feedback current generator 13 and the current detector 12. The bias voltage generator 14 may generate a bias voltage stimulus VG1 from the feedback current Iref. The bias voltage driver VG1 may be connected to both the current detector 12 and the rf amplifier output stage 11. As shown in the exemplary embodiment, the bias voltage driver VG1 may be connected to both the gate of the three-terminal transistor N11 of the current detector 12 and the gate of the three-terminal transistor N1 of the rf amplifier output stage 11.
The bias voltage generator 14 may constitute a feedback control circuit with the feedback current generator 13 and the current detector 12. The negative feedback control circuit can adjust the mirror bias current ISense of the current detector 12 to a preset current value. Since the rf amplifier output stage 11 and the current detector 12 are mirror images of each other, the bias current IDD and the mirror bias current ISense are also mirror images of each other. Therefore, while the mirror bias current ISense is adjusted to the preset current value, the bias current IDD may be adjusted to a second preset current value. So that an effective control of the bias current IDD can be achieved.
As shown in fig. 1, the bias voltage generator 14 may include a resistor R3. The resistor R3 may be connected to the feedback current generator 13. Resistor R3 may be used to convert the feedback current Iref to the feedback voltage VFB. Optionally, the bias voltage generator 14 may further include an operational amplifier OP 1. The feedback voltage VFB and the reference voltage VREF may be respectively connected to a positive input terminal and a negative input terminal of the operational amplifier OP 1. The operational amplifier OP1 may be used to generate an offset voltage stimulus VG1 from a comparison of the feedback voltage VFB and the reference voltage VREF. Optionally, the bandwidth of the operational amplifier OP1 may cover the operating bandwidth of the device 1000. Alternatively, the operational amplifier OP1 may be replaced by a comparator.
As shown in fig. 1, the feedback current generator 13 and the current detector 12 and the bias voltage generator 14 may constitute a deep negative feedback circuit. From the feedback circuit principle, it can be known that:
VREF=VFB （1）
namely:
VREF=ISense×K2×R3 （2）
wherein, K2Is the ratio between the feedback current Iref and the mirror bias current ISense.
Can be obtained from the formula (2):
ISense= VREF/（K2×R3） （3）
from formula (3):
IDD= VREF/（K1×K2×R3） （4）
wherein, K1Is the ratio between the mirror bias current ISense and the bias current IDD.
As can be seen from equation (4), the apparatus 1000 realizes stable control of the bias current IDD. The apparatus 1000 can suppress variations in the bias current IDD due to RFIN fluctuations of the input signal.
The current detector 12 and the rf amplifier output stage 11 can be packaged in the same chip and can be manufactured by the same process. Thus can make K1Can be relatively stable and is less influenced by temperature. Similarly, the feedback current generator 13 may also include various components packaged in the same chip and manufactured by the same process. Thus can make K2Can be relatively stable and is less influenced by temperature. Therefore, the bias current IDD controlled by the apparatus 1000 can be relatively stable and less affected by temperature. Meanwhile, the control effect of the bias current IDD can be less influenced by the chip process. The uniformity of the bias current IDD is high across a plurality of chips that are mass-produced including the device 1000. So that the yield of chip production, which may include the device 1000, is high.
Alternatively, the resistor R3 may be a high precision resistor. Alternatively, the device 1000 may be packaged inside a chip. In this case, the resistor R3 may be an off-chip high-precision resistor or an on-chip high-precision resistor. For example, resistor R3 may be an on-chip polysilicon resistor. The control accuracy of the bias current IDD can be further improved by utilizing the high-accuracy resistor R3, and the influence of the temperature on the bias current IDD is reduced. Alternatively, the resistor R3 may be replaced by a resistor network of resistors. Alternatively, the resistor R3 may comprise a circuit network including at least one of a resistor, an inductor, and a capacitor.
As shown in fig. 1, the bias voltage generator 14 may further include a three-terminal transistor P3. The three-terminal transistor P3 may be connected to an output terminal of the operational amplifier OP 1. The three-terminal transistor P3 may be used to power amplify the output signal of the operational amplifier OP 1. As shown in the exemplary embodiment, three-terminal transistor P3 may be a P-channel field effect transistor. Alternatively, the three-terminal transistor P3 may be replaced by an N-channel fet, or other type of unipolar transistor. Alternatively, the three-terminal transistor P3 may be replaced by a bipolar transistor. For example, it may be an NPN transistor or a PNP transistor. Alternatively, the three-terminal transistor P3 may be replaced by a local circuit composed of a plurality of three-terminal transistors.
As shown in fig. 1, the bias voltage generator 14 may further include a resistor R4 and a capacitor C1 connected in parallel. The resistor R4 and the capacitor C1 may be connected to the drain of a three terminal transistor P3 as shown in the exemplary embodiment. Resistor R4 and capacitor C1 may be used to filter out the ac component of the bias voltage excitation VG 1.
As shown in fig. 1, the apparatus 1000 may further include a reference voltage generator 15. The reference voltage generator 15 may be connected to an input terminal of the operational amplifier OP 1. The reference voltage generator 15 may be used to generate the reference voltage VREF.
As shown in example embodiments, the reference voltage generator 15 may include a second mirror current source circuit 151 and a third mirror current source circuit 152. The second mirror current source circuit 151 may include three-terminal transistors P4, P5, and P6. Wherein the three-terminal transistors P4, P5, and P6 may all be the same P-channel fets. Drains of the three-terminal transistors P4, P5, and P6 may be a mirror current terminal 1512, a source current terminal 1511, and a mirror current terminal 1513 of the second mirror current source circuit 151, respectively. Sources of the three-terminal transistors P4, P5, and P6 may be commonly connected to a power supply VDD, and gates of the three-terminal transistors P4, P5, and P6 may be commonly connected to a drain of the three-terminal transistor P5. Since the gate-source voltages of the three-terminal transistors P4, P5, and P6 are all the same, currents flowing through the mirror current terminal 1512, the source current terminal 1511, and the mirror current terminal 1513 can all be made equal.
The third mirror current source circuit 152 may include three-terminal transistors N4 and N5. Wherein the three-terminal transistors N4 and N5 may both be the same N-channel field effect transistor. The gates of the three-terminal transistors N4 and N5 may both be connected to the drain of the three-terminal transistor N4. The drains of the three-terminal transistors N4 and N5 may be the source current terminal 1521 and the mirror current terminal 1522 of the third mirror current source circuit 152, respectively. As shown in the example embodiment, the source of the three-terminal transistor N4 may be directly connected to signal ground, and the source of the three-terminal transistor N5 may be connected to signal ground through the resistor R6.
As shown in the example embodiment, the source current terminal 1511 of the second mirror current source circuit 151 may be connected with the mirror current terminal 1522 of the third mirror current source circuit 152. The source current terminal 1521 of the third mirror current source circuit 152 may be connected to the mirror current terminal 1512 of the second mirror current source circuit 151. The second mirror current source circuit 151 and the third mirror current source circuit 152 cooperate with each other, so that the currents flowing through the mirror current terminal 1512, the source current terminal 1511 and the mirror current terminal 1513 of the second mirror current source circuit 151 are all stabilized at a predetermined current value. The mirror current terminal 1513 may be connected to signal ground through a resistor R3. The voltage across resistor R5 may be made a preset voltage reference VREF.
As shown in the example embodiment, the reference source 151 may generate a positive temperature coefficient reference voltage VREF. As the temperature of the ptc reference source 151 increases, the output voltage reference VREF increases slightly. Therefore, the phenomenon of gain reduction of the amplifier due to noise caused by temperature rise can be compensated and improved.
As shown in fig. 1, the gate of the three-terminal transistor N22 of the current detector 12 and the three-terminal transistor N2 of the output stage of the rf amplifier output stage 11 may also be commonly connected to the second bias voltage driver VG 2. Optionally, a resistor R1 may also be included between the bias voltage driver VG1 and the gate of the three-terminal transistor N1 of the rf amplifier output stage 11. A resistor R2 may also be included between the bias voltage driver VG2 and the gate of the three-terminal transistor N2 of the rf amplifier output stage 11. Optionally, a capacitor may also be included between the gate of the three-terminal transistor N1 and the input signal RFIN. A capacitor may also be included between the gate of three terminal transistor N2 and signal ground.
As shown in fig. 1, optionally, the apparatus 1000 may also include a choke inductance L1. Optionally, the choke inductor L1 may be connected between the output terminal of the rf amplifier output stage 11 and the power supply VDD. Optionally, the apparatus 1000 may also include a matching circuit. The matching circuit may be connected to the output of the rf amplifier output stage 11.
Fig. 2 shows a schematic topology of a bias current control device according to another embodiment of the present application.
As shown in fig. 2, the apparatus 2000 may be used for bias current control of the rf amplifier output stage 21. The radio frequency amplifier output stage 21 may comprise at least one three terminal transistor. As shown in the example embodiment, the at least one three-terminal transistor included in the rf amplifier output stage 21 may be a three-terminal transistor Q1. The three-terminal transistor Q1 may be an NPN transistor. Alternatively, the three-terminal transistor Q1 can be replaced by a PNP transistor. Alternatively, the three-terminal transistor Q1 may also be a Heterojunction Bipolar Transistor (HBT). Alternatively, the three-terminal transistor Q1 may be another type of bipolar transistor. Alternatively, the three-terminal transistor Q1 may be replaced by a unipolar transistor.
As shown in fig. 2, the apparatus 2000 may include a current detector 22, a feedback current generator 23, and a bias voltage generator 24.
Wherein the current detector 22 is connected to the rf amplifier output stage 21. The current detector 22 may include at least one three-terminal transistor. Wherein the current detector 22 comprises at least one three-terminal transistor that can be a mirror image of at least one three-terminal transistor of the rf amplifier output stage 21. Further, the current detector 22 may comprise a mirror circuit of the radio frequency amplifier output stage 21. That is, the current detector 22 may comprise the same circuit parts as the rf amplifier output stage 21 topology and the input drive.
As shown in the exemplary embodiment, the current detector 22 also includes a three terminal transistor Q11. Alternatively, the three-terminal transistor Q11 and the three-terminal transistor Q1 may be the same type of transistor. As shown in the exemplary embodiment, the three-terminal transistor Q1 is an NPN transistor, and the three-terminal transistor Q11 is also an NPN transistor. Alternatively, the three-terminal transistor Q11 may be the same transistor as the three-terminal transistor Q1.
The three-terminal transistor Q11 may be mirrored with respect to the three-terminal transistor Q1. As shown in the exemplary embodiment, the base of the three terminal transistor Q11 is connected to the base of the three terminal transistor Q1, and is commonly connected to the bias voltage stimulus output by the bias voltage generator 24 and commonly connected to the input signal RFIN via a capacitor. The emitter of the three-terminal transistor Q11 and the emitter of the three-terminal transistor Q1 are commonly connected to signal ground.
In normal operation, the three-terminal transistors Q1 and Q11 are both in the amplification region. Since the base-emitter voltage difference is identical. The collector current of the three-terminal transistor Q11 is thus proportional to the collector current of the three-terminal transistor Q1. That is, the mirror bias current ISense is proportional to the bias current ICC of the rf amplifier output stage 21. The ratio of the mirror bias current ISense to the bias current ICC is comparable to the ratio of the beta values of the two transistors.
As shown in fig. 2, the feedback current generator 23 may be connected to the current detector 22. And may be used to replicate the mirrored bias current ISense as the feedback current Iref at a preset ratio. The feedback current generator 23 may be similar to the same-name components in fig. 1. And will not be described in detail herein.
As shown in fig. 2, the bias voltage generator 24 may be connected between the feedback current generator 23 and the current detector 22. And can generate bias voltage excitation according to the feedback current Iref output by the feedback current generator 23 and the reference voltage VREF. The bias voltage excitation may be applied to both the current detector 22 and the rf amplifier output stage 21.
The bias voltage generator 24 may constitute a feedback control circuit with the feedback current generator 23 and the current detector 22. The feedback control circuit may adjust the mirror bias current ISense of the current detector 22 to a preset current value. Since the rf amplifier output stage 21 is mirrored with the current detector 22. The feedback control circuit also adjusts the bias current ICC to a second predetermined current value.
As shown in fig. 2, the bias voltage generator 24 may include a resistor R3. The resistor R3 may be connected to the feedback current generator 23 and may convert the feedback current Iref output by the feedback current generator 23 into the feedback voltage VFB across the resistor R3.
As shown in fig. 2, the bias voltage generator 24 may further include an operational amplifier OP 1. The operational amplifier OP1 may be used to generate a bias voltage stimulus for the rf amplifier output stage 21 based on a comparison of the feedback voltage VFB and the reference voltage VREF.
As shown in fig. 2, the current detector 22, the feedback current generator 23, and the bias voltage generator 24 constitute a negative feedback circuit. The bias current of the rf amplifier output stage 21 may be automatically adjusted to a current value in a preset ratio to the reference voltage VREF. So that the bias current of the radio frequency amplifier output stage 21 may be unaffected by the input signal RFIN.
Similar to the device shown in fig. 1, the bias voltage generator 24 in the device 2000 may also include a three-terminal transistor P3 for power amplification. And may include a capacitor C1 and a resistor R4 for filtering out ac components. And will not be described in detail herein.
As shown in fig. 2, the device 2000 and the rf amplifier output stage 21 may use different power supplies. As shown in the exemplary embodiment, the supply power source used by the rf amplifier output stage 21 is a power source VCC. And the power supply of device 2000 may be power supply VDD.
As shown in fig. 2, the bias voltage generator 24 may optionally include a three-terminal transistor Q4 to enable cross-supply connection of the bias voltage. Alternatively, the three-terminal transistor Q4 may be a bipolar transistor. Further, the three-terminal transistor Q4 may be an NPN type transistor or a PNP type transistor. Alternatively, the three-terminal transistor Q4 may be a unipolar transistor. Further, the three-terminal transistor Q4 may be an N-channel fet or a P-channel fet.
As shown in the exemplary embodiment, the three-terminal transistor Q4 is an NPN transistor. The base of the three-terminal transistor Q4 can be connected with the three-terminal transistor P3 through the resistor R1. The collector of the three-terminal transistor Q4 may be connected to a power supply VCC. The emitter of the three-terminal transistor Q4 may be connected to the base of the three-terminal transistor Q1 in the rf amplifier output stage 21. Optionally, a capacitor C2 may be included between the base of the three terminal transistor Q1 and signal ground.
As shown in fig. 2, the bias voltage generator 24 may further include a clamping circuit. The clamp circuit may be used to ensure that the bias voltage output by the bias voltage generator 24 is within a reasonable range. This reasonable range does not damage the subsequent stage circuits including the rf amplifier output stage 21.
As shown in the exemplary embodiment, the clamp may be connected across the base of the three terminal transistor Q4 and signal ground. The clamp circuit may include three-terminal transistors Q1 and Q2. Wherein three-terminal transistors Q1 and Q2 may be connected in series. And the base and the collector of the three-terminal transistor Q1 can be in short circuit, and the base and the collector of the three-terminal transistor Q2 can be in short circuit. As shown in the exemplary embodiment, the three-terminal transistors Q1, Q2 may be NPN transistors.
Similar to the arrangement shown in fig. 1, the arrangement 2000 may also comprise a choke inductance L1 and a matching circuit. And will not be described in detail herein.
Fig. 3 shows a schematic diagram of the composition of a radio frequency amplifier according to another embodiment of the present application.
Alternatively, the rf amplifier 3000 may be an rf power amplifier. As shown in fig. 3, the radio frequency amplifier 3000 may include an output stage 31 and a bias current controller 32.
Wherein the output stage may comprise at least one three terminal transistor. The at least one transistor may be a unipolar transistor or a bipolar transistor. For example, the at least one transistor may include a transistor. The triode can be an NPN type triode or a PNP type triode. The at least one transistor may also include a field effect transistor. The field effect transistor can be an N-channel field effect transistor or a P-channel field effect transistor.
The bias current controller 32 may be any of the previously described bias current controllers. The bias current controller 32 may be a closed-loop control circuit composed of at least one of a current detector 321, a feedback current generator 322, and a bias voltage generator 323.
Wherein the current detector 321 may include at least one three-terminal transistor provided in mirror image with at least one three-terminal transistor in the output stage 31. Further, the current detector 321 may include a mirror circuit of the output stage 31, or may include a mirror circuit of a partial circuit of the output stage 31. Such as: the current detector 321 may comprise the same or similar topology as the output stage 31. And the current detector 321 may be connected to the same or similar input stimuli as the output stage 31. Since the current detector 321 has a mirror relationship with the output stage 31, the current flowing through the current detector 321 is equal to or in a preset proportional relationship with the current flowing through the output stage 31. So that the bias current collection of the output stage 31 can be achieved.
Alternatively, the current detector 321 may be integrated with the output stage 31 in the same chip, and the same process may be adopted. The transistors included in the current detector 321 and the transistors included in the output stage 31 may have highly similar temperature characteristics and other characteristics. Therefore, when the current detector 321 is used to detect the bias current of the output stage 31, the temperature stability is good.
The feedback current generator 322 may include a first mirror current source circuit. The source current terminal of the first mirror current source circuit may be connected to the current detector 321, and the current flowing through the current detector 321 may be copied to the mirror current terminal of the first mirror current source circuit in a predetermined ratio. And may output the mirror current terminal current of the first mirror current source as a feedback current to the bias voltage generator 323.
The first mirror current source circuit comprises at least two three-terminal transistors which can be arranged in the same chip. The characteristics of at least two three-terminal transistors of the first mirror current source circuit are highly uniform. Therefore, the feedback current generated by the feedback current generator 322 has better temperature stability and can better reflect the bias current of the output stage 31. The bias current of the output stage 31 can be very accurately collected using the cascaded current detector 321 and feedback current generator 322. Since the current detector 321 and the feedback current generator 322 have better temperature stability, the bias current of the output stage 31 controlled by the bias current controller 32 with the current detector 321 and the feedback current generator 322 as current feedback has better temperature stability. Meanwhile, the current detector 321 and the feedback current generator 322 have very simple structures and are easy to implement.
The bias voltage generator 323 may be connected between the feedback current generator 322 and the current detector 321. And may constitute a negative feedback control circuit with the current detector 321 and the feedback current generator 322. So that the mirror bias current of the current detector 321 can be adjusted to a preset value. The output of the bias voltage generator 323 is also connected to the output stage 31. Since the output stage 31 and the current detector 321 are mirror images. The bias current of the output stage 31 and the current detector 321 are also mirror images. Thus, the bias voltage generator 323 simultaneously achieves an efficient control of the bias current of the output stage 31.
As shown in the exemplary embodiment, bias current controller 32 may include a reference source 324. The reference source 324 may be connected to a bias voltage generator 323. The input of the closed loop circuit is given, and the preset value is generated.
The present application further provides an electronic device including any one of the foregoing bias current control devices, or including any one of the foregoing radio frequency amplifiers.
The present application further provides an embodiment of a chip, which includes any one of the foregoing bias current control devices, or includes any one of the foregoing radio frequency amplifiers.
By using the bias current control device, the radio frequency amplifier, the electronic equipment and the chip, the bias current of the output stage of the radio frequency amplifier can be relatively accurately detected by taking the mirror circuit of the output stage of the radio frequency amplifier as a current detector, and the bias current can be copied into the mirror bias current according to a preset proportion. And the mirror bias current may be copied to the feedback current in a predetermined ratio using a feedback current generator including a mirror current source circuit. The bias current of the output stage of the radio frequency amplifier can be copied into the feedback current relatively accurately by using the method. And the bias voltage generator can control the bias current of the output stage of the radio frequency amplifier to be a preset current value according to the feedback current.
In the above scheme, the bias current, the mirror bias current and the feedback current of the output stage of the rf amplifier generated by the apparatus may be the positive temperature coefficient current. Therefore, when the temperature rises, the transconductance of the transistor of the radio frequency amplifier can be ensured to be compensated. And the phenomenon that the gain of the amplifier is reduced when the temperature is increased is improved, and the performance of the amplifier at high temperature is guaranteed.
On the other hand, at normal temperature, the consistency of the bias current control device, the radio frequency amplifier, the electronic device and the chip which are produced in batch can be relatively high. The product yield and the mass production stability are improved.
In the above scheme, since the signal is transferred through at least one mirror current circuit, the bias current generated by the above scheme can be less affected by the transistor process. Meanwhile, the bias current control device is realized by a pure analog circuit, the topological structure is relatively simple, and the realization cost is relatively low.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the description of the embodiments is only intended to facilitate the understanding of the methods and their core concepts of the present application. Meanwhile, a person skilled in the art should, according to the idea of the present application, change or modify the embodiments and applications of the present application based on the scope of the present application. In view of the above, the description should not be taken as limiting the application.
Claims (11)
1. A bias current control device, comprising:
the current detector is connected with a preset radio frequency amplifier output stage, the bias current of the radio frequency amplifier output stage is copied in a preset proportion to be a mirror image bias current, the current detector and the radio frequency amplifier output stage adopt the same process and are packaged in the same chip, and the bias current and the mirror image bias current are both positive temperature coefficient currents;
the feedback current generator copies the mirror bias current in a preset proportion to serve as feedback current, and comprises a first mirror current source circuit;
and the bias voltage generator generates a bias voltage for the output stage of the radio frequency amplifier according to the feedback current and a reference voltage with a positive temperature coefficient, and comprises a first operational amplifier which generates the bias voltage according to the difference value of the feedback voltage generated by the feedback current and the reference voltage.
2. The bias current control device according to claim 1,
the radio frequency amplifier output stage comprises at least one three-terminal transistor;
the current detector comprises at least one three-terminal transistor;
the current detector comprises at least one three-terminal transistor which is arranged in a mirror image manner with at least one three-terminal transistor comprised by the output stage of the radio frequency amplifier.
3. The bias current control device according to claim 2,
the current detector comprises a mirror circuit of the preset radio frequency amplifier output stage.
4. The bias current control device according to claim 1, wherein:
the source current terminal of the first mirror current source circuit is connected to the current detector,
and the mirror current end of the first mirror current source circuit is connected with the bias voltage generator.
5. The bias current control device according to claim 1, further comprising:
a reference voltage generator for generating the reference voltage.
6. The bias current control device according to claim 5, wherein the reference voltage generator is connected to the second mirror current source circuit and the third mirror current source circuit,
wherein a source current terminal of the second mirror current source circuit is connected to a mirror current terminal of the third mirror current source circuit,
and the source current end of the third mirror image current source circuit is connected with the mirror image current end of the second mirror image current source circuit.
7. The bias current control device according to claim 1, further comprising:
a first choke inductance connected to the RF amplifier output stage.
8. The bias current control device according to claim 1, further comprising:
and the matching circuit is connected with the output stage of the radio frequency amplifier.
9. A radio frequency amplifier, comprising:
an output stage;
the bias current control device of any one of claims 1-8, connected to said output stage.
10. An electronic device, comprising:
the bias current control device of any one of claims 1 to 8, or comprising the radio frequency amplifier of claim 9.
11. A chip, comprising:
the bias current control device of any one of claims 1 to 8, or comprising the radio frequency amplifier of claim 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110951870.7A CN113411055B (en) | 2021-08-19 | 2021-08-19 | Bias current control device, radio frequency amplifier, electronic device and chip |
| PCT/CN2022/078248 WO2023019905A1 (en) | 2021-08-19 | 2022-02-28 | Bias current control device, radio frequency amplifier, electronic device, and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202110951870.7A CN113411055B (en) | 2021-08-19 | 2021-08-19 | Bias current control device, radio frequency amplifier, electronic device and chip |
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| CN113411055A CN113411055A (en) | 2021-09-17 |
| CN113411055B true CN113411055B (en) | 2021-12-28 |
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| CN202110951870.7A Active CN113411055B (en) | 2021-08-19 | 2021-08-19 | Bias current control device, radio frequency amplifier, electronic device and chip |
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| CN113411055B (en) * | 2021-08-19 | 2021-12-28 | 深圳飞骧科技股份有限公司 | Bias current control device, radio frequency amplifier, electronic device and chip |
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Also Published As
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| WO2023019905A1 (en) | 2023-02-23 |
| CN113411055A (en) | 2021-09-17 |
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