CN116994627A

CN116994627A - Method and device for testing memory chip, memory medium and electronic equipment

Info

Publication number: CN116994627A
Application number: CN202210451608.0A
Authority: CN
Inventors: 刘�东
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2023-11-03

Abstract

The disclosure provides a testing method of a memory chip, a testing device of the memory chip, a computer readable storage medium and electronic equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: writing test data into a memory unit of the memory chip; activating a memory cell with a non-adjacent word line in the memory chip by taking a preset time length as the word line starting time of the memory chip, wherein the preset time length is longer than the standard word line starting time of the memory chip, and the preset time length is obtained by setting a tRAS time sequence parameter; and comparing the storage data with the test data by reading the storage data of the storage units in the storage chip, and determining the test result of the storage chip. The method and the device can improve the testing efficiency of the memory chip.

Description

Method and device for testing memory chip, memory medium and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and apparatus for testing a memory chip, a computer readable storage medium, and an electronic device.

Background

Memory chips are an important component of many electronic products. In the production process of the memory chip, the testing technology is an important link for detecting the product yield and the use function of the memory chip.

The test of the memory chip includes various test types such as a reliability test, an environment test, a function test, a read-write test, and the like. The read-write test needs to scan all memory cells in the memory chip, and along with the continuous improvement of the memory capacity of the memory chip and the complexity of the process, the failure modes of the memory chip are more and more, and how to test the memory chip completely and efficiently becomes the study content of the key attention of the technicians.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure provides a testing method of a memory chip, a testing device of the memory chip, a computer readable storage medium and an electronic device, so as to at least improve the problems of low testing efficiency and low integrity of the memory chip in the prior art to a certain extent.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.

According to a first aspect of the present disclosure, there is provided a method of testing a memory chip, the method comprising: writing test data into a memory unit of the memory chip; activating a memory cell with a non-adjacent word line in the memory chip by taking a preset time length as the word line starting time of the memory chip, wherein the preset time length is longer than the standard word line starting time of the memory chip, and the preset time length is obtained by setting a tRAS time sequence parameter; and comparing the storage data with the test data by reading the storage data of the storage units in the storage chip, and determining the test result of the storage chip.

In an exemplary embodiment of the present disclosure, the writing test data into the memory cells of the memory chip includes: and writing the test data into the memory cells on each word line of the memory chip one by one so as to write one bit of binary data into each memory cell on each word line of the memory chip.

In an exemplary embodiment of the present disclosure, the writing the test data into the memory cells on each word line of the memory chip one by one includes: opening a current word line of the memory chip before writing the test data into a memory cell on the current word line each time; and writing the test data into the memory cells on the current word line according to the unit burst length, closing the current word line when the data writing of the memory cells corresponding to the unit burst length is completed each time, until the data writing of all the memory cells on the current word line is completed, and then writing the test data into the memory cells on the next word line of the memory chip.

In an exemplary embodiment of the present disclosure, the activating a memory cell having a non-adjacent word line in the memory chip with a preset duration as a word line on time of the memory chip includes: taking preset duration as word line opening time of the memory chip, and respectively repeatedly activating memory cells with even word line numbers and memory cells with odd word line numbers in the memory chip; and after the repeated activation of any one of the memory cells with even digital line numbers and the memory cells with odd digital line numbers is completed, reading the memory data of all the memory cells in the memory chip, and comparing the memory data with the test data to determine the test result of the memory chip.

In an exemplary embodiment of the present disclosure, the test data includes a plurality of different sets of data topologies, the method further comprising: writing each group of data topology into all storage units of the storage chip respectively; after writing of any one set of data topologies in the memory cells of the memory chip is completed, executing a step of activating the memory cells with non-adjacent word lines in the memory chip; and reading the storage data of the storage units in the storage chip, comparing the storage data with any one group of data topologies, and determining the test result of the storage chip about the any one group of data topologies.

In an exemplary embodiment of the present disclosure, each set of data topologies includes a plurality of different binary sequences therein, and when each set of data topologies is written to all memory cells of the memory chip separately, the method further includes: all memory cells with odd number word lines and even number word lines in the memory chip are respectively determined to obtain a first memory cell and a second memory cell; and writing different binary sequences in any group of data topologies into the first storage unit and the second storage unit respectively so as to write different binary sequences in the storage units of two adjacent word lines in the storage chip.

In an exemplary embodiment of the present disclosure, after writing different binary sequences in the arbitrary set of data topologies to the first storage unit and the second storage unit, respectively, the method further comprises: respectively activating the first memory cell or the second memory cell by taking the preset duration as the word line starting time of the memory chip; and when the activation operation of the first storage unit or the second storage unit is completed, the storage data of all the storage units in the storage chip are read, the storage data are compared with the corresponding binary sequences in the arbitrary set of data topology, and the test result of the storage chip is determined.

In one exemplary embodiment of the present disclosure, the plurality of sets of data topologies includes a first data topology having two binary sequences, with adjacent data bits of data being different in each binary sequence of the first data topology.

In an exemplary embodiment of the disclosure, the writing the different binary sequences in the arbitrary set of data topologies to the first storage unit and the second storage unit, respectively, includes: writing a first binary sequence in the first data topology to the first storage unit and writing a second binary sequence in the first data topology to the second storage unit; or writing a second binary sequence in the first data topology to the first storage unit and writing a first binary sequence in the first data topology to the second storage unit.

In one exemplary embodiment of the present disclosure, the plurality of sets of data topologies includes a second data topology having two binary sequences, wherein the two binary sequences are an all 0 sequence and an all 1 sequence, respectively.

In an exemplary embodiment of the disclosure, the writing the different binary sequences in the arbitrary set of data topologies to the first storage unit and the second storage unit, respectively, includes: writing an all 0 sequence in the second data topology to the first storage unit and an all 1 sequence in the second data topology to the second storage unit; or writing an all 1 sequence in the second data topology to the first storage unit and an all 0 sequence in the second data topology to the second storage unit.

In an exemplary embodiment of the present disclosure, the method further comprises: when the binary sequences written in the first storage unit and the second storage unit are updated, respectively activating the first storage unit or the second storage unit by taking a preset duration as the word line starting time of the storage chip; after the activation of the first storage unit or the second storage unit is completed, the storage data of all storage units in the storage chip are read, the storage data are compared with binary sequences in corresponding data topologies, and the test result of the storage chip is determined.

In an exemplary embodiment of the present disclosure, the determining the test result of the memory chip by reading the memory data of the memory cells in the memory chip, comparing the memory data with the test data includes: and reading the storage data of the storage units in the storage chip, comparing the storage data with the test data bit by bit, and determining whether each storage unit in the storage chip has a read-write error or not and the number of bits with the read-write error so as to obtain the test result.

In an exemplary embodiment of the present disclosure, the reading the storage data of the storage unit in the storage chip includes: opening a current word line of the memory chip before each reading of memory data of a memory cell on the current word line; and in the memory cells on the current word line, reading the memory data in the memory cells according to the unit burst length, closing the current word line when the data reading of the memory cells corresponding to the unit burst length is completed each time, until the data reading of all the memory cells on the current word line is completed, and then reading the memory data of the memory cells on the next word line of the memory chip.

In an exemplary embodiment of the present disclosure, when a memory cell having a non-adjacent word line in the memory chip is activated for a word line on time of the memory chip with a preset duration, the method further includes: and reducing the word line closing voltage of the memory chip to enhance the GIDL effect between the memory cells of adjacent word lines in the memory chip.

In one exemplary embodiment of the present disclosure, after writing the test data into the memory cells of the memory chip, the method further includes: and refreshing the memory cells of the memory chip according to a preset refreshing period.

According to a second aspect of the present disclosure, there is provided a test apparatus of a memory chip, the apparatus comprising: the writing module is used for writing test data into the memory unit of the memory chip; the activation module is used for activating the memory cells with non-adjacent word lines in the memory chip by taking the preset time length as the word line opening time of the memory chip, wherein the preset time length is longer than the standard word line opening time of the memory chip, and the preset time length is obtained by setting a tRAS time sequence parameter; and the comparison module is used for comparing the storage data with the test data by reading the storage data of the storage units in the storage chip to determine the test result of the storage chip.

In one exemplary embodiment of the present disclosure, the writing module is configured to write the test data into the memory cells on each word line of the memory chip one by one, so that one bit of binary data is written into each memory cell on each word line of the memory chip.

In an exemplary embodiment of the present disclosure, the writing module is further configured to turn on a current word line of the memory chip before writing the test data into a memory cell on the current word line each time, write the test data into the memory cell according to a unit burst length in the memory cell on the current word line, and turn off the current word line each time data writing of the memory cell corresponding to the unit burst length is completed, until data writing of all the memory cells on the current word line is completed, and then write the test data into a memory cell on a next word line of the memory chip.

In an exemplary embodiment of the present disclosure, the activation module is configured to repeatedly activate, with a preset duration as a word line on time of the memory chip, a memory cell having an even word line number and a memory cell having an odd word line number in the memory chip, and after completing the repeated activation of any one of the memory cell having the even word line number and the memory cell having the odd word line number, the comparison module is configured to read memory data of all the memory cells in the memory chip, and compare the memory data with the test data to determine a test result of the memory chip.

In an exemplary embodiment of the present disclosure, the test data includes a plurality of different sets of data topologies, and the writing module is configured to write each set of data topologies into all memory cells of the memory chip, respectively; the activation module is used for executing the step of activating the memory cells with non-adjacent word lines in the memory chip after the writing of any group of data topologies in the memory cells of the memory chip is completed; the comparison module is used for reading the storage data of the storage unit in the storage chip, comparing the storage data with the arbitrary set of data topology, and determining the test result of the storage chip about the arbitrary set of data topology.

In an exemplary embodiment of the present disclosure, each set of data topologies includes a plurality of different binary sequences, and when each set of data topologies is written into all memory cells of the memory chip, the writing module is further configured to determine all memory cells having an odd word line number and an even word line number in the memory chip, respectively, to obtain a first memory cell and a second memory cell, and write the different binary sequences in any set of data topologies into the first memory cell and the second memory cell, respectively, so as to write the different binary sequences into the memory cells of two adjacent word lines in the memory chip.

In an exemplary embodiment of the present disclosure, after writing different binary sequences in the arbitrary set of data topologies into the first memory cell and the second memory cell, respectively, the activation module is further configured to activate the first memory cell or the second memory cell, respectively, for a word line on time of the memory chip with a preset duration; and when the activation operation of the first storage unit or the second storage unit is completed, the comparison module is also used for reading the storage data of all the storage units in the storage chip, comparing the storage data with the corresponding binary sequences in any one group of data topologies, and determining the test result of the storage chip.

In an exemplary embodiment of the present disclosure, the writing module is further configured to write a first binary sequence in the first data topology to the first storage unit and a second binary sequence in the first data topology to the second storage unit, or write a second binary sequence in the first data topology to the first storage unit and a first binary sequence in the first data topology to the second storage unit.

In an exemplary embodiment of the present disclosure, the writing module is further configured to write an all 0 sequence in the second data topology to the first storage unit and an all 1 sequence in the second data topology to the second storage unit, or write an all 1 sequence in the second data topology to the first storage unit and an all 0 sequence in the second data topology to the second storage unit.

In an exemplary embodiment of the present disclosure, the activation module is further configured to activate the first memory cell or the second memory cell respectively, with a preset duration being a word line on time of the memory chip, when the binary sequences written in the first memory cell and the second memory cell are updated; and the comparison module is also used for reading the storage data of all the storage units in the storage chip after the first storage unit or the second storage unit is activated, comparing the storage data with the binary sequence in the corresponding data topology, and determining the test result of the storage chip.

In an exemplary embodiment of the disclosure, the comparison module is further configured to read storage data of storage units in the storage chip, compare the storage data with the test data bit by bit, and determine whether a read-write error occurs in each storage unit in the storage chip and a bit number of the read-write error occurs, so as to obtain the test result.

In an exemplary embodiment of the present disclosure, the comparison module is further configured to turn on a current word line of the memory chip before each reading of the stored data of the memory cells on the current word line, read the stored data in the memory cells according to the unit burst length in the memory cells on the current word line, and turn off the current word line each time the data reading of the memory cells corresponding to the unit burst length is completed, until the data reading of all the memory cells on the current word line is completed, and then read the stored data of the memory cells on a next word line of the memory chip.

In an exemplary embodiment of the present disclosure, when the memory cells having non-adjacent word lines in the memory chip are activated with a preset duration as the word line on time of the memory chip, the activation module is further configured to reduce the word line off voltage of the memory chip to enhance the GIDL effect between the memory cells of the adjacent word lines in the memory chip.

In an exemplary embodiment of the present disclosure, after writing the test data into the memory cells of the memory chip, the activation module is further configured to perform a refresh process on the memory cells of the memory chip according to a preset refresh period.

According to a third aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the test method of any one of the above-described memory chips.

According to a fourth aspect of the present disclosure, there is provided an electronic device comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform any one of the above-described memory chip testing methods via execution of the executable instructions.

The present disclosure has the following beneficial effects:

in summary, according to the method for testing a memory chip, the device for testing a memory chip, the computer-readable storage medium, and the electronic device in this exemplary embodiment, test data may be written into a memory cell of the memory chip, a memory cell having a non-adjacent word line in the memory chip is activated with a preset duration as a word line on time of the memory chip, and a test result of the memory chip is determined by reading the memory data of the memory cell in the memory chip and comparing the memory data with the test data. The preset time length is longer than the standard word line opening time of the memory chip, and the preset time length is obtained by setting the tRAS time sequence parameter. On one hand, the scheme can determine the test result of the memory chip by reading the memory data of the memory cells in the memory chip and comparing the memory data with the test data, and complete the read-write performance test of the memory chip; on the other hand, by taking the preset duration as the word line opening time of the memory chip, the memory cells with non-adjacent word lines in the memory chip are activated, so that the memory cells with non-adjacent word lines can be activated for a long time, the probability of row leakage can be increased, the problem of row leakage can be displayed as soon as possible, and the test efficiency of the memory chip can be improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely some embodiments of the present disclosure and that other drawings may be derived from these drawings without undue effort.

Fig. 1 is a flowchart showing a test method of a memory chip in the present exemplary embodiment;

fig. 2 shows a sub-flowchart of a test method of a memory chip in the present exemplary embodiment;

fig. 3 shows an example of test data in the present exemplary embodiment;

fig. 4 is a sub-flowchart showing another test method of a memory chip in the present exemplary embodiment;

fig. 5 is a flowchart showing another test method of a memory chip in the present exemplary embodiment;

fig. 6 is a block diagram showing a structure of a test apparatus of a memory chip in the present exemplary embodiment;

Fig. 7 illustrates a computer-readable storage medium for implementing the above-described method in the present exemplary embodiment;

fig. 8 shows an electronic device for implementing the above method in the present exemplary embodiment.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The exemplary embodiment of the disclosure first provides a method for testing a memory chip, which includes writing test data into memory cells of the memory chip, activating memory cells having non-adjacent word lines in the memory chip with a preset duration greater than a standard word line on time as the word line on time of the memory chip, further reading the memory data in the memory cells, and comparing the test data with the memory data to determine a test result of the memory chip. In the present exemplary embodiment, the memory chip may be a DRAM (Dynamic Random Access Memory ).

Fig. 1 shows a flow of the present exemplary embodiment, which may include the following steps S110 to S130:

and S110, writing test data into the memory cells of the memory chip.

The memory cell of the memory chip is a cell having functions of storing data and reading and writing data. In general, one memory chip may include a plurality of memory cells. Structurally, each memory cell is composed of a transistor and a capacitor, and whether a binary bit is 0 or 1 can be represented by the number of the capacitors. The test data refers to data written into the memory cells for testing the read/write function of the memory chip. Since the memory chip stores data in binary form, the test data may also be a binary sequence having a certain data bit length, that is, the test data may be any sequence composed of 0 and 1, such as an all 0 sequence or an all 1 sequence, a mixed sequence, or the like. In addition, the sequence length of the test data may be set to a fixed length according to the number of memory cells of the memory chip, such as the number of rows or columns, or may be set directly to an arbitrary length.

In order to detect the read-write performance of each memory cell in the memory chip, test data may be written in the memory cells of the memory chip first. For example, a binary sequence in test data may be written to each memory cell of a memory chip in sequence in a split manner such that each memory cell writes 1 bit of data, i.e., "0" or "1". Meanwhile, when writing test data into the memory cells of the memory chip, the test data may also be written into the memory cells according to the relationship between the sequence length of the binary sequence corresponding to the test data and the total number of the memory cells, for example, assuming that the sequence length N of the binary sequence corresponding to the test data is smaller than the total number M of the memory cells, at this time, the same test data may be repeatedly written in the order of the memory cells, i.e., a group of test data is written into every N memory cells, so that 1 bit of binary data is written into each memory cell. Wherein M and N are positive integers.

In particular, in an alternative embodiment, test data may be written to memory cells on each word line of the memory chip one by one, such that one bit of binary data is written to each memory cell on each word line of the memory chip.

In a memory chip, for example, memory cells may be arranged as a memory array made up of a plurality of rows and columns. In a memory array, a number of memory cells form a "word", also called an information cell, and an address decoder has n address input lines and 2n decoding output lines, each of which is a word line. When writing test data into the memory cells of the memory chip, the test data may be written into the memory cells on each word line of the memory chip one by one, so that one bit of binary data may be written into the memory cells on each word line, for example, the test data may be written into the memory cells of each numbered word line in turn according to the number of the word line of the memory chip, which is a symbol uniquely identifying each word line, so that each memory cell is written with 1 bit of binary data. By the method, the test data can be written into the memory cells of each word line, and the possibility of write omission of the test data is avoided.

Further, in order to improve the writing efficiency of the test data, in an alternative embodiment, as shown in fig. 2, the following method may be further performed:

in step S210, the current word line is turned on before each writing of test data into the memory cells on the current word line of the memory chip.

Step S220, writing test data into the memory cells according to the unit burst length in the memory cells on the current word line, closing the current word line when the data writing of the memory cells corresponding to the unit burst length is completed each time, until the data writing of all the memory cells on the current word line is completed, and then writing the test data into the memory cells on the next word line of the memory chip.

The unit Burst Length (Burst Length) refers to the number of memory cells involved in continuous data transmission in adjacent memory cells on the same word line, and in this transmission mode, after a row address is given, a memory chip to be tested can automatically perform a read operation on a corresponding number of memory cells in sequence without continuously providing a column address by a controller, as long as a start column address and the unit Burst Length are specified.

When writing test data in a write-by-word line manner, for a current word line performing a write operation at a current time, the current word line may be turned on first, and then the test data may be written into memory cells in the current word line in a unit burst length, for example, assuming that the unit burst length is 8, x (x > 7) memory cells in total in the current word line WL0 may be written into the first 8 memory cells in the current word line WL0, that is, the memory cells 0 to 7 after the current word line is turned on. And then closing the current word line after completing the writing of the test data of one group of memory cells corresponding to the unit burst length, restarting the current word line, continuing to write the test data into the other group of memory cells corresponding to the unit burst length of the current word line, for example, writing the test data into the memory cells 8-15 in the current word line WL0, continuing to close the current word line after completing the writing, restarting again, and executing the writing of the test data of the rest memory cells according to the unit burst length until the data writing of all the memory cells on the current word line is completed, and writing the test data into the memory cells on the new word lines WL1 and WL 2.

By the method, each word line can be controlled to write test data into a plurality of memory cells corresponding to the unit burst length at one time without writing one by one, so that the writing efficiency of the test data can be improved, and meanwhile, the word lines are closed and restarted after each time of writing of the test data is finished, the interference between adjacent memory cells can be reduced, and the correctness of the written data is ensured.

To adequately detect the read-write performance of the memory chip, and ensure the integrity and integrity of the test memory chip, in an alternative embodiment, the test data may include multiple sets of different data topologies. The data topologies refer to data structures of test data, each data topology can comprise one or more binary sequences, and for two data topologies, if at least one binary sequence in the two data topologies is different, or the binary sequences in the two data topologies are the same, but the sequence of the binary sequences is different, the two data topologies can be considered to be different. In this case, each set of data topologies may be written separately into all memory cells of the memory chip when writing test data. For example, each set of data topology may be written into the storage units of the memory chip in sequence according to the sequence of the plurality of sets of data topologies, and after any set of data topology is written into the storage units of the memory chip, the test performance of the memory chip may be analyzed to determine the test result corresponding to the set of data topologies.

In particular, in an alternative embodiment, a plurality of different binary sequences may be included in each set of data topologies, for example, in the test data example shown in fig. 3, the test data may include data topology 1, data topology 2, data topology 3, and data topology 4, with two different binary sequences included in each set of data topologies. In writing each set of data topologies into all memory cells of the memory chip, respectively, the following method may be performed:

all memory cells with odd number word lines and even number word lines in the memory chip are respectively determined to obtain a first memory cell and a second memory cell;

and respectively writing different binary sequences in any group of data topologies into the first storage unit and the second storage unit so as to write different binary sequences into the storage units of two adjacent word lines in the storage chip.

Taking data topology 1 as an example, a first binary sequence may be written into a memory cell having an odd word line number in the memory chip, i.e., a first memory cell, and a second binary sequence may be written into a memory cell having an even word line number in the memory chip, i.e., a second memory cell. By the method, the test data written in the two adjacent word lines are different, so that the coupling effect between the memory cells of the adjacent word lines can be enhanced, and the test accuracy is improved.

In an alternative embodiment, the plurality of sets of data topologies may include a first data topology having two binary sequences, with adjacent data bits of different data in each binary sequence of the first data topology. For example, the first data topology may be data topology 1 and data topology 2 as shown in fig. 3, wherein two binary sequences are included in each data topology, and the data of adjacent data bits are different, such as two binary sequences "10101010" and "01010101" in data topology 1, and the data of adjacent data bits are 0 and 1.

For the first data topology, in an alternative embodiment, test data may be written to the memory cells of the memory chip by:

writing a first binary sequence in a first data topology into a first memory cell and writing a second binary sequence in the first data topology into a second memory cell; or writing a second binary sequence in the first data topology to the first memory cell and writing the first binary sequence in the first data topology to the second memory cell.

For example, for data topology 1, a first binary sequence "10101010" may be written into a first memory cell, i.e., a memory cell with an odd-numbered word line, a second binary sequence "01010101" may be written into a second memory cell, i.e., a memory cell with an even-numbered word line, or a first binary sequence "10101010" may be written into a second memory cell, i.e., a memory cell with an even-numbered word line, a second binary sequence "01010101" may be written into a first memory cell, i.e., a memory cell with an odd-numbered word line. In the writing mode, the test data written by the memory cells of two adjacent word lines are different, and from the distribution of the written data in the memory array, the data written by the upper and lower memory cells, the left and right memory cells of the memory cells written with 0 are 1, and the data written by the upper and lower memory cells, the left and right memory cells of the memory cells written with 1 are 0.

In an alternative embodiment, the plurality of sets of data topologies may include a second data topology having two binary sequences, wherein the two binary sequences are an all 0 sequence and an all 1 sequence, respectively. For example, the second data topology may be data topology 3 and data topology 4 as shown in fig. 3, both of which include two binary sequences, namely "00000000" and "11111111".

For the second data topology, in an alternative embodiment, the second data topology may be written into the memory cells of the memory chip by:

writing the all 0 sequences in the second data topology into the first storage unit, and writing the all 1 sequences in the second data topology into the second storage unit; or write an all 1 sequence in the second data topology to the first storage unit and an all 0 sequence in the second data topology to the second storage unit.

For example, assuming that the second data topology is data topology 4, the all 0 sequence "00000000" may be written into the first memory cell, that is, the memory cell having the odd-numbered word line, the all 1 sequence "11111111" may be written into the second memory cell, that is, the memory cell having the even-numbered word line, or the all 1 sequence "11111111" may be written into the first memory cell, that is, the memory cell having the odd-numbered word line, and the all 0 sequence "00000000" may be written into the second memory cell, that is, the memory cell having the even-numbered word line. According to the method, the test data written by the memory cells of two adjacent word lines are different, and from the view of the distribution of the write data in the memory array, the data written by the memory cells above and below the memory cells written with 0 are 1, the data written by the memory cells below and above the memory cells written with 1 are 0, and the data written by the memory cells below and above the memory cells written with 1 are 1.

Further, due to the inherent properties of the capacitance in which data is stored in the memory chip, the data stored in the capacitor may be gradually lost with time, temperature, and the like. Therefore, in order to maintain the storage of the write data in the memory cells, in an alternative embodiment, after the test data is written in the memory cells of the memory chip, the memory cells of the memory chip may be subjected to refresh processing according to a preset refresh period. The preset refresh period may be defined according to the test requirement, for example, may be set to 100 μs. The method can realize continuous storage of the test data in the storage chip through refreshing processing, and avoid errors of the test result due to external reasons.

And S120, activating the memory cells with non-adjacent word lines in the memory chip by taking the preset duration as the word line opening time of the memory chip.

The preset time length is longer than the standard word line opening time of the memory chip, and the preset time length is obtained by setting the tRAS time sequence parameter. the tRAS timing parameter refers to the row activation time, i.e., the minimum number of clock cycles required between the row activation command and the issuing of the precharge command; the standard word line on time refers to the standard time between the row activate command and the issue of the precharge command.

After the test data is written into the memory cells of the memory chip, the preset duration can be used as the word line opening time of the memory chip, and the memory cells with non-adjacent word lines in the memory chip are activated, namely, the memory cells with non-adjacent word lines in the memory chip are repeatedly opened according to the word line opening time. That is, the memory cells of even word lines or the memory cells of odd word lines in the memory chip are turned on every preset time period, so that the periodic activation of the memory cells of non-adjacent word lines is realized. By the method for continuously activating the memory cells of the non-adjacent word lines, the probability of row leakage can be increased, so that the problem of row leakage can be displayed as soon as possible, and the test efficiency of the memory chip can be improved.

Specifically, in an alternative embodiment, step S120 may be performed to repeatedly activate the memory cells having even numbers and the memory cells having odd numbers in the memory chip by taking the preset duration as the word line on time of the memory chip.

For example, the memory cells with even-numbered word lines and the memory cells with odd-numbered word lines in the memory chip may be repeatedly activated at intervals in sequence with a preset duration as the word line on time of the memory chip, or the memory cells with even-numbered word lines in the memory chip may be repeatedly activated until a preset number of times is reached, and then the memory cells with odd-numbered word lines in the memory chip may be repeatedly activated until the same preset number of times is reached, so that the memory cells with even-numbered word lines and the memory cells with odd-numbered word lines are continuously activated.

As described above, in order to fully detect the read-write performance of the memory chip and ensure the integrity and integrity of the test memory chip, the test data may include multiple sets of different data topologies, and each set of data topologies may be written into all the memory cells of the memory chip when the test data is written. In this case, in step S120, the step of activating memory cells having non-adjacent word lines in the memory chip may be performed after the writing of any one set of data topologies in the memory cells of the memory chip is completed. For example, when writing any data topology as shown in fig. 3 into the memory cells of the memory chip, the memory cells of the memory chip having non-adjacent word lines may be repeatedly activated with a preset duration as the word line on time of the memory chip, such as by activating the memory cells of the odd word lines first and then activating the memory cells of the even word lines, at intervals.

Since each set of data topologies may comprise two binary sequences, different binary sequences may be written to the first and second memory cells, respectively. Based on this, in an alternative embodiment, the first memory cell or the second memory cell may be activated respectively with a preset duration as a word line on time of the memory chip. For example, the first memory cell and the second memory cell may be activated sequentially with a preset duration as a word line on time of the memory chip, or the first memory cell may be activated repeatedly within a plurality of preset durations, and then the second memory cell may be activated repeatedly within another plurality of preset durations, thereby completing the repeated activation of non-adjacent word lines.

Further, in an alternative embodiment, the following method may also be performed:

when the binary sequences written in the first memory cell and the second memory cell are updated, the first memory cell or the second memory cell is activated respectively by taking the preset duration as the word line opening time of the memory chip. At this time, the first memory cell having the odd word line number or the second memory cell having the even word line number is repeatedly activated only when the data written in the memory cells of the entire memory chip is changed, for example, when a new data topology is written in the memory cells of the memory chip.

In addition, in an alternative embodiment, when the word line on time of the memory chip is set to be the preset time length, and the memory cells with non-adjacent word lines in the memory chip are activated, the word line off voltage of the memory chip can be reduced, so that the GIDL (Gate-Induced Drain Leakage) effect between the memory cells with adjacent word lines in the memory chip is enhanced. The word line closing voltage refers to a voltage value of a current word line when the current word line is closed. By reducing the word line closing voltage of the memory chip and increasing the GIDL effect between the memory cells of adjacent word lines in the memory chip, the leakage condition of the memory chip is more serious, and the read-write performance of the memory chip under severe conditions can be conveniently detected.

S130, comparing the stored data with the test data by reading the stored data of the storage units in the storage chip, and determining the test result of the storage chip.

After the activation of the memory cells with non-adjacent word lines in the memory chip is completed each time, the memory chip can be controlled to read the memory data, and then the memory data is compared with the written test data to determine the memory cells with the same and different written data and the read data, so as to obtain the test result of the memory chip. By the method, whether the read-write data of the memory chip are consistent or not can be determined, and the read-write performance test of the memory chip is completed.

Specifically, in an optional implementation manner, step S130 may be implemented by reading the storage data of the storage units in the storage chip, comparing the storage data with the test data bit by bit, and determining whether each storage unit in the storage chip has a read-write error or not and the number of bits having the read-write error, so as to obtain the test result.

For the memory chip, the written test data and the read memory data are compared, whether the read data corresponding to each data bit are consistent or not can be determined, then a corresponding relation is established between the comparison result and the memory cells of the memory chip, and whether the read-write function of each memory cell is normal or not is determined. For the memory cells with read-write errors, the bit numbers of the memory cells with read-write errors can be counted, and the bit numbers of the memory cells with read-write errors in the whole memory chip are determined to obtain the test result of the memory chip.

Further, to reduce the interference between memory cells between different word lines, in an alternative embodiment, as shown in fig. 4, the following method may be further performed:

in step S410, the current word line is turned on before each reading of the memory data of the memory cells on the current word line of the memory chip.

In step S420, in the memory cells on the current word line, the memory data in the memory cells are read according to the unit burst length, and when the data reading of the memory cells corresponding to the unit burst length is completed each time, the current word line is closed until the data reading of all the memory cells on the current word line is completed, and then the memory data of the memory cells on the next word line of the memory chip are read.

When performing a read operation of a memory cell on a current word line, the current word line may be turned on first, and then the memory data of the memory cell on the current word line may be read in a unit burst length, for example, assuming that the unit burst length is 8 and x (x > 7) memory cells are shared in the current word line WL0, the first 8 memory cells in the current word line WL0, that is, the memory data in the memory cells 0 to 7, may be read after the current word line is turned on. After the reading of the storage data of one group of storage units corresponding to the unit burst length is completed, closing the current word line, restarting the current word line, continuing to read the storage data of the other group of storage units corresponding to the unit burst length of the current word line, for example, reading the storage data of storage units 8-15 in the current word line WL0, continuing to close the current word line after the reading is completed, restarting again, and executing the reading of the storage data of the rest storage units according to the unit burst length until the data reading of all storage units on the current word line is completed, and reading the storage data of the storage units on the next word line.

According to the method, the stored data in the plurality of storage units corresponding to the burst length of each word line can be controlled to be read at one time without reading one by one, so that the reading efficiency of the stored data can be improved, and meanwhile, after the stored data of the current word line is read each time, the current word line is closed and restarted, so that the interference between adjacent storage units can be reduced, and the influence on the correctness of the stored data is avoided.

As described above, in step S120, the memory cells having even word line numbers and the memory cells having odd word line numbers in the memory chip may be repeatedly activated with the preset time period as the word line on time of the memory chip, respectively. Thus, in an alternative embodiment, after the repeated activation of any one of the memory cells having even-numbered memory cells and the memory cells having odd-numbered memory cells is completed, the memory data of all the memory cells in the memory chip may be read, and the memory data may be compared with the test data to determine the test result of the memory chip. That is, after the repeated activation of the memory cells with the even word line numbers or the repeated activation of the memory cells with the odd word line numbers is completed, the memory data of all the memory cells in the memory chip can be read, and then compared with the written test data to determine the test result of the memory chip. By the method, the test result of the memory cells in the memory chip can be determined after the memory cells of the adjacent word lines are repeatedly activated, and the influence of the repeated activation of the memory cells with odd number word lines and the memory cells with even number word lines on the read-write performance of the memory chip can be determined.

Further, when the test data includes multiple sets of different data topologies, the memory cells of the memory chip having non-adjacent word lines may be activated after writing of any one set of data topologies into the memory cells of the memory chip is completed. Thus, in step S130, the storage data of the storage unit in the storage chip may be read, and the storage data may be compared with any one of the data topologies to determine the test result of the storage chip with respect to any one of the data topologies. That is, after the writing of a set of data topologies into memory cells of a memory chip and the repeated activation of memory cells of non-adjacent word lines are completed, a read operation with respect to the set of data topologies may continue to be performed, and the read memory data may be compared with the set of data topologies to determine the read-write performance of the memory chip under the set of data topologies. With the increase of the variety of data topologies, the method can perfect the testing mechanism of the memory chip and fully mine the read-write performance of the memory chip in various data environments, so that the testing comprehensiveness of the memory chip can be improved.

Specifically, when the test data includes multiple sets of different data topologies, different binary sequences in any one set of data topologies may be written into the first memory cell having the odd word line number and the second memory cell having the even word line number, respectively. Therefore, in an alternative embodiment, when the activation operation of the first storage unit or the second storage unit is completed, the storage data of all storage units in the storage chip are read, and the storage data are compared with the binary sequences corresponding to any one group of data topologies to determine the test result of the storage chip. In this way, only after repeated activation of the memory cells of the odd or even word line numbers is completed, a read operation of the memory data may be performed to compare the memory data with the written data topology and determine the test result of the memory chip.

In an alternative embodiment, when the binary sequences written in the first memory cell and the second memory cell are updated, the first memory cell or the second memory cell may be activated respectively by taking the preset duration as the word line on time of the memory chip. And then, after the activation of the first storage unit or the second storage unit is completed, the storage data of all the storage units in the storage chip can be read, and the storage data is compared with the binary sequence in the corresponding data topology to determine the test result of the storage chip. By the method, the storage data in the storage unit can be read only when the new data topology is written in the storage unit of the storage chip, so that the test result of the storage chip about a certain data topology is obtained, and the problem of low test efficiency caused by reading repeated data can be avoided.

Fig. 5 illustrates another method for testing a memory chip in the present exemplary embodiment, and as shown in the drawing, may include the following steps S510 to S540:

step S510, writing any one set of data topologies in the memory cells of the memory chip.

Wherein the plurality of sets of data topologies form test data, and each set of data topologies may comprise a plurality of binary sequences. For example, the test data may include four data topologies as shown in fig. 3, each including two binary sequences therein.

Step S520, the memory cells of the memory chip are refreshed according to a preset refresh cycle.

Specifically, after writing any one group of data topologies into the memory cells of the memory chip, the memory cells of the memory chip may be refreshed according to a preset refresh period. At this time, the refresh processing may be performed for all the memory cells in the memory chip, or may be performed for the memory cells in the memory chip to which data has been written.

In step S530, the memory cells having non-adjacent word lines in the memory chip are activated with the preset duration as the word line on time of the memory chip.

The preset time length is longer than the standard word line opening time of the memory chip, and the preset time length is obtained by setting the tRAS time sequence parameter. The preset time length is taken as the word line opening time of the memory chip, and the preset time length is longer than the standard word line opening time, so that when the memory cells with non-adjacent word lines in the memory chip are activated, the memory cells with non-adjacent word lines can be activated for a long time, the probability of generating row leakage is increased, and the problem of row leakage can be displayed as soon as possible.

Specifically, in order to determine the influence of repeatedly activating the odd-numbered lines on the read/write performance of the memory chip, step S530 may be performed to first activate the memory cells having the odd-numbered lines in the memory chip with a preset duration as the word line on time of the memory chip.

Step S540, the storage data of the storage units in the storage chip are read, the storage data are compared with the test data, and the test result of the storage chip is determined.

After the activation of the memory cells of the non-adjacent word lines is completed, the memory data in the memory chip can be read, then the memory data is compared with any one set of data topology, for example, according to the corresponding relation of the rows, the memory data of the corresponding rows is compared with the binary sequence in any one set of written data topology, so as to determine the number of bits, the positions and the like of the memory cells in the memory chip, which have no read-write errors and have read-write errors, and the like, so that the test result of the memory chip about any one set of data topology is obtained.

Next, in order to determine the influence of repeatedly activating even word line numbers on the read-write performance of the memory chip, after the steps S530 to S540 are completed for the first time, the steps S530 and S540 may be executed again, the memory cells having even word line numbers in the memory chip are activated with the preset duration as the word line on time of the memory chip, after the activation operation is completed, the memory data in the memory chip are read, and then the memory data are compared with the arbitrary set of data topologies, so as to obtain the test result of the memory chip about the arbitrary set of data topologies.

Finally, steps S510 to S540 may be continuously performed to write other sets of data topologies into the memory cells of the memory chip, and determine test results corresponding to the other sets of data topologies until test results of all the data topologies are obtained.

In summary, according to the method for testing a memory chip in this exemplary embodiment, test data may be written into a memory cell of the memory chip, a memory cell having a non-adjacent word line in the memory chip is activated with a preset time period as a word line on time of the memory chip, and the memory data and the test data are compared by reading the memory data of the memory cell in the memory chip, so as to determine a test result of the memory chip. The preset time length is longer than the standard word line opening time of the memory chip, and the preset time length is obtained by setting the tRAS time sequence parameter. On one hand, the scheme can determine the test result of the memory chip by reading the memory data of the memory cells in the memory chip and comparing the memory data with the test data, and complete the read-write performance test of the memory chip; on the other hand, by taking the preset duration as the word line opening time of the memory chip, the memory cells with non-adjacent word lines in the memory chip are activated, so that the memory cells with non-adjacent word lines can be activated for a long time, the probability of row leakage can be increased, the problem of row leakage can be displayed as soon as possible, and the test efficiency of the memory chip can be improved.

The present exemplary embodiment also provides a test apparatus of a memory chip, and referring to fig. 6, a test apparatus 600 of a memory chip may include: a writing module 610, which may be used to write test data into the memory cells of the memory chip; the activation module 620 may be configured to activate a memory cell having a non-adjacent word line in the memory chip with a preset duration as a word line on time of the memory chip, where the preset duration is longer than a standard word line on time of the memory chip, and the preset duration is obtained by setting a tRAS timing parameter; the comparison module 630 may be used to determine a test result of the memory chip by reading the memory data of the memory cells in the memory chip and comparing the memory data with the test data.

In one exemplary embodiment of the present disclosure, the writing module 610 may be used to write test data into memory cells on each word line of the memory chip one by one, such that one bit of binary data is written into each memory cell on each word line of the memory chip.

In an exemplary embodiment of the present disclosure, the writing module 610 may be further configured to turn on a current word line of the memory chip before writing test data into a memory cell on the current word line each time, write test data into the memory cell according to a unit burst length in the memory cell on the current word line, and turn off the current word line each time data writing of the memory cell corresponding to the unit burst length is completed, until data writing of all the memory cells on the current word line is completed, and then write test data into the memory cell on a next word line of the memory chip.

In an exemplary embodiment of the present disclosure, the activation module 620 may be configured to repeatedly activate memory cells having even word line numbers and memory cells having odd word line numbers in the memory chip with a preset duration as a word line on time of the memory chip, and after completing the repeated activation of any one of the memory cells having even word line numbers and the memory cells having odd word line numbers, the comparison module 630 may be configured to read memory data of all the memory cells in the memory chip, and compare the memory data with test data to determine a test result of the memory chip.

In an exemplary embodiment of the present disclosure, the test data includes multiple sets of different data topologies, and the writing module 610 may be configured to write each set of data topologies to all memory cells of the memory chip, respectively; the activation module 620 may be configured to perform the step of activating memory cells having non-adjacent word lines in the memory chip after writing of any one set of data topologies in the memory cells of the memory chip is completed; the comparison module 630 may be used to read the storage data of the storage unit in the storage chip, compare the storage data with any one set of data topology, and determine the test result of the storage chip about any one set of data topology.

In an exemplary embodiment of the present disclosure, each set of data topologies includes a plurality of different binary sequences, where when each set of data topologies is written to all memory cells of a memory chip, the writing module 610 may be further configured to determine all memory cells of the memory chip having odd word line numbers and even word line numbers, respectively, to obtain a first memory cell and a second memory cell, and write the different binary sequences in any set of data topologies to the first memory cell and the second memory cell, respectively, so as to write the different binary sequences in the memory cells of two adjacent word lines in the memory chip.

In an exemplary embodiment of the present disclosure, after writing different binary sequences in any one set of data topologies into the first memory cell and the second memory cell, respectively, the activation module 620 may be further configured to activate the first memory cell or the second memory cell, respectively, with a preset duration as a word line on time of the memory chip; when the activation operation on the first storage unit or the second storage unit is completed, the comparison module 630 may also be used to read the storage data of all the storage units in the storage chip, compare the storage data with the corresponding binary sequence in any one set of data topology, and determine the test result of the storage chip.

In one exemplary embodiment of the present disclosure, the writing module 610 may also be configured to write a first binary sequence in a first data topology to a first storage unit and a second binary sequence in the first data topology to a second storage unit, or write a second binary sequence in the first data topology to the first storage unit and a first binary sequence in the first data topology to a second storage unit.

In one exemplary embodiment of the present disclosure, the writing module 610 may also be configured to write an all 0 sequence in the second data topology to the first storage unit and an all 1 sequence in the second data topology to the second storage unit, or to write an all 1 sequence in the second data topology to the first storage unit and an all 0 sequence in the second data topology to the second storage unit.

In an exemplary embodiment of the present disclosure, the activation module 620 may be further configured to activate the first memory cell or the second memory cell respectively, with a preset duration as a word line on time of the memory chip when the binary sequences written in the first memory cell and the second memory cell are updated; the comparison module 630 may also be used to read the storage data of all the storage units in the storage chip after completing the activation of the first storage unit or the second storage unit, compare the storage data with the binary sequence in the corresponding data topology, and determine the test result of the storage chip.

In an exemplary embodiment of the present disclosure, the comparison module 630 may also be configured to read the storage data of the storage units in the storage chip, and compare the storage data with the test data bit by bit, so as to determine whether each storage unit in the storage chip has a read-write error and the number of bits that have a read-write error, so as to obtain a test result.

In an exemplary embodiment of the present disclosure, the comparison module 630 may be further configured to turn on a current word line before each reading of the stored data of the memory cells on the current word line of the memory chip, read the stored data in the memory cells according to the unit burst length among the memory cells on the current word line, and turn off the current word line each time the data reading of the memory cells corresponding to the unit burst length is completed, until the data reading of all the memory cells on the current word line is completed, and then read the stored data of the memory cells on the next word line of the memory chip.

In one exemplary embodiment of the present disclosure, the activation module 620 may also be used to decrease the word line off voltage of the memory chip to enhance the GIDL effect between memory cells of adjacent word lines in the memory chip when activating memory cells of the memory chip having non-adjacent word lines with a preset duration as the word line on time of the memory chip.

In one exemplary embodiment of the present disclosure, the activation module 620 may also be used to refresh the memory cells of the memory chip according to a preset refresh period after writing the test data into the memory cells of the memory chip.

The specific details of each module in the above apparatus are already described in the method section embodiments, and the details of the undisclosed solution may be referred to the method section embodiments, so that they will not be described in detail.

Those skilled in the art will appreciate that the various aspects of the present disclosure may be implemented as a system, method, or program product. Accordingly, various aspects of the disclosure may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.

Exemplary embodiments of the present disclosure also provide a computer-readable storage medium having stored thereon a program product capable of implementing the method described above in the present specification. In some possible implementations, various aspects of the disclosure may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps according to the various exemplary embodiments of the disclosure as described in the "exemplary methods" section of this specification, when the program product is run on the terminal device.

Referring to fig. 7, a program product 700 for implementing the above-described method according to an exemplary embodiment of the present disclosure is described, which may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

Program product 700 may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The computer readable signal medium may include a data signal propagated in baseband or as part of a carrier wave with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

The exemplary embodiment of the disclosure also provides an electronic device capable of implementing the method. An electronic device 800 according to such an exemplary embodiment of the present disclosure is described below with reference to fig. 8. The electronic device 800 shown in fig. 8 is merely an example and should not be construed to limit the functionality and scope of use of embodiments of the present disclosure in any way.

As shown in fig. 8, the electronic device 800 may be embodied in the form of a general purpose computing device. Components of electronic device 800 may include, but are not limited to: the at least one processing unit 810, the at least one memory unit 820, a bus 830 connecting the different system components (including the memory unit 820 and the processing unit 810), and a display unit 840.

Wherein the storage unit 820 stores program code that can be executed by the processing unit 810, such that the processing unit 810 performs steps according to various exemplary embodiments of the present disclosure described in the above section of the present specification. For example, the processing unit 810 may perform the method steps shown in fig. 1-2, 4-5, etc.

Storage unit 820 may include readable media in the form of volatile storage units such as Random Access Memory (RAM) 821 and/or cache memory unit 822, and may further include Read Only Memory (ROM) 823.

The storage unit 820 may also include a program/utility 824 having a set (at least one) of program modules 825, such program modules 825 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.

Bus 830 may be one or more of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 800 may also communicate with one or more external devices 900 (e.g., keyboard, pointing device, bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 800, and/or any device (e.g., router, modem, etc.) that enables the electronic device 800 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 850. Also, electronic device 800 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through network adapter 860. As shown, network adapter 860 communicates with other modules of electronic device 800 over bus 830. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 800, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with exemplary embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Furthermore, the above-described figures are only schematic illustrations of processes included in the method according to the exemplary embodiments of the present disclosure, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.

From the description of the embodiments above, those skilled in the art will readily appreciate that the exemplary embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the exemplary embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a terminal device, or a network device, etc.) to perform the method according to the exemplary embodiments of the present disclosure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A method for testing a memory chip, the method comprising:

writing test data into a memory unit of the memory chip;

activating a memory cell with a non-adjacent word line in the memory chip by taking a preset time length as the word line starting time of the memory chip, wherein the preset time length is longer than the standard word line starting time of the memory chip, and the preset time length is obtained by setting a tRAS time sequence parameter;

and comparing the storage data with the test data by reading the storage data of the storage units in the storage chip, and determining the test result of the storage chip.

2. The method of claim 1, wherein writing test data into the memory cells of the memory chip comprises:

and writing the test data into the memory cells on each word line of the memory chip one by one so as to write one bit of binary data into each memory cell on each word line of the memory chip.

3. The method of claim 2, wherein writing the test data into the memory cells on each word line of the memory chip one by one comprises:

opening a current word line of the memory chip before writing the test data into a memory cell on the current word line each time;

and writing the test data into the memory cells on the current word line according to the unit burst length, closing the current word line when the data writing of the memory cells corresponding to the unit burst length is completed each time, until the data writing of all the memory cells on the current word line is completed, and then writing the test data into the memory cells on the next word line of the memory chip.

4. The method of claim 1, wherein activating memory cells in the memory chip having non-adjacent word lines for a word line on time of the memory chip for a predetermined duration comprises:

Taking preset duration as word line opening time of the memory chip, and respectively repeatedly activating memory cells with even word line numbers and memory cells with odd word line numbers in the memory chip;

and after the repeated activation of any one of the memory cells with even digital line numbers and the memory cells with odd digital line numbers is completed, reading the memory data of all the memory cells in the memory chip, and comparing the memory data with the test data to determine the test result of the memory chip.

5. The method of claim 4, wherein the test data comprises a plurality of different sets of data topologies, the method further comprising:

writing each group of data topology into all storage units of the storage chip respectively;

after writing of any one set of data topologies in the memory cells of the memory chip is completed, executing a step of activating the memory cells with non-adjacent word lines in the memory chip;

and reading the storage data of the storage units in the storage chip, comparing the storage data with any one group of data topologies, and determining the test result of the storage chip about the any one group of data topologies.

6. The method of claim 5, wherein each set of data topologies includes a plurality of different binary sequences, and wherein when each set of data topologies is written to all memory cells of the memory chip, respectively, the method further comprises:

and writing different binary sequences in any group of data topologies into the first storage unit and the second storage unit respectively so as to write different binary sequences in the storage units of two adjacent word lines in the storage chip.

7. The method of claim 6, wherein after writing different binary sequences in the arbitrary set of data topologies to the first storage unit and the second storage unit, respectively, the method further comprises:

respectively activating the first memory cell or the second memory cell by taking the preset duration as the word line starting time of the memory chip;

and when the activation operation of the first storage unit or the second storage unit is completed, the storage data of all the storage units in the storage chip are read, the storage data are compared with the corresponding binary sequences in the arbitrary set of data topology, and the test result of the storage chip is determined.

8. The method of claim 7, wherein the plurality of sets of data topologies includes a first data topology having two binary sequences, wherein in each binary sequence of the first data topology, the data of adjacent data bits is different.

9. The method of claim 8, wherein writing different binary sequences in the arbitrary set of data topologies to the first storage unit and the second storage unit, respectively, comprises:

writing a first binary sequence in the first data topology to the first storage unit and writing a second binary sequence in the first data topology to the second storage unit; or alternatively

Writing a second binary sequence in the first data topology to the first memory cell and writing a first binary sequence in the first data topology to the second memory cell.

10. The method of claim 7, wherein the plurality of sets of data topologies comprises a second data topology having two binary sequences, wherein the two binary sequences are an all 0 sequence and an all 1 sequence, respectively.

11. The method of claim 10, wherein writing different binary sequences in the arbitrary set of data topologies to the first storage unit and the second storage unit, respectively, comprises:

Writing an all 0 sequence in the second data topology to the first storage unit and an all 1 sequence in the second data topology to the second storage unit; or alternatively

And writing the full 1 sequence in the second data topology into the first storage unit, and writing the full 0 sequence in the second data topology into the second storage unit.

12. The method of claim 7, wherein the method further comprises:

when the binary sequences written in the first storage unit and the second storage unit are updated, respectively activating the first storage unit or the second storage unit by taking a preset duration as the word line starting time of the storage chip;

after the activation of the first storage unit or the second storage unit is completed, the storage data of all storage units in the storage chip are read, the storage data are compared with binary sequences in corresponding data topologies, and the test result of the storage chip is determined.

13. The method of claim 2, wherein the determining the test result of the memory chip by reading the memory data of the memory cells in the memory chip, and comparing the memory data with the test data, comprises:

And reading the storage data of the storage units in the storage chip, comparing the storage data with the test data bit by bit, and determining whether each storage unit in the storage chip has a read-write error or not and the number of bits with the read-write error so as to obtain the test result.

14. The method of claim 3, wherein the reading the memory data of the memory cells in the memory chip comprises:

opening a current word line of the memory chip before each reading of memory data of a memory cell on the current word line;

and in the memory cells on the current word line, reading the memory data in the memory cells according to the unit burst length, closing the current word line when the data reading of the memory cells corresponding to the unit burst length is completed each time, until the data reading of all the memory cells on the current word line is completed, and then reading the memory data of the memory cells on the next word line of the memory chip.

15. The method of any of claims 1-14, wherein when a memory cell in the memory chip having a non-adjacent word line is activated for a word line on time of the memory chip for a preset duration, the method further comprises:

And reducing the word line closing voltage of the memory chip to enhance the GIDL effect between the memory cells of adjacent word lines in the memory chip.

16. The method of any of claims 1-14, wherein after writing test data into the memory cells of the memory chip, the method further comprises:

and refreshing the memory cells of the memory chip according to a preset refreshing period.

17. A test apparatus for a memory chip, the apparatus comprising:

the writing module is used for writing test data into the memory unit of the memory chip;

the activation module is used for activating the memory cells with non-adjacent word lines in the memory chip by taking the preset time length as the word line opening time of the memory chip, wherein the preset time length is longer than the standard word line opening time of the memory chip, and the preset time length is obtained by setting a tRAS time sequence parameter;

and the comparison module is used for comparing the storage data with the test data by reading the storage data of the storage units in the storage chip to determine the test result of the storage chip.

18. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the method of any of claims 1-16.

19. An electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the method of any of claims 1-16 via execution of the executable instructions.