WO2024082343A1 - Memory refresh parameter determination method and apparatus, memory refresh method and apparatus, and medium and device - Google Patents

Abstract

A memory refresh parameter determination method, comprising: for each memory unit in a semiconductor to be tested, determining the time ratio of a data retention duration of the memory unit to a reference data retention duration of a reference memory unit, wherein the reference memory unit is a memory unit having the shortest data retention duration in said semiconductor (201); for each memory unit, determining a target refresh interval duration of the memory unit according to a reference refresh interval duration of the reference memory unit and the time ratio (202); and for each memory unit, determining, according to a reference refresh amount of the reference memory unit for memory data within the reference refresh interval duration and the time ratio, a target refresh amount of the memory unit within the target refresh interval duration (203). The method reduces the power consumption of a DRAM chip.

Description

Memory refresh parameter determination, memory refresh method, device, medium and equipment

This disclosure claims priority to Chinese patent application No. 202211269164.5, filed on October 17, 2022, and entitled “Memory refresh parameter determination, memory refresh method, device, medium and apparatus”, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular to a memory refresh parameter determination, a memory refresh method, a device, a medium and a device.

Background technique

The basic structure of a DRAM (Dynamic Random Access Memory) chip generally includes one transistor and one capacitor. The capacitor is prone to leakage during operation, and the data retention time is inversely proportional to the memory refresh interval. Therefore, in order to ensure the integrity of the data, the capacitor needs to be charged periodically. This charging process is called memory refresh.

Due to factors such as physical layout and production process, the data retention time of different memory cells is different, and the maximum time difference can reach more than 50%. In response to this situation, most of the current refreshes are based on the memory cell with the shortest data retention time in the DRAM chip. This causes the memory cells with longer data retention time to also need to be refreshed based on the shortest refresh interval. In other words, the memory cells with longer data retention time have more refresh times per unit time, which greatly increases the power consumption of the DRAM chip.

Therefore, the current DRAM chips consume a lot of power.

Public Content

In a first aspect, an embodiment of the present disclosure provides a method for determining a memory refresh parameter, comprising:

For each memory cell in the semiconductor under test, determining a time ratio between a data retention time of the memory cell and a reference data retention time of a reference memory cell; wherein the reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor under test;

For each memory unit, determining a target refresh interval duration of the memory unit according to a reference refresh interval duration of the reference memory unit and a time ratio;

For each memory unit, a target refresh amount of the memory unit within a target refresh interval is determined according to a ratio of a reference refresh amount of memory data of the reference memory unit within a reference refresh interval to a time ratio.

In an optional embodiment of the present disclosure, before determining the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell for each memory cell in the semiconductor under test, the memory refresh parameter determination method further includes:

Obtaining the data retention time of each memory cell in the semiconductor under test during a data retention test;

The memory cell corresponding to the minimum value among the data retention time lengths is determined as the reference memory cell.

In an optional embodiment of the present disclosure, obtaining the data retention time of each memory cell in the semiconductor under test in a data retention test includes:

Performing mass production tests on the semiconductor to be tested and obtaining test results of the semiconductor to be tested;

The data retention time of each memory unit is extracted from the test results.

In an optional embodiment of the present disclosure, after determining the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell for each memory cell in the semiconductor under test, the memory refresh parameter determination method further includes:

The time ratio corresponding to each memory unit is stored in a preset storage module in the semiconductor to be tested.

In an optional embodiment of the present disclosure, the memory refresh parameter determination method further includes:

The target refresh amount corresponding to each memory unit is stored in a preset storage module in the semiconductor to be tested.

In an optional embodiment of the present disclosure, the preset storage module is a readable register in the semiconductor to be tested.

In an optional embodiment of the present disclosure, for each memory unit, determining a target refresh interval duration of the memory unit according to a reference refresh interval duration of the reference memory unit and a time ratio includes:

For each memory unit, the ratio between the reference refresh interval duration of the reference memory unit and the time ratio corresponding to the memory unit is calculated to obtain the target refresh interval duration of the memory unit.

In an optional embodiment of the present disclosure, for each memory unit, determining a target refresh amount of the memory unit within a target refresh interval duration according to a ratio of a baseline refresh amount of memory data of the reference memory unit within a baseline refresh interval duration to a time includes:

Determine a baseline refresh amount of memory data by a baseline memory unit within a baseline refresh interval;

For each memory unit, the ratio between the reference refresh amount and the time ratio corresponding to the memory unit is calculated to obtain the target refresh amount of the memory unit within the target refresh interval.

In an optional embodiment of the present disclosure, the reference refresh amount is the number of refresh units of each data unit in the memory unit within the reference refresh interval.

In an optional embodiment of the present disclosure, the semiconductor to be tested is a dynamic random access memory.

In a second aspect, an embodiment of the present disclosure provides a memory refresh method, comprising:

Obtaining a target refresh interval duration and a target refresh amount within the target refresh interval duration for each memory cell in the semiconductor under test; wherein the target refresh interval duration and the target refresh amount are determined according to any of the memory refresh parameter determination methods described above;

Based on the target refresh interval duration and the target refresh amount, each corresponding memory unit in the semiconductor under test is controlled to perform memory refresh.

In a third aspect, an embodiment of the present disclosure provides a memory refresh parameter determination device, the device comprising:

A first determination module is used to determine, for each memory cell in the semiconductor under test, a time ratio between a data retention time of the memory cell and a reference data retention time of a reference memory cell; wherein the reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor under test;

A second determination module is used to determine, for each memory unit, a target refresh interval duration of the memory unit according to a reference refresh interval duration of the reference memory unit and a time ratio;

The third determination module is used to determine, for each memory unit, a target refresh amount of the memory unit within a target refresh interval according to a ratio of a benchmark refresh amount of memory data of the benchmark memory unit within a benchmark refresh interval to time.

In a fourth aspect, an embodiment of the present disclosure provides a memory refresh device, the device comprising:

An acquisition module, used to acquire a target refresh interval duration and a target refresh amount within the target refresh interval duration for each memory cell in the semiconductor to be tested; wherein the target refresh interval duration and the target refresh amount are determined according to any of the memory refresh parameter determination methods described above;

The control module is used to control the corresponding memory units in the semiconductor to be tested to perform memory refresh based on the target refresh interval duration and the target refresh amount.

In a fifth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the above method when executed by a processor.

In a sixth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above method by executing the executable instructions.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG. 1( a ) shows a schematic diagram of the structure of a DRAM chip in this exemplary embodiment;

FIG. 1( b ) shows a schematic diagram of the structure of a memory cell in a DRAM chip according to the exemplary embodiment;

FIG2 shows a flow chart of a method for determining memory refresh parameters in this exemplary embodiment;

FIG3 is a diagram showing a corresponding relationship between a data retention time and a time ratio in a method for determining a memory refresh parameter in this exemplary embodiment;

FIG4 shows a flow chart of a method for determining memory refresh parameters in this exemplary embodiment;

FIG5 shows a flow chart of a method for determining memory refresh parameters in this exemplary embodiment;

FIG6 shows a flow chart of a method for determining memory refresh parameters in this exemplary embodiment;

FIG7 shows a flow chart of a memory refresh method in this exemplary embodiment;

FIG8 is a schematic diagram showing the structure of a memory refresh parameter determination device in this exemplary embodiment;

FIG9 shows a schematic structural diagram of a memory refresh device in this exemplary embodiment;

FIG. 10 is a schematic structural diagram of an electronic device in this exemplary embodiment.

Detailed ways

Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, exemplary embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the exemplary embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and/or processor devices and/or microcontroller devices.

The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

In the related art, the basic structure of a DRAM (Dynamic Random Access Memory) chip generally includes one transistor and one capacitor. The capacitor is prone to leakage during operation. Therefore, in order to ensure the integrity of the data, the capacitor needs to be periodically charged. This charging process is called memory refresh. Please refer to Figures 1(a) and 1(b). At present, the memory array of the DRAM chip 10 is composed of multiple Bank Groups/Banks (memory unit combinations/memory units). For example, in Figure 1(a), each memory unit 110 is placed in a DRAM chip in a certain order. Each memory unit 110 contains multiple data units, such as the 7×7 data units in Figure 1(b) (this is only an example, not enough to limit the number and arrangement of paired data units). The CPU (central processing unit) needs to refresh each memory unit 110 every tRFCpb (refresh interval), and each memory unit has the same refresh interval for memory refresh. Due to factors such as physical layout and production process, the refresh intervals of different memory units are not only the same, but the maximum time difference can reach more than 50%. In response to this situation, most of the memory units in the DRAM chip are refreshed based on the shortest refresh interval. This means that the memory units with longer refresh intervals also need to be refreshed based on the shortest refresh interval. In other words, the memory units with longer refresh intervals are refreshed more times per unit time, which greatly increases the power consumption of the DRAM chip. Therefore, the power consumption of DRAM chips is currently high.

In view of the above problems, the present disclosure provides a memory refresh parameter determination method to reduce the power consumption of DRAM chips. The following is a brief introduction to the application environment of the memory refresh parameter determination method provided by the present disclosure:

The memory refresh parameter determination method provided in the embodiment of the present disclosure is applied to a control device, which can be a CPU inside a DRAM chip, or other control components, control devices or control chips independent of the DRAM chip. The embodiment of the present disclosure does not make any specific limitations and can be arbitrarily set according to actual conditions.

The following uses the control device as the execution subject, and applies the memory refresh parameter determination method to the memory unit in the semiconductor under test to determine the memory refresh parameter as an example. The semiconductor under test can be any semiconductor that needs to perform memory refresh, such as a DRAM chip, etc., and the embodiment of the present disclosure is not specifically limited. Referring to FIG. 2, the memory refresh parameter determination method provided in the embodiment of the present disclosure includes the following steps 201-203:

Step 201: for each memory cell in the semiconductor to be tested, determine the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell.

The data retention time refers to the time that the capacitor in the memory cell can maintain no leakage. One memory cell corresponds to a data retention time, such as 10 seconds, 20 seconds, 30 seconds, etc. The benchmark memory cell refers to the memory cell with the shortest data retention time in the semiconductor to be tested. For example, please refer to Figure 3, which is a data retention time icon of each memory cell in a batch of DDR 4 SDRAM (Double Data Rate Fourth Synchronous Dynamic Random Access Memory, the fourth generation double data rate synchronous dynamic random access memory), where the horizontal axis is the number of different memory cells BANK0-BANK7, and the vertical axis is the data retention time of each memory cell. It can be seen from Figure 3 that BANK3 has the shortest data retention time of 30 seconds, that is, BANK3 is determined as the benchmark memory cell, and the corresponding benchmark data retention time is 30 seconds. Then, the ratio between the data retention time of each memory cell and 30 seconds is calculated respectively, and the time ratio corresponding to each memory cell is obtained, as shown in the following table (1):

Table 1)

Step 202: For each memory unit, determine a target refresh interval of the memory unit according to a reference refresh interval of the reference memory unit and a time ratio.

The refresh interval refers to the time between two memory refreshes of a memory unit, and correspondingly, the reference refresh interval is the time between two memory refreshes of a reference memory unit. The target refresh interval of each memory unit can be obtained by calculating the ratio, product or weighted product of the reference refresh interval and each time ratio.

Continuing with the above example, for example, the reference refresh interval of the reference memory unit BANK3 is 90 nanoseconds, and the target refresh intervals corresponding to BANK0-BANK7 are shown in the following table (2):

Table 2)

Memory Unit

Data retention time

Time ratio

Target refresh interval (single

The	(Unit: seconds)	The	bit: nanosecond)
BANK0	46	1.5	60
BANK1	45	1.5	60
BANK2	40	1.3	69
BANK3	30	1.0	90
BANK4	39	1.3	69
BANK5	41	1.4	64
BANK6	42	1.4	64
BANK7	50	1.7	53

It can be seen from the above table (2) that the target refresh interval of the memory unit is negatively correlated with the data retention time. The shorter the data retention time, the longer the target refresh interval. Conversely, the longer the data retention time, the shorter the target refresh interval. In addition, the target refresh intervals of different memory units are not the same. The refresh interval of each memory unit is shorter than the traditional method of uniformly using the longest refresh interval (such as 90 nanoseconds of BANK3 in the above example), thereby improving the refresh efficiency.

Step 203 : for each memory unit, determine a target refresh amount of the memory unit within a target refresh interval according to a ratio of a benchmark refresh amount of memory data of the benchmark memory unit within a benchmark refresh interval to a time ratio.

The refresh amount in the embodiments of the present disclosure refers to the amount of memory data refreshed by the memory unit within a refresh interval. It can be represented by a specific data size, such as 3M, 5M, etc., or by a data unit, such as 1 row, 2 rows, etc., which is not specifically limited in the embodiments of the present disclosure. Correspondingly, the benchmark refresh amount is the amount of memory data refreshed by the benchmark memory unit within a refresh interval. The target refresh amount of each memory unit can be obtained by calculating the ratio, product or weighted product of the benchmark refresh amount and each time ratio.

Continuing with the above example, for example, the baseline refresh amount of the above baseline memory unit BANK3 is 4.0 rows, and the target refresh amounts corresponding to BANK0-BANK7 are as follows (3):

table 3)

It can be seen from the above table (3) that the target refresh amount of the memory unit is negatively correlated with the data retention time. The shorter the data retention time, the larger the target refresh amount. On the contrary, the longer the data retention time, the smaller the target refresh amount. In addition, the target refresh amounts of different memory units are not the same. The refresh interval of each memory unit is smaller than the traditional method of uniformly using the maximum refresh amount (for example, the refresh amount of BANK3 in the above example is 4), and the refresh amount is reduced, which further reduces the power consumption of memory refresh.

The memory refresh parameter determination method provided by the embodiment of the present disclosure determines, for each memory cell in the semiconductor to be tested, the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell. In the first aspect, the target refresh interval of each memory cell is determined according to the reference refresh interval of the reference memory cell and the time ratio, thereby avoiding the traditional method of uniformly using the longest refresh interval of each memory cell, the overall refresh interval is shorter, and the memory refresh efficiency is higher; and each memory cell has a target refresh interval adapted to the corresponding data retention time to ensure normal data refresh;

On the second aspect, the disclosed embodiment determines the target refresh amount of the memory unit within the target refresh interval based on the ratio of the benchmark refresh amount of the memory data of the benchmark memory unit within the benchmark refresh interval to the time, thereby avoiding the traditional method of uniformly using the maximum refresh amount (for example, the refresh amount of 4 for BANK3 in the above example), reducing the refresh amount and further reducing the power consumption of the memory refresh.

Therefore, the disclosed embodiments improve the efficiency of memory refresh while greatly reducing the power consumption of memory refresh, thereby solving the current technical problem of high power consumption of DRAM chips and achieving the technical effect of reducing the power consumption of DRAM chips.

Please refer to FIG. 4 . In an optional embodiment of the present disclosure, before the above step 201, for each memory cell in the semiconductor under test, determining the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell, the above memory refresh parameter determination method further includes the following steps 401-402:

Step 401: Obtain the data retention time of each memory cell in the semiconductor under test in a data retention test.

Data retention test refers to the test of the data retention time of each memory cell in the semiconductor under test. For example, by continuously testing the data written in the memory cell, the data is written or the test is started as the starting time, and the time when the first group of data is lost or other set number of data are lost is the ending time. The time between the starting time and the ending time is the data retention time, which is used to characterize the data retention ability of the memory cell.

Step 402: Determine the memory unit corresponding to the minimum value among the data retention time as the reference memory unit.

Continuing with the above example, as can be seen in FIG3 , the data retention time of BANK3 is the shortest, which is 30 seconds. That is, BANK3 is determined as the benchmark memory unit, and the corresponding benchmark data retention time is 30 seconds.

The data retention time in the disclosed embodiment is based on that obtained from the data retention test rather than being obtained based on empirical fitting. The obtained benchmark memory unit is based on actual production, and the target refresh interval time and target refresh amount of each memory unit determined based on the benchmark memory unit are also more reliable.

Please refer to FIG. 5 . In an optional embodiment of the present disclosure, the above step 401 of obtaining the data retention time of each memory cell in the semiconductor under test in the data retention test includes the following steps 501 to 502:

Step 501: Perform mass production testing on the semiconductor to be tested to obtain a test result of the semiconductor to be tested.

The mass production test of the chip (Automatic Test Equipment, ATE for short) is used to detect the integrity of the integrated circuit function. The test content includes but is not limited to: the data retention time of the memory unit, whether there is an open circuit or short circuit in the chip pins, logical function, device DC current and voltage parameters, AC output signal quality and signal timing parameters, embedded flash function and performance, etc.

Step 502: extract the data retention time of each memory unit from the test results.

The disclosed embodiments do not need to perform data retention tests separately. Data retention tests can be added while mass production tests are being performed, and tests can be performed synchronously with other projects. After the test is completed, the required data retention time can be extracted from the test results, saving test time and test costs.

In an optional embodiment of the present disclosure, after the above step 201, for each memory cell in the semiconductor under test, determines the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell, the above memory refresh parameter determination method further includes the following step A:

Step A: storing the time ratio corresponding to each memory unit in a preset storage module in the semiconductor to be tested.

The preset storage module can be a storage module in the semiconductor to be tested, and can be specifically selected or set according to actual conditions, without any limitation here. The time ratio corresponding to each memory unit is stored in the preset storage module to facilitate the control device to read, thereby improving the convenience and efficiency of determining the memory refresh parameter.

In an optional embodiment of the present disclosure, the above-mentioned memory refresh parameter determination method further includes the following step B:

Step B: storing the target refresh amount corresponding to each memory cell in a preset storage module in the semiconductor to be tested.

As in step A above, the preset storage module can be a storage module in the semiconductor to be tested, which can be specifically selected or set according to the actual situation, and is not limited here. The target refresh amount corresponding to each memory unit is stored in the preset storage module to facilitate the control device to read, thereby improving the convenience and efficiency of determining the memory refresh parameters.

In an optional embodiment of the present disclosure, the above-mentioned reference refresh amount is the number of refresh units for each data unit in the memory unit within the reference refresh interval. Data unit refers to the storage form of memory data in the memory unit, for example, 1 row, 2 rows or 3 rows can be a data unit, or 10KB, 20KB or 30KB can be a data unit, or 10 characters, 20 characters or 30 characters can be a data unit. Measuring the refresh amount in data units has a smaller amount of calculation than real-time calculation of memory data, which can save computing resources and further improve the efficiency of determining memory refresh parameters.

In an optional embodiment of the present disclosure, the semiconductor to be tested is a dynamic random access memory, that is, the semiconductor to be tested is a DRAM chip, and the target refresh interval duration of each memory unit when performing memory refresh in the DRAM chip and the target refresh amount within the target refresh interval duration are determined based on the memory refresh parameter determination method provided in the embodiment of the present disclosure, which can greatly improve the efficiency of memory refresh of the DRAM chip and reduce the power consumption of memory refresh.

In an optional embodiment of the present disclosure, the preset storage module is a readable register in the semiconductor to be tested.

A readable register refers to a semiconductor to be tested, such as a readable mode register (such as an MR register) in a DRAM chip. The readable mode register can be accessed by a control device, such as the CPU of a DRAM chip, to read data, thereby facilitating the acquisition of the time ratio of each stored memory unit, the target refresh interval duration, and the target refresh amount, thereby improving the efficiency and convenience of memory refresh and the overall performance of the DRAM chip.

In an optional embodiment of the present disclosure, the above step 202, for each memory unit, determines the target refresh interval of the memory unit according to the reference refresh interval of the reference memory unit and the time ratio, includes the following step C:

Step C: for each memory unit, calculate the ratio between the reference refresh interval duration of the reference memory unit and the time ratio corresponding to the memory unit to obtain the target refresh interval duration of the memory unit.

That is, in this embodiment, the target refresh interval of the memory unit can be calculated by the following formula (1):

tRF _i = tRF ₀ /(RT _i /RT ₀ ) (1)

In formula (1), tRF _i represents the target refresh interval of the i-th memory unit, tRF ₀ represents the reference refresh interval of the reference memory unit, RT _i represents the data retention time of the i-th memory unit, RT ₀ represents the reference data retention time of the reference memory unit, and (RT _i /RT ₀ ) represents the time ratio of the i-th memory unit.

This embodiment directly obtains the target refresh interval of the memory unit by calculating the ratio between the benchmark refresh interval of the benchmark memory unit and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

Please refer to FIG. 6 . In an optional embodiment of the present disclosure, the above step 203, for each memory unit, determines the target refresh amount of the memory unit within the target refresh interval according to the ratio of the reference refresh amount of the memory data of the reference memory unit within the reference refresh interval to the time, including the following steps 601-602:

Step 601: Determine a reference refresh amount of memory data of a reference memory unit within a reference refresh interval.

For example, the baseline refresh amount of the baseline memory unit within the baseline refresh interval duration is 4.

Step 602: For each memory unit, calculate the ratio between the reference refresh amount and the time ratio corresponding to the memory unit to obtain the target refresh amount of the memory unit within the target refresh interval.

That is, in this embodiment, the target refresh amount of the memory unit can be calculated by the following formula (2):

R _i = R ₀ /(RT _i /RT ₀ ) (2)

In formula (2), _Ri represents the target refresh amount of the i-th memory unit, _R0 represents the reference refresh amount of the reference memory unit, _RTi represents the data retention time of the i-th memory unit, _RT0 represents the reference data retention time of the reference memory unit, and ( _RTi / _RT0 ) represents the time ratio of the i-th memory unit.

This embodiment directly obtains the target refresh amount of the memory unit within the target refresh interval by calculating the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

Referring to FIG. 7 , an embodiment of the present disclosure provides a memory refresh method, including the following steps 701 to 702:

Step 701: Obtain a target refresh interval duration and a target refresh amount within the target refresh interval duration for each memory cell in the semiconductor under test.

The target refresh interval and the target refresh amount are determined according to any of the memory refresh parameter determination methods described above;

The beneficial effects of the memory refresh parameter determination method have been described in detail in the above embodiments and will not be repeated here.

Step 702: Control corresponding memory cells in the semiconductor under test to perform memory refresh based on the target refresh interval duration and the target refresh amount.

The disclosed embodiment first determines the target refresh interval duration of each memory unit in the semiconductor to be tested and the target refresh amount within the target refresh interval duration based on the above-mentioned memory refresh parameter determination method, and then controls the corresponding memory units in the semiconductor to be tested to perform memory refresh based on the target refresh interval duration and the target refresh amount. On the one hand, it can avoid the traditional method of uniformly using the longest refresh interval duration in each memory unit, and the overall refresh interval duration is shorter, and the memory refresh efficiency is higher; and each memory unit has a target refresh interval duration adapted to the corresponding data retention duration to ensure normal data refresh; on the other hand, it can avoid the traditional method of uniformly using the maximum refresh amount (such as the refresh amount 4 of BANK3 in the above example), and the refresh amount is reduced, which further reduces the power consumption of memory refresh. Therefore, the disclosed embodiment greatly reduces the power consumption of memory refresh while improving the efficiency of memory refresh, thereby solving the technical problem of the current high power consumption of DRAM chips and achieving the technical effect of reducing the power consumption of DRAM chips.

Please refer to FIG8 . In order to implement the above-mentioned memory refresh parameter determination method, a memory refresh parameter determination device 800 is provided in one embodiment of the present disclosure. FIG8 shows a schematic architecture diagram of the memory refresh parameter determination device 800 . The memory refresh parameter determination device 800 includes: a first determination module 810 , a second determination module 820 and a third determination module 830 , wherein:

The first determination module 810 is used to determine, for each memory cell in the semiconductor under test, a time ratio between a data retention time of the memory cell and a reference data retention time of a reference memory cell; wherein the reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor under test;

The second determination module 820 is used to determine, for each memory unit, a target refresh interval duration of the memory unit according to a reference refresh interval duration of the reference memory unit and a time ratio;

The third determination module 830 is used to determine, for each memory unit, a target refresh amount of the memory unit within a target refresh interval according to a ratio of a benchmark refresh amount of memory data of the benchmark memory unit within a benchmark refresh interval to a time.

The memory refresh parameter determination device provided by the embodiment of the present disclosure determines, for each memory cell in the semiconductor to be tested, the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell. In the first aspect, the target refresh interval of each memory cell is determined according to the reference refresh interval of the reference memory cell and the time ratio, thereby avoiding the traditional method of uniformly using the longest refresh interval of each memory cell, the overall refresh interval is shorter, and the memory refresh efficiency is higher; and each memory cell has a target refresh interval adapted to the corresponding data retention time to ensure normal data refresh;

On the second aspect, the disclosed embodiment determines the target refresh amount of the memory unit within the target refresh interval according to the ratio of the benchmark refresh amount of the memory data of the benchmark memory unit within the benchmark refresh interval to the time, thereby avoiding the traditional method of uniformly using the maximum refresh amount (for example, the refresh amount of 4 for BANK3 in the above example), reducing the refresh amount and further reducing the power consumption of the memory refresh.

Therefore, the disclosed embodiments improve the efficiency of memory refresh while greatly reducing the power consumption of memory refresh, thereby solving the current technical problem of high power consumption of DRAM chips and achieving the technical effect of reducing the power consumption of DRAM chips.

In an optional embodiment, the first determination module 810 is further used to obtain the data retention time of each memory unit in the semiconductor under test in a data retention test; and determine the memory unit corresponding to the minimum value of each data retention time as the reference memory unit.

The data retention time in the disclosed embodiment is based on that obtained from the data retention test rather than being obtained based on empirical fitting. The obtained benchmark memory unit is based on actual production, and the target refresh interval time and target refresh amount of each memory unit determined based on the benchmark memory unit are also more reliable.

In an optional embodiment, the first determination module 810 is specifically used to perform mass production testing on the semiconductor to be tested to obtain test results of the semiconductor to be tested; and extract the data retention time of each memory unit from the test results.

The disclosed embodiments do not need to perform data retention tests separately. Data retention tests can be added while mass production tests are being performed, and tests can be performed synchronously with other projects. After the test is completed, the required data retention time can be extracted from the test results, saving test time and test costs.

In an optional embodiment, the first determination module 810 is further configured to store the time ratio corresponding to each memory unit in a preset storage module in the semiconductor to be tested.

In an optional embodiment, the third determination module 830 is further configured to store the target refresh amount corresponding to each memory unit in a preset storage module in the semiconductor to be tested.

The time ratio and target refresh amount corresponding to each memory unit are stored in the preset storage module to facilitate the control device to read, thereby improving the convenience and efficiency of determining the memory refresh parameters.

In an optional embodiment, the preset storage module is a readable register in the semiconductor to be tested.

A readable register refers to a semiconductor to be tested, such as a readable mode register (such as an MR register) in a DRAM chip. The readable mode register can be accessed by a control device, such as the CPU of a DRAM chip, for data reading, thereby facilitating the acquisition of the time ratio of each stored memory unit, the target refresh interval duration, and the target refresh amount, etc., thereby improving the efficiency and convenience of memory refresh and the overall performance of the DRAM chip.

In an optional embodiment, the second determination module 820 is specifically used to calculate, for each memory unit, a ratio between a benchmark refresh interval of a benchmark memory unit and a time ratio corresponding to the memory unit to obtain a target refresh interval of the memory unit.

This embodiment directly obtains the target refresh interval of the memory unit by calculating the ratio between the benchmark refresh interval of the benchmark memory unit and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

In an optional embodiment, the third determination module 830 is specifically used to determine a baseline refresh amount of memory data by a baseline memory unit within a baseline refresh interval; for each memory unit, the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit is calculated to obtain a target refresh amount of the memory unit within a target refresh interval.

This embodiment directly calculates the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit to obtain the target refresh amount of the memory unit within the target refresh interval. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

In an optional embodiment, the reference refresh amount is the number of refresh units of each data unit in the memory unit within the reference refresh interval.

Measuring the refresh amount in data units has a smaller amount of calculation than real-time calculation of memory data, which can save computing resources and further improve the efficiency of determining memory refresh parameters.

In an optional embodiment, the semiconductor to be tested is a dynamic random access memory.

That is, the semiconductor to be tested is a DRAM chip. Based on the embodiments of the present disclosure, the target refresh interval of each memory unit when performing memory refresh in the DRAM chip and the target refresh amount within the target refresh interval are determined, which can greatly improve the efficiency of DRAM chip memory refresh and reduce the power consumption of memory refresh.

Please refer to FIG9 . In order to implement the above memory refresh method, a memory refresh device 900 is provided in one embodiment of the present disclosure. FIG9 shows a schematic architecture diagram of the memory refresh device 900 . The memory refresh device 900 includes: an acquisition module 910 and a control module 920 , wherein:

The acquisition module 910 is used to obtain the target refresh interval duration of each memory unit in the semiconductor to be tested, and the target refresh amount within the target refresh interval duration; wherein the target refresh interval duration and the target refresh amount are determined according to any of the memory refresh parameter determination methods described above;

The control module 920 is used to control the memory refresh of each corresponding memory unit in the semiconductor under test based on the target refresh interval duration and the target refresh amount.

This embodiment directly obtains the target refresh amount of the memory unit within the target refresh interval by calculating the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

The exemplary embodiments of the present disclosure also provide a computer-readable storage medium, which can be implemented in the form of a program product, which includes a program code, and when the program product is run on an electronic device, the program code is used to cause the electronic device to perform the steps described in the above "Exemplary Method" section of this specification according to various exemplary embodiments of the present disclosure. In one embodiment, the program product can be implemented as a portable compact disk read-only memory (CD-ROM) and includes program code, and can be run on an electronic device, such as a personal computer. However, the program product of the present disclosure is not limited to this, and in this document, the readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

The program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and conventional procedural programming languages such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., using an Internet service provider to connect through the Internet). In the embodiments of the present disclosure, when the program code stored in the computer-readable storage medium is executed, any step in the above memory refresh parameter determination method or memory refresh method may be implemented.

In one embodiment of the present disclosure, when the program code stored in the computer-readable storage medium is executed, the following steps can be implemented:

For each memory cell in the semiconductor under test, determining a time ratio between a data retention time of the memory cell and a reference data retention time of a reference memory cell; wherein the reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor under test;

For each memory unit, determining a target refresh interval duration of the memory unit according to a reference refresh interval duration of the reference memory unit and a time ratio;

For each memory unit, a target refresh amount of the memory unit within a target refresh interval is determined according to a ratio of a reference refresh amount of memory data of the reference memory unit within a reference refresh interval to a time ratio.

The disclosed embodiment determines the time ratio between the data retention time of each memory cell in the semiconductor to be tested and the reference data retention time of the reference memory cell. In the first aspect, the target refresh interval of each memory cell is determined according to the reference refresh interval of the reference memory cell and the time ratio, thereby avoiding the traditional method of uniformly using the longest refresh interval of each memory cell, the overall refresh interval is shorter, and the memory refresh efficiency is higher; and each memory cell has a target refresh interval adapted to the corresponding data retention time to ensure normal data refresh;

On the second aspect, the disclosed embodiment determines the target refresh amount of the memory unit within the target refresh interval based on the ratio of the benchmark refresh amount of the memory data of the benchmark memory unit within the benchmark refresh interval to the time, thereby avoiding the traditional method of uniformly using the maximum refresh amount (for example, the refresh amount of 4 for BANK3 in the above example), reducing the refresh amount and further reducing the power consumption of the memory refresh.

Therefore, the disclosed embodiments improve the efficiency of memory refresh while greatly reducing the power consumption of memory refresh, thereby solving the current technical problem of high power consumption of DRAM chips and achieving the technical effect of reducing the power consumption of DRAM chips.

In an optional embodiment of the present disclosure, the program code stored in a computer-readable storage medium can implement the following steps when executed: obtaining the data retention time of each memory cell in the semiconductor under test in a data retention test; determining the memory cell corresponding to the minimum value of each data retention time as the reference memory cell.

The data retention time in the disclosed embodiment is based on that obtained from the data retention test rather than being obtained based on empirical fitting. The obtained benchmark memory unit is based on actual production, and the target refresh interval time and target refresh amount of each memory unit determined based on the benchmark memory unit are also more reliable.

In an optional embodiment of the present disclosure, the program code stored in the computer-readable storage medium can implement the following steps when executed: perform mass production testing on the semiconductor to be tested to obtain test results of the semiconductor to be tested; and extract the data retention time of each memory unit from the test results.

The disclosed embodiments do not need to perform data retention tests separately. Data retention tests can be added while mass production tests are being performed, and tests can be performed synchronously with other projects. After the test is completed, the required data retention time can be extracted from the test results, saving test time and test costs.

In an optional embodiment of the present disclosure, the program code stored in the computer-readable storage medium can implement the following steps when executed: storing the time ratio corresponding to each memory unit in a preset storage module in the semiconductor to be tested.

In an optional embodiment of the present disclosure, the program code stored in the computer-readable storage medium can implement the following steps when executed: storing the target refresh amount corresponding to each memory unit in a preset storage module in the semiconductor to be tested.

The time ratio and target refresh amount corresponding to each memory unit are stored in the preset storage module to facilitate the control device to read, thereby improving the convenience and efficiency of determining the memory refresh parameters.

In an optional embodiment of the present disclosure, the preset storage module is a readable register in the semiconductor to be tested.

A readable register refers to a semiconductor to be tested, such as a readable mode register (such as an MR register) in a DRAM chip. The readable mode register can be accessed by a control device, such as the CPU of a DRAM chip, for data reading, thereby facilitating the acquisition of the time ratio of each stored memory unit, the target refresh interval duration, and the target refresh amount, etc., thereby improving the efficiency and convenience of memory refresh and the overall performance of the DRAM chip.

In an optional embodiment of the present disclosure, the program code stored in a computer-readable storage medium can implement the following steps when executed: for each memory unit, calculate the ratio between the baseline refresh interval duration of the baseline memory unit and the time ratio corresponding to the memory unit to obtain the target refresh interval duration of the memory unit.

This embodiment directly obtains the target refresh interval of the memory unit by calculating the ratio between the benchmark refresh interval of the benchmark memory unit and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

In an optional embodiment of the present disclosure, the program code stored in a computer-readable storage medium can implement the following steps when executed: determining a baseline refresh amount of memory data by a baseline memory unit within a baseline refresh interval; for each memory unit, calculating the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit, to obtain a target refresh amount of the memory unit within a target refresh interval.

This embodiment directly obtains the target refresh amount of the memory unit within the target refresh interval by calculating the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

In an optional embodiment of the present disclosure, the reference refresh amount is the number of refresh units of each data unit in the memory unit within the reference refresh interval.

Measuring the refresh amount in data units has a smaller amount of calculation than real-time calculation of memory data, which can save computing resources and further improve the efficiency of determining memory refresh parameters.

In an optional embodiment of the present disclosure, the semiconductor to be tested is a dynamic random access memory.

That is, the semiconductor to be tested is a DRAM chip. Based on the embodiments of the present disclosure, the target refresh interval of each memory unit when performing memory refresh in the DRAM chip and the target refresh amount within the target refresh interval are determined, which can greatly improve the efficiency of DRAM chip memory refresh and reduce the power consumption of memory refresh.

In one embodiment of the present disclosure, when the program code stored in the computer-readable storage medium is executed, the following steps can be implemented:

Obtaining a target refresh interval duration and a target refresh amount within the target refresh interval duration for each memory cell in the semiconductor under test; wherein the target refresh interval duration and the target refresh amount are determined according to any of the memory refresh parameter determination methods described above;

Based on the target refresh interval duration and the target refresh amount, each corresponding memory unit in the semiconductor under test is controlled to perform memory refresh.

This embodiment directly obtains the target refresh amount of the memory unit within the target refresh interval by calculating the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

Referring to FIG. 10 , an exemplary embodiment of the present disclosure further provides an electronic device 1000, which may be a background server of an information platform. The electronic device 1000 is described below with reference to FIG. 10 . It should be understood that the electronic device 1000 shown in FIG. 10 is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

As shown in Fig. 10, the electronic device 1000 is in the form of a general computing device. The components of the electronic device 1000 may include but are not limited to: at least one processing unit 1010, at least one storage unit 1020, and a bus 1030 connecting different system components (including the storage unit 1020 and the processing unit 1010).

The storage unit stores program codes, which can be executed by the processing unit 1010, so that the processing unit 1010 performs the steps of various exemplary embodiments of the present invention described in the above "Exemplary Method" section of this specification. For example, the processing unit 1010 can perform the method steps shown in Figure 2, etc.

The storage unit 1020 may include a volatile storage unit, such as a random access storage unit (RAM) 1021 and/or a cache storage unit 1022 , and may further include a read-only storage unit (ROM) 1023 .

The storage unit 1020 may also include a program/utility 1024 having a set (at least one) of program modules 1025, such program modules 1025 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

The bus 1030 may include a data bus, an address bus, and a control bus.

The electronic device 1000 may also communicate with one or more external devices 2000 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), and such communication may be performed via an input/output (I/O) interface 1040. The electronic device 1000 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and/or public networks, such as the Internet) via a network adapter 1050. As shown, the network adapter 1050 communicates with other modules of the electronic device 1000 via a bus 1030. It should be understood that, although not shown in the figure, other hardware and/or software modules may be used in conjunction with the electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

In the embodiments of the present disclosure, when the program code stored in the electronic device is executed, any step in the above-mentioned memory refresh parameter determination method or memory refresh method can be implemented.

In one embodiment of the present disclosure, when the program code stored in the electronic device is executed, the following steps can be implemented:

For each memory cell in the semiconductor under test, determining a time ratio between a data retention time of the memory cell and a reference data retention time of a reference memory cell; wherein the reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor under test;

For each memory unit, determining a target refresh interval duration of the memory unit according to a reference refresh interval duration of the reference memory unit and a time ratio;

For each memory unit, a target refresh amount of the memory unit within a target refresh interval is determined according to a ratio of a reference refresh amount of memory data of the reference memory unit within a reference refresh interval to a time ratio.

The disclosed embodiment determines the time ratio between the data retention time of each memory cell in the semiconductor to be tested and the reference data retention time of the reference memory cell. In the first aspect, the target refresh interval of each memory cell is determined according to the reference refresh interval of the reference memory cell and the time ratio, thereby avoiding the traditional method of uniformly using the longest refresh interval of each memory cell, the overall refresh interval is shorter, and the memory refresh efficiency is higher; and each memory cell has a target refresh interval adapted to the corresponding data retention time to ensure normal data refresh;

On the second aspect, the disclosed embodiment determines the target refresh amount of the memory unit within the target refresh interval based on the ratio of the benchmark refresh amount of the memory data of the benchmark memory unit within the benchmark refresh interval to the time, thereby avoiding the traditional method of uniformly using the maximum refresh amount (for example, the refresh amount of 4 for BANK3 in the above example), reducing the refresh amount and further reducing the power consumption of the memory refresh.

Therefore, the disclosed embodiments improve the efficiency of memory refresh while greatly reducing the power consumption of memory refresh, thereby solving the current technical problem of high power consumption of DRAM chips and achieving the technical effect of reducing the power consumption of DRAM chips.

In an optional embodiment of the present disclosure, the program code stored in the electronic device can implement the following steps when executed: obtaining the data retention time of each memory unit in the semiconductor under test in the data retention test; determining the memory unit corresponding to the minimum value of each data retention time as the reference memory unit.

The data retention time in the disclosed embodiment is based on that obtained from the data retention test rather than being obtained based on empirical fitting. The obtained benchmark memory unit is based on actual production, and the target refresh interval time and target refresh amount of each memory unit determined based on the benchmark memory unit are also more reliable.

In an optional embodiment of the present disclosure, the program code stored in the electronic device can implement the following steps when executed: perform mass production testing on the semiconductor to be tested to obtain test results of the semiconductor to be tested; and extract the data retention time of each memory unit from the test results.

The disclosed embodiments do not need to perform data retention tests separately. Data retention tests can be added while mass production tests are being performed, and tests can be performed synchronously with other projects. After the test is completed, the required data retention time can be extracted from the test results, saving test time and test costs.

In an optional embodiment of the present disclosure, when the program code stored in the electronic device is executed, the following steps can be implemented: storing the time ratio corresponding to each memory unit in a preset storage module in the semiconductor to be tested.

In an optional embodiment of the present disclosure, when the program code stored in the electronic device is executed, the following steps can be implemented: storing the target refresh amount corresponding to each memory unit in a preset storage module in the semiconductor to be tested.

The time ratio and target refresh amount corresponding to each memory unit are stored in the preset storage module to facilitate the control device to read, thereby improving the convenience and efficiency of determining the memory refresh parameters.

In an optional embodiment of the present disclosure, the preset storage module is a readable register in the semiconductor to be tested.

A readable register refers to a semiconductor to be tested, such as a readable mode register (such as an MR register) in a DRAM chip. The readable mode register can be accessed by a control device, such as the CPU of a DRAM chip, for data reading, thereby facilitating the acquisition of the time ratio of each stored memory unit, the target refresh interval duration, and the target refresh amount, etc., thereby improving the efficiency and convenience of memory refresh and the overall performance of the DRAM chip.

In an optional embodiment of the present disclosure, the program code stored in the electronic device can implement the following steps when executed: for each memory unit, calculate the ratio between the benchmark refresh interval duration of the benchmark memory unit and the time ratio corresponding to the memory unit to obtain the target refresh interval duration of the memory unit.

This embodiment directly obtains the target refresh interval of the memory unit by calculating the ratio between the benchmark refresh interval of the benchmark memory unit and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

In an optional embodiment of the present disclosure, the program code stored in the electronic device can implement the following steps when executed: determine a baseline refresh amount of memory data by a baseline memory unit within a baseline refresh interval; for each memory unit, calculate the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit, and obtain a target refresh amount of the memory unit within a target refresh interval.

This embodiment directly obtains the target refresh amount of the memory unit within the target refresh interval by calculating the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

In an optional embodiment of the present disclosure, the reference refresh amount is the number of refresh units of each data unit in the memory unit within the reference refresh interval.

Measuring the refresh amount in data units has a smaller amount of calculation than real-time calculation of memory data, which can save computing resources and further improve the efficiency of determining memory refresh parameters.

In an optional embodiment of the present disclosure, the semiconductor to be tested is a dynamic random access memory.

That is, the semiconductor to be tested is a DRAM chip. Based on the embodiments of the present disclosure, the target refresh interval of each memory unit when performing memory refresh in the DRAM chip and the target refresh amount within the target refresh interval are determined, which can greatly improve the efficiency of DRAM chip memory refresh and reduce the power consumption of memory refresh.

In one embodiment of the present disclosure, when the program code stored in the electronic device is executed, the following steps can be implemented:

Obtaining a target refresh interval duration and a target refresh amount within the target refresh interval duration for each memory cell in the semiconductor under test; wherein the target refresh interval duration and the target refresh amount are determined according to any of the memory refresh parameter determination methods described above;

Based on the target refresh interval and the target refresh amount, each corresponding memory unit in the semiconductor under test is controlled to perform memory refresh.

This embodiment directly obtains the target refresh amount of the memory unit within the target refresh interval by calculating the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters of the disclosed embodiment.

It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the exemplary embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

It will be appreciated by those skilled in the art that various aspects of the present disclosure may be implemented as systems, methods or program products. Therefore, various aspects of the present disclosure may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or implementations combining hardware and software aspects, which may be collectively referred to herein as "circuit", "module" or "system". Those skilled in the art will readily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptive changes of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and implementation are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (15)

1. A method for determining memory refresh parameters, comprising:

   For each memory cell in the semiconductor under test, determining a time ratio between a data retention time of the memory cell and a reference data retention time of a reference memory cell; wherein the reference memory cell refers to a memory cell in the semiconductor under test with the shortest data retention time;

   For each of the memory units, determining a target refresh interval duration of the memory unit according to a reference refresh interval duration of the reference memory unit and the time ratio;

   For each of the memory units, a target refresh amount of the memory unit within the target refresh interval is determined according to a reference refresh amount of the memory data of the reference memory unit within the reference refresh interval and the time ratio.
2. The memory refresh parameter determination method according to claim 1, wherein, before determining the time ratio between the data retention time of each memory cell in the semiconductor to be tested and the reference data retention time of the reference memory cell, the method further comprises:

   Obtaining the data retention time of each memory cell in the semiconductor under test in a data retention test;

   The memory unit corresponding to the minimum value among the data retention time lengths is determined as the reference memory unit.
3. The memory refresh parameter determination method according to claim 2, wherein the step of obtaining the data retention time of each memory unit in the semiconductor under test in a data retention test comprises:

   Performing mass production testing on the semiconductor to be tested to obtain a test result of the semiconductor to be tested;

   The data retention time of each memory unit is extracted from the test results.
4. The method for determining memory refresh parameters according to claim 1, wherein, after determining the time ratio between the data retention time of each memory cell in the semiconductor to be tested and the reference data retention time of the reference memory cell, the method further comprises:

   The time ratio corresponding to each of the memory units is stored in a preset storage module in the semiconductor to be tested.
5. The method for determining memory refresh parameters according to claim 1, wherein the method further comprises:

   The target refresh amount corresponding to each of the memory cells is stored in a preset storage module in the semiconductor to be tested.
6. According to the memory refresh parameter determination method according to claim 4 or 5, wherein the preset storage module is a readable register in the semiconductor to be tested.
7. The memory refresh parameter determination method according to claim 1, wherein, for each of the memory units, determining the target refresh interval duration of the memory unit according to the reference refresh interval duration of the reference memory unit and the time ratio comprises:

   For each of the memory units, the ratio between the reference refresh interval duration of the reference memory unit and the time ratio corresponding to the memory unit is calculated to obtain the target refresh interval duration of the memory unit.
8. The method for determining memory refresh parameters according to claim 1, wherein for each of the memory units, determining the target refresh amount of the memory unit within the target refresh interval duration according to the ratio of the baseline refresh amount of the memory data of the baseline memory unit within the baseline refresh interval duration to the time, comprises:

   Determine the reference refresh amount of memory data by the reference memory unit within the reference refresh interval duration;

   For each of the memory units, the ratio between the reference refresh amount and the time ratio corresponding to the memory unit is calculated to obtain the target refresh amount of the memory unit within the target refresh interval.
9. The memory refresh parameter determination method according to claim 1, wherein the reference refresh amount is the number of refresh units for each data unit in the memory unit within the reference refresh interval.
10. The memory refresh parameter determination method according to claim 1, wherein the semiconductor to be tested is a dynamic random access memory.
11. A memory refresh method, comprising:

    Obtaining a target refresh interval duration of each memory cell in the semiconductor under test, and a target refresh amount within the target refresh interval duration; wherein the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method according to any one of claims 1 to 10;

    Based on the target refresh interval duration and the target refresh amount, each corresponding memory unit in the semiconductor under test is controlled to perform memory refresh.
12. A memory refresh parameter determination device, wherein the device comprises:

    A first determination module is used to determine, for each memory cell in the semiconductor under test, a time ratio between a data retention time of the memory cell and a reference data retention time of a reference memory cell; wherein the reference memory cell refers to a memory cell in the semiconductor under test having the shortest data retention time;

    A second determination module is used to determine, for each of the memory units, a target refresh interval duration of the memory unit according to a reference refresh interval duration of the reference memory unit and the time ratio;

    The third determination module is used to determine, for each of the memory units, a target refresh amount of the memory unit within the target refresh interval duration based on a benchmark refresh amount of the memory data of the benchmark memory unit within the benchmark refresh interval duration and the time ratio.
13. A memory refresh device, wherein the device comprises:

    An acquisition module, used to acquire a target refresh interval duration of each memory unit in the semiconductor to be tested, and a target refresh amount within the target refresh interval duration; wherein the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method according to any one of claims 1 to 10;

    A control module is used to control the corresponding memory units in the semiconductor to be tested to perform memory refresh based on the target refresh interval duration and the target refresh amount.
14. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.
15. An electronic device, comprising:

    Processor; and

    A memory, configured to store executable instructions of the processor;

    The processor is configured to perform the method of any one of claims 1 to 11 by executing the executable instructions.

Images