CN114882922A - Memory cell refreshing method and device and electronic equipment - Google Patents

Memory cell refreshing method and device and electronic equipment Download PDF

Info

Publication number
CN114882922A
CN114882922A CN202210600714.0A CN202210600714A CN114882922A CN 114882922 A CN114882922 A CN 114882922A CN 202210600714 A CN202210600714 A CN 202210600714A CN 114882922 A CN114882922 A CN 114882922A
Authority
CN
China
Prior art keywords
address
memory cell
command
refresh
refreshing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210600714.0A
Other languages
Chinese (zh)
Inventor
苏鹏洲
潘宜飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202210600714.0A priority Critical patent/CN114882922A/en
Publication of CN114882922A publication Critical patent/CN114882922A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

The application discloses a method and a device for refreshing a memory cell and electronic equipment, wherein the method comprises the following steps: when a word line activating command is received, recording the address of a storage unit by using a monitor; when a word line closing command is received, timing by using a timer and keeping the address information of the memory cell within timing time T1; when a refresh command is received, the address of the memory cell stored within the timer time T1 is matched with the refresh address, and if not, the memory cell is refreshed.

Description

Memory cell refreshing method and device and electronic equipment
Technical Field
The present invention relates to the field of data storage technologies, and in particular, to a method and an apparatus for refreshing a memory cell, and an electronic device.
Background
Since the charge on the capacitor in the DRAM is lost after a certain period of time, the data can be stored for a short period of time, and in order to store the data, a periodic refresh operation, i.e., a charge replenishment operation, is performed on the DRAM to maintain the amount of charge stored in the capacitor of the memory array. For example, the capacitance of a memory cell connected to a word line may be refreshed by turning on the word line, that is, the refreshing may be performed in a row unit, but if the word line has been refreshed in a short time when receiving a refresh command, refreshing the memory cell may decrease efficiency, resulting in increased power consumption.
Disclosure of Invention
The application provides a memory cell refreshing method and device and electronic equipment, which are used for solving the problem of low periodic refreshing efficiency of a dynamic random access memory.
In a first aspect, an embodiment of the present application provides a method for refreshing a memory cell, where the method includes:
when a word line activating command is received, recording the address of a storage unit by using a monitor;
when a word line closing command is received, timing by using a timer and keeping the address information of the memory cell within timing time T1;
and when a refresh command is received, matching the address of the memory cell stored in the timing time T1 with a refresh address, and if the address of the memory cell is not matched with the refresh address, refreshing the memory cell.
In some embodiments, when the timed duration of the timer exceeds a timed time T1, the memory cell address recorded in the monitor is cleared.
In some embodiments, the timer time T1 is one refresh cycle.
In some embodiments, the addresses of the memory cells include Bank addresses and row addresses.
In some embodiments, refreshing the memory cell when the address of the memory cell does not match the refresh address includes:
and skipping the memory cell when the Bank address and the row address of the memory cell are matched with the Bank address and the row address of the refresh address, and refreshing the memory cell of which the Bank address and the row address are not matched.
In a second aspect, an embodiment of the present application provides a memory cell refreshing apparatus, including:
the command module is used for sending a word line activating command, a word line closing command and a refreshing command;
the address module is used for sending the address of the storage unit;
the monitoring module is used for recording the address of the storage unit by adopting a monitor when the word line activating command is received;
the timing module is used for timing by adopting a timer when receiving a word line closing command;
and the refreshing module is used for matching the address of the memory unit with a refreshing address when receiving a refreshing command, and refreshing the memory unit if the address of the memory unit is not matched with the refreshing address.
In some embodiments, the monitoring module maintains the address information of the memory cell for a time T1 timed by the timing module.
In some embodiments, the monitoring module is further configured to clear the address of the storage unit recorded in the monitor when the timing duration of the timing module exceeds a timing time T1;
in some embodiments, the timer time T1 is one refresh cycle.
In some embodiments, the command module includes a command decoder through which the command module sends the word line activation command, the word line shutdown command, and the refresh command.
In some embodiments, the addresses of the memory cells include Bank addresses and row addresses.
In some embodiments, the memory cell is a memory cell in a volatile memory.
In a third aspect, an embodiment of the present application provides an electronic device, including at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of memory cell refresh as provided in the first aspect above.
In a fourth aspect, the present disclosure provides a computer storage medium storing a computer program for causing a computer to execute the method for refreshing a memory cell provided in the first aspect.
In the embodiment of the application, when a word line activating command is received, the monitor is used for recording the address of the memory cell, when a word line closing command is received, the timer is used for timing and the address information of the memory cell is kept in the timing time T1, when a refreshing instruction is received, the address of the memory cell stored in the timing time T1 is matched with the refreshing address, if the address of the memory cell is not matched with the refreshing address, the memory cell is refreshed, the refreshing times are reduced, the power consumption is reduced, and meanwhile, the bandwidth occupied by periodic refreshing operation is effectively saved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a flow chart illustrating a method for refreshing a memory cell according to an embodiment of the present application;
FIG. 2 is a block diagram of an overall flow of a memory cell refresh method according to one embodiment of the present application;
FIG. 3 is a block diagram of a memory cell refresh apparatus according to one embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described in detail and clearly with reference to the accompanying drawings. In the description of the embodiments of the present application, "/" means "or" unless otherwise specified, for example, a/B may mean a or B; "and/or" in the text is only an association relationship describing an associated object, and means that three relationships may exist, for example, a and/or B may mean: three cases of a alone, a and B both, and B alone exist, and in addition, "a plurality" means two or more than two in the description of the embodiments of the present application.
In the description of the embodiments of the present application, the term "plurality" means two or more unless otherwise specified, and other terms and the like should be understood similarly, and the preferred embodiments described herein are only for the purpose of illustrating and explaining the present application, and are not intended to limit the present application, and features in the embodiments and examples of the present application may be combined with each other without conflict.
To further illustrate the technical solutions provided by the embodiments of the present application, the following detailed description is made with reference to the accompanying drawings and the detailed description. Although the embodiments of the present application provide method steps as shown in the following embodiments or figures, more or fewer steps may be included in the method based on conventional or non-inventive efforts. In steps where no necessary causal relationship exists logically, the order of execution of the steps is not limited to that provided by the embodiments of the present application. The method may be executed in sequence or in parallel according to the embodiments or methods shown in the drawings during actual processing or execution by a control device.
Since the charge on the capacitor in the DRAM is lost after a certain period of time, the data can be stored for a short period of time, and in order to store the data, a periodic refresh operation, i.e., a charge replenishment operation, is performed on the DRAM to maintain the amount of charge stored in the capacitor of the memory array. For example, the capacitance of a memory cell connected to a word line may be refreshed by turning on the word line, that is, the refreshing may be performed in a row unit, but if the word line has been refreshed in a short time when receiving a refresh command, refreshing the memory cell may decrease efficiency, resulting in increased power consumption.
Based on the above problems, the application provides a memory cell refreshing method and device and an electronic device, which effectively improve the memory cell refreshing efficiency.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The memory cell refresh method in the embodiment of the present application is described in detail below with reference to the drawings.
Fig. 1 shows a schematic flow chart of a memory cell refreshing method provided in an embodiment of the present application, including:
s101: when a word line activation command is received, the monitor is used to record the address of the memory cell.
The DRAM is generally composed of Bank groups, and as shown in fig. 3, the Bank groups include n banks, and when a refresh operation is performed, the refresh operation can be performed in Bank units, and after Bank addresses are confirmed, the word line addresses in each Bank are further confirmed. The word line WL corresponding to the refresh operation is turned on, the data is rewritten into the capacitor of the memory cell by the bit line, and then after the refresh operation is completed, the word line needs to be turned off to store the data. Therefore, whether the corresponding memory cell on the word line is subjected to the refresh operation can be judged by recording whether the word line is turned on or off in the refresh period. As shown in the overall flow chart of the memory cell refreshing method in fig. 2, the address of the memory cell in the embodiment of the present application may be recorded by the monitor after receiving the word line activation command. The addresses of the memory cells may include Bank addresses and row addresses, and the row addresses are word line WL addresses, where the monitor in this embodiment may be a hardware structure including a nonvolatile memory such as NAND or Flash and a controller, or a computer program stored on a medium such as the nonvolatile memory.
S102: when a word line closing command is received, a timer is used for timing and the address information of the memory cell is kept in the timing time T1.
As shown in the overall flow chart of the memory cell refreshing method in fig. 2, when the monitor receives the word line closing command, the monitor indicates that the refreshing is finished, and at this time, the timer also starts to count, during the timing time T1, i.e. during a refresh period, the monitor needs to keep the recorded addresses of the memory cells, the memory cells with the recorded addresses are indicated to be refreshed within the timing time T1, and the duration of a refresh period may be 64ms, 96ms, or 128 ms. In some embodiments, when the counted duration of the timer exceeds the counted duration T1, the addresses of the memory cells recorded in the monitor may be cleared to increase the memory space and reduce the power consumption.
S103: when a refresh command is received, the address of the memory cell stored within the timer period T1 is matched with the refresh address, and if not, the memory cell is refreshed.
When a refresh instruction is received, that is, a next refresh operation command after a refresh operation is completed, matching the address of the memory cell stored within the timing time T1 with a refresh address, where the address of the memory cell stored within the timing time T1 is a Bank address or a word line address corresponding to a memory cell that has been refreshed, as shown in the overall flow chart of the memory cell refresh method shown in fig. 2, if the address does not match, it is determined that the refresh address is not recorded in the monitor, that is, the memory cell corresponding to the Bank address or the word line address has exceeded a refresh cycle, and in order to ensure the integrity of data, the memory cell corresponding to the Bank address or the word line address needs to be refreshed, that is, data is rewritten; if the Bank address and the word line address match, the memory cell corresponding to the Bank address or the word line address is refreshed within the timing T1, and therefore, the memory cell does not need to be refreshed.
In some embodiments, after matching the address of the memory cell stored in the timer T1 with the refresh address, the method further comprises resetting the timer and the monitor, i.e. clearing the address of the memory cell recorded in the monitor, and restarting the timing, so that the next Bank address and the row address are recorded in the next T1 time, and after receiving the refresh command, the address of the memory cell recorded in the monitor is matched with the refresh address in T1 time. In the embodiment of the application, when a word line activating command is received, the monitor is used for recording the address of the memory cell, when a word line closing command is received, the timer is used for timing and the address information of the memory cell is kept in the timing time T1, when a refreshing instruction is received, the address of the memory cell stored in the timing time T1 is matched with the refreshing address, if the address of the memory cell is not matched with the refreshing address, the memory cell is refreshed, the refreshing times are reduced, the power consumption is reduced, and meanwhile, the bandwidth occupied by periodic refreshing operation is effectively saved.
The present application also provides a memory cell refreshing apparatus, as shown in fig. 3, the apparatus including:
a command module 301, configured to send a word line activation command, a word line shutdown command, and a refresh command; the commands sent by the command module 301 include not only a word line activation command, a word line deactivation command, and a refresh command, but also Bank addresses and row addresses corresponding to the commands.
An address module 302 for sending an address of a memory location; the addresses of the memory cells sent by the address module 302 include Bank addresses and row addresses.
A monitoring module 303, configured to record an address of a memory cell by using a monitor when the word line activation command is received;
a timing module 304, configured to use a timer to time when receiving a word line shutdown command; during the timer time T1, i.e. during a refresh period, the monitoring module 303 needs to maintain the addresses of the memory cells recorded with the addresses, the memory cells recorded with the addresses are indicated to be refreshed within the timer time T1, a refresh period may have a duration of 64ms, 96ms, or 128ms, and when the timer duration of the timer in the timing module 304 exceeds the timer time T1, the addresses of the memory cells recorded in the monitoring module may be cleared to increase the memory space and reduce the power consumption.
The refresh module 305 is configured to match the address of the memory cell with a refresh address when receiving a refresh command, and refresh the memory cell if the address of the memory cell does not match the refresh address.
When the DRAM performs a refresh operation, the DRAM may be refreshed in Bank units, the refresh command includes a Bank address to be refreshed and a row address (i.e., a word line address), and after receiving the refresh command issued by the command module 301, the refresh module 305 may perform a refresh operation as neededBank address to be refreshed and word line address in Bank refresh corresponding Bank and word line WL, as shown in FIG. 3, after determining refresh Bank1, WL is sequentially refreshed according to word line address 1 …WL n+1 Refreshing is performed.
In some embodiments, the command module 301 includes a command decoder through which the command module 301 sends a word line activation command, a word line shutdown command, and a refresh command.
The command module 301 sends different commands periodically through the command decoder, for example, a word line activation command to the address module 302 and the monitoring module 303, a word line deactivation command to the timing module 304 and the monitoring module 303, and a refresh command to the refresh module 305.
In some embodiments, the memory cells may be memory cells in a volatile memory, such as memory cells in a DRAM.
In some embodiments, the monitor of the monitoring module 303 may be a hardware structure including a non-volatile memory such as NAND or Flash and a controller, or may be a computer program stored on a medium such as the non-volatile memory.
When command block 301 sends a wordline activation command, it triggers address block 302 to send the address of the memory cell, which may include the Bank address and the row address, to a monitor in monitor block 303, which records the address of the memory cell.
When the command block 301 sends a word line close command, indicating that the refresh is over, the timer in the timing block 304 starts counting and the monitoring block 303 needs to keep the recorded addresses of the memory cells within the counted time T1, and the memory cells whose addresses are recorded by the monitor in the monitored block 303 are indicated to be refreshed within the counted time T1. In some embodiments, when the timing duration of the timing module 304 exceeds the timing time T1, the memory location addresses recorded by the monitor in the monitoring module 303 may be cleared to increase the memory space and reduce the power consumption.
After the refresh module 305 receives the refresh command, the memory cell address recorded by the monitor in the monitoring module 303 is obtained, and the memory cell address is matched with the refresh address, if the memory cell address is not matched with the refresh address, it indicates that the refresh address is not recorded in the monitoring module 303, that is, the memory cell corresponding to the Bank address or the word line address has exceeded the refresh cycle, and in order to ensure the integrity of the data, the memory cell corresponding to the Bank address or the word line address needs to be refreshed by the refresh module 305, that is, data is rewritten. If the Bank address and the word line address match, the memory cell corresponding to the Bank address or the word line address is refreshed within the timing T1, and therefore, the memory cell does not need to be refreshed.
In some embodiments, after matching the addresses of the memory cells saved by the monitoring module 303 within the timing time T1 with the refresh addresses in the refresh module 305, the method further includes resetting the monitoring module 303 and the timing module 304, that is, clearing the addresses of the memory cells recorded by the monitor in the monitoring module 303, and restarting timing by the timing module 304, so as to record the address of the next memory cell within the next time T1, and matching the addresses of the memory cells recorded by the monitoring module 303 with the refresh addresses within the time T1 after receiving the refresh command from the command module 301.
In the embodiment of the apparatus of the present application, after the command module 301 sends a word line activation command, the address module 302 is triggered to send an address of a memory cell to the monitor in the monitoring module 303, the monitor in the monitoring module 303 records the address of the memory cell, and when the command module 301 sends a word line closing command, the timing module 304 uses a timer to time and maintain the address of the memory cell recorded in the monitor in the monitoring module 303 within a timing time T1, when the command module 301 sends a refresh instruction to the refresh module 305, the address of the memory cell stored within the timing time T1 is matched with the refresh address, and if the addresses are not matched, the memory cell is refreshed, so that the refresh frequency is reduced, the power consumption is reduced, and meanwhile, the bandwidth occupied by the periodic refresh operation is effectively saved.
Having described the memory cell refresh method and apparatus of the exemplary embodiments of the present application, an electronic device according to another exemplary embodiment of the present application is next described.
As will be appreciated by one skilled in the art, aspects of the present application may be embodied as a system, method or program product. Accordingly, various aspects of the present application may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.
In some possible implementations, an electronic device according to the present application may include at least one processor, and at least one memory. The memory stores program code, and when the program code is executed by the processor, the program code causes the processor to execute the steps of the memory cell refreshing method according to various exemplary embodiments of the present application described above in the specification.
The electronic device 130 according to this embodiment of the present application, i.e., the above-described memory cell refresh device, is described below with reference to fig. 4. The electronic device 130 shown in fig. 4 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.
As shown in fig. 4, the electronic device 130 is represented in the form of a general electronic device. The components of the electronic device 130 may include, but are not limited to: the at least one processor 131, the at least one memory 132, and a bus 133 that connects the various system components (including the memory 132 and the processor 131).
Bus 133 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor, or a local bus using any of a variety of bus architectures.
The memory 132 may include readable media in the form of volatile memory, such as Random Access Memory (RAM)1321 and/or cache memory 1322, and may further include Read Only Memory (ROM) 1323.
Memory 132 may also include a program/utility 1325 having a set (at least one) of program modules 1324, such program modules 1324 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.
The electronic device 130 may also communicate with one or more external devices 134 (e.g., keyboard, pointing device, etc.), with one or more devices that enable a user to interact with the electronic device 130, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 130 to communicate with one or more other electronic devices. Such communication may occur via input/output (I/O) interfaces 135. Also, the electronic device 130 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) via the network adapter 136. As shown, network adapter 136 communicates with other modules for electronic device 130 over bus 133. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with electronic device 130, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.
In some possible embodiments, aspects of a memory cell refresh method provided herein may also be implemented in the form of a program product including program code for causing a computer device to perform the steps of a memory cell refresh method according to various exemplary embodiments of the present application described above in this specification when the program product is run on the computer device.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The program product for monitoring of the embodiments of the present application may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on an electronic device. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the consumer electronic device, partly on the consumer electronic device, as a stand-alone software package, partly on the consumer electronic device and partly on a remote electronic device, or entirely on the remote electronic device or server. In the case of remote electronic devices, the remote electronic devices may be connected to the consumer electronic device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to external electronic devices (e.g., through the internet using an internet service provider).
It should be noted that although several units or sub-units of the apparatus are mentioned in the above detailed description, such division is merely exemplary and not mandatory. Indeed, the features and functions of two or more units described above may be embodied in one unit, according to embodiments of the application. Conversely, the features and functions of one unit described above may be further divided into embodiments by a plurality of units.
Further, while the operations of the methods of the present application are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and block diagrams, and combinations of flows and blocks in the flow diagrams and block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (15)

1. A method for refreshing a memory cell, comprising:
when a word line activating command is received, recording the address of a storage unit by using a monitor;
when a word line closing command is received, timing by using a timer and keeping the address information of the memory cell within timing time T1;
and when a refresh command is received, matching the address of the memory cell stored in the timing time T1 with a refresh address, and if the address of the memory cell is not matched with the refresh address, refreshing the memory cell.
2. The method of claim 1, further comprising:
and when the timing duration of the timer exceeds the timing time T1, clearing the memory cell address recorded in the monitor.
3. The method of claim 2, wherein the timer T1 is a refresh period.
4. The method of claim 1, wherein the addresses of the memory cells comprise Bank addresses and row addresses.
5. The method of claim 4, wherein refreshing the memory cell when the address of the memory cell does not match the refresh address comprises:
and skipping the memory cell when the Bank address and the row address of the memory cell are matched with the Bank address and the row address of the refresh address, and refreshing the memory cell of which the Bank address and the row address are not matched.
6. A memory cell refresh apparatus, comprising:
the command module is used for sending a word line activating command, a word line closing command and a refreshing command;
the address module is used for sending the address of the storage unit;
the monitoring module is used for recording the address of the storage unit by adopting a monitor when the word line activating command is received;
the timing module is used for timing by adopting a timer when receiving a word line closing command;
and the refreshing module is used for matching the address of the memory unit with a refreshing address when receiving a refreshing command, and refreshing the memory unit if the address of the memory unit is not matched with the refreshing address.
7. The apparatus of claim 6,
the monitoring module keeps the address information of the memory unit within the timing module timing time T1.
8. The apparatus of claim 7,
the monitoring module is further configured to clear the address of the storage unit recorded in the monitor when the timing duration of the timing module exceeds a timing time T1.
9. The apparatus of claim 8,
the timer time T1 is a refresh period.
10. The apparatus of claim 6,
the command module includes a command decoder through which the command module sends the word line activation command, the word line shutdown command, and the refresh command.
11. The apparatus of claim 6,
the addresses of the memory cells include Bank addresses and row addresses.
12. The apparatus of claim 6,
the storage unit is a storage unit in a volatile memory.
13. An electronic device comprising at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.
14. A computer storage medium, characterized in that the computer storage medium stores a computer program for causing a computer to perform the method according to any one of claims 1-5.
15. A computer program product comprising computer program instructions, characterized in that the computer program instructions, when executed by a processor, implement the method of any of claims 1-5.
CN202210600714.0A 2022-05-30 2022-05-30 Memory cell refreshing method and device and electronic equipment Pending CN114882922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210600714.0A CN114882922A (en) 2022-05-30 2022-05-30 Memory cell refreshing method and device and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210600714.0A CN114882922A (en) 2022-05-30 2022-05-30 Memory cell refreshing method and device and electronic equipment

Publications (1)

Publication Number Publication Date
CN114882922A true CN114882922A (en) 2022-08-09

Family

ID=82679395

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210600714.0A Pending CN114882922A (en) 2022-05-30 2022-05-30 Memory cell refreshing method and device and electronic equipment

Country Status (1)

Country Link
CN (1) CN114882922A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117393015A (en) * 2023-12-11 2024-01-12 浙江力积存储科技有限公司 Three-dimensional memory architecture, refreshing method thereof and memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117393015A (en) * 2023-12-11 2024-01-12 浙江力积存储科技有限公司 Three-dimensional memory architecture, refreshing method thereof and memory
CN117393015B (en) * 2023-12-11 2024-03-22 浙江力积存储科技有限公司 Three-dimensional memory architecture, refreshing method thereof and memory

Similar Documents

Publication Publication Date Title
US9348527B2 (en) Storing data in persistent hybrid memory
KR101049312B1 (en) Method and system for minimizing impact of refresh operations on volatile memory performance
CN102063943B (en) Nand flash memory parameter automatic detecting system
US20170242584A1 (en) Method of dynamic table journaling
EP2410428A2 (en) Apparatus and method for managing a dram buffer
US20070168624A1 (en) Increased storage capacity for solid state disks using data compression
CN104516471A (en) Method and device for managing power supply of storage system
US8560767B2 (en) Optimizing EDRAM refresh rates in a high performance cache architecture
CN101963891A (en) Method and device for data storage and processing, solid-state drive system and data processing system
CN103853671A (en) Data writing control method and device
US10572168B2 (en) DRAM bank activation management
CN104505117A (en) Dynamic memory refreshing method and refreshing controller
CN114882922A (en) Memory cell refreshing method and device and electronic equipment
CN103378986A (en) System event log recording system and method
CN115565592A (en) Failure unit testing method and device, storage medium and electronic equipment
US8370564B2 (en) Access control device, information processing device, access control program and access control method
US20110078392A1 (en) Writing to memory using adaptive write techniques
CN113590505A (en) Address mapping method, solid state disk controller and solid state disk
CN102376346B (en) Dynamic random access memory unit and its data update method
CN111813340A (en) Instruction response method, system and device based on solid state disk and electronic equipment
KR20100105127A (en) Solid state drive controller and method for operating of the solid state drive controller
CN101499314B (en) Memory device and its updating method
US10564890B2 (en) Runt handling data storage system
CN115857811A (en) Data processing method and device, solid state disk and readable storage medium
US20200004636A1 (en) Data Storage System with Strategic Contention Avoidance

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination