CN115458025A

CN115458025A - Failure test method, test device, test equipment and readable storage medium

Info

Publication number: CN115458025A
Application number: CN202211157141.5A
Authority: CN
Inventors: 赵哲; 吴耆贤
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-09-21
Filing date: 2022-09-21
Publication date: 2022-12-09

Abstract

The disclosure provides a failure test method, a test device, test equipment and a readable storage medium, and relates to the technical field of semiconductors. The failure test method comprises the following steps: periodically writing test data circularly and sequentially shifted into storage units in a storage array, wherein in one test period, aiming at an activated word line in the storage array, the test data is written by taking a storage unit with a specified burst length as a writing unit until the storage array is written, in the next test period, the test data is sequentially shifted, and the shifted test data is written into the storage array until a failure test is completed. By the technical scheme, the test data is written in by taking the storage unit with the appointed burst length as a writing unit, so that the test efficiency can be improved.

Description

Failure test method, test device, test equipment and readable storage medium

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a failure test method for a memory chip, a failure test apparatus for a memory chip, a failure test device for a memory chip, and a computer-readable storage medium.

Background

DRAM (Dynamic Random Access Memory) is a semiconductor Memory widely used in multi-computer systems, and as the structure of DRAM includes transistors, word lines, bit lines, capacitors, metal interconnects, peripheral regions, etc., as the process advances, problems such as structural or functional abnormalities may occur, and these abnormal particles need to be screened out during the yield test process, so that an effective test method is required.

In the related art, a corresponding AC test scheme is required for different failure test items to perform testing, and thousands of test frequencies are required for some test items, such as short circuit tests between memory cells, to complete the testing, which results in the defects of a longer test period, higher test cost, and the like in the existing test scheme.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure aims to provide a failure test method, a test device, test equipment and a readable storage medium for a memory chip, which can solve the problems of long test period and high test cost of the memory chip in the related art.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

According to one aspect of the present disclosure, there is provided a failure test method of a memory chip including a memory array, the failure test method including: and periodically writing test data circularly and sequentially shifted into the storage units in the storage array, wherein in one test period, aiming at the activated word line in the storage array, the test data is written by taking the storage unit with the appointed burst length as a writing unit until the storage array is written, in the next test period, the test data is sequentially shifted, and the shifted test data is written into the storage array until the failure test is completed.

In an exemplary embodiment of the present disclosure, the test data includes two sets of identical 4-bit data, each set of 4-bit data including 1-bit first data and 3-bit second data.

In an exemplary embodiment of the present disclosure, further comprising: in the process of writing the test data, the timing control of the delay time tRCD for the row address to the column address transfer of the memory cell is released.

In an exemplary embodiment of the present disclosure, the memory chip further includes a sense amplifier, two ends of the sense amplifier are respectively connected to a bit line and a reference bit line, the bit line is electrically connected to the memory cell, and in one test cycle, after the test data is written in each time by using a memory cell with a specified burst length as a write unit, the method further includes: and performing an inversion operation on the test data, and writing the inverted test data into the memory cells with the specified burst length, wherein the voltages at two ends of the sense amplifier reversely change based on the operation of writing the inverted test data so as to test the inversion capability of the sense amplifier.

In an exemplary embodiment of the disclosure, after writing the test data after inverting to the memory cell of the specified burst length, the method further includes: performing a precharge operation on the active wordline to close the active wordline, the precharge operation to change a direction of current in the active wordline to accelerate aging of a high resistance location in the active wordline.

In an exemplary embodiment of the present disclosure, the timing control of the precharge valid period tRP is released in the course of performing the precharge operation on the activated word line that is closed.

In an exemplary embodiment of the present disclosure, the writing the test data in a unit of writing of a memory cell of a specified burst length for an activated word line in the memory array until the writing of the memory array is completed includes: after the precharge operation is executed, the activation operation is executed again on the closed activation word line, so that the test data and the inverted test data are written into the next group of memory cells with the specified burst length on the activation word line, and the precharge operation is executed on the closed activation word line until the write operation on all the memory cells on the activation word line is completed.

In an exemplary embodiment of the present disclosure, the performing the activation operation again on the activated word line that is turned off includes: the activation operation is performed 64 times or 128 times per word line in one of the test cycles.

In an exemplary embodiment of the present disclosure, after writing the test data in a unit of writing a memory cell of a specified burst length, the method further includes: reading the test data written between two adjacent memory cells; detecting whether the read result is consistent with the write result; and detecting whether a short circuit occurs between two adjacent memory cells based on the detection result.

In an exemplary embodiment of the disclosure, after writing the test data after inverting to the memory cell of the specified burst length, the method further includes: reading the inverted test data written between two adjacent storage units; detecting whether the read result is consistent with the write result; and detecting whether a short circuit occurs between two adjacent memory cells based on the detection result.

In an exemplary embodiment of the present disclosure, the adjacent two of the memory cells include any one of diagonally adjacent two memory cells, laterally or longitudinally adjacent two memory cells, and two memory cells diagonally spaced by one memory cell.

In an exemplary embodiment of the present disclosure, the periodically writing the cyclically sequentially shifted test data to the memory cells in the memory array further includes: in periodically writing the cyclically sequentially shifted test data to memory cells in a memory array, a column failure phenomenon is detected based on a signal transmission path, wherein the column failure phenomenon includes at least one of a bit line failure, a sense amplifier failure, and an equalizer failure.

In an exemplary embodiment of the present disclosure, before periodically writing the cyclically sequentially shifted test data to the memory cells in the memory array, the method further includes: performing an initialization operation on the memory chip.

According to another aspect of the present disclosure, there is provided a failure test apparatus of a memory chip including a memory array, the failure test apparatus including: the write-in module is used for periodically writing test data which are circularly and sequentially shifted into the storage units in the storage array, wherein in one test period, aiming at an activated word line in the storage array, the test data are written by taking the storage unit with the appointed burst length as a write-in unit until the storage array is written, in the next test period, the test data are sequentially shifted, and the shifted test data are written into the storage array until the failure test is completed.

According to still another aspect of the present disclosure, there is provided a failure test apparatus of a memory chip, including: a processor; and a memory for storing executable instructions for the processor; wherein the processor is configured to execute the failure testing method of the memory chip according to any one of the above-mentioned first aspect through executing the executable instructions.

According to yet another aspect of the present disclosure, there is provided a computer readable medium, on which a computer program is stored, which when executed by a processor, implements the failure testing method of the memory chip as described in the above embodiments.

According to the failure test scheme of the memory chip provided by the embodiment of the disclosure, a periodic failure detection is performed by performing a write operation of test data of cyclic sequential shift on a memory cell of the memory chip, so as to improve the failure test efficiency, specifically, in one test period, a word line in the memory array is activated first, a corresponding memory cell is formed at an intersection of the activated word line and each bit line in the memory array, for the memory cell on the activated word line, corresponding test data is written in sequence by taking the memory cell with the designated burst length as a write unit until the memory cell of the word line is completely activated, then other word lines are activated in sequence until the write operation is completed on the entire memory array, so as to complete one test period, the test data is sequentially taken as a back, so as to obtain test data used in the next test period, and the memory array is rewritten until the failure test is completed, using the test mode, the test data is written in the memory cell with the designated burst length as the write unit, so that the test efficiency can be improved, and by reasonably setting the test data and combining with a sequential shift update mode, the voltage difference between adjacent devices connected with the memory cells can be further tested, so as to realize the similar failure performance test.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

FIG. 1 is a block diagram schematic of a memory according to the present disclosure;

FIG. 2 is a flowchart of a failure testing method for a memory chip according to an embodiment of the disclosure;

FIG. 3 is a partial structural diagram of a memory according to the present disclosure;

FIG. 4 is a flow chart of a failure testing method of a memory chip according to another embodiment of the disclosure;

FIG. 5 is a graph of the potential change for writing data 0 to a memory chip according to an embodiment of the present disclosure;

FIG. 6 is a flow chart of a failure testing method of a memory chip according to still another embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a portion of a memory cell of a memory of the present disclosure;

FIG. 8 is a flow chart of a method for failure testing of a memory chip according to yet another embodiment of the present disclosure;

FIG. 9 is a schematic block diagram of a failure testing apparatus for a memory chip provided by an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a computer system suitable for implementing an electronic device according to an embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and steps, nor do they necessarily have to be performed in the order described. For example, some steps may be decomposed, and some steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation. The terms "a," "an," and "the" are used to indicate the presence of one or more elements/components/etc. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.

As shown in fig. 1, the memory chip includes a memory array 110, a word line driver 120, a bit line selector 130 and a sense amplifier 140, where M × N memory cells may be included in the memory array 110, where M and N are positive integers, the memory cells are arranged in rows and columns to form the memory array 110, the rows and columns are bit word lines and bit lines respectively, each memory cell corresponds to a unique address, memory cells in the same row (e.g., C (M, 1) to C (M, N)) may be connected to the same word line (e.g., word line WLM), the word lines (WL 1 to WLM) may be connected to the word line driver 120, a memory string in which the memory cell is located is selected by controlling a bit line transistor Tb and/or a source line transistor Ts through the bit line selector 130, and a word line read voltage is applied to the word line through the word line driver 120 to select the memory cell in the memory string.

The memory chip further includes a plurality of sense amplifiers 140, each of which is electrically connected to a corresponding bit line BL and a reference bit line/BL (not shown), and amplifies the voltages of the bit line BL and the reference bit line/BL to make the higher side of the voltage higher and the lower side lower and higher to output an identifiable signal during a data read operation.

Referring to fig. 2, an embodiment of the present disclosure first provides a failure testing method of a memory chip, including:

step S202, periodically writing test data circularly and sequentially shifted into the memory cells in the memory array, wherein in a test period, aiming at the activated word line in the memory array, the test data is written by taking the memory cell with the appointed burst length as a writing unit until the memory array is written, in the next test period, the test data is sequentially shifted, and the shifted test data is written into the memory array until the failure test is completed.

Specifically, the test data is 8-bit data, and each bit of data is used to indicate a high level or a low level.

The test data written periodically and shifted in cycle sequence means that in two adjacent test periods, the test data used in the next test period is relative to the test data used in the previous test period, the data on each bit is sequentially moved forward by one bit, and the data at the last bit is moved to the first bit.

The memory cell is respectively connected with a Word Line and a Bit Line, the Word Line is used for controlling the communication of the memory cell and the Bit Line, and the Bit Line is used for reading and writing the memory cell.

For an activated word line in the memory array, the corresponding word line is brought into a ready-to-read/write state by receiving a row activation command, and a failure detection operation is further performed on a read/write basis for each column by receiving a write data command and a corresponding column address signal.

Burst refers to a mode of continuously transmitting data in adjacent memory cells in the same row, the specified Burst length can be at least one memory cell with the Burst length, namely the number of memory cells (columns) involved in continuous transmission, and the transmission efficiency is improved through operation based on Burst so as to improve the failure detection efficiency.

In addition, completing the failure test may be understood as detecting a failure of the memory chip.

In this embodiment, a write operation of test data of cyclic sequential shift is performed on memory cells of a memory chip, and periodic failure detection is performed to improve failure test efficiency, and specifically, in one test cycle, a word line in a memory array is activated first, a corresponding memory cell is formed at an intersection of the activated word line and each bit line in the memory array, for the memory cells on the activated word line, corresponding test data is written in sequence with the memory cell of a specified burst length as a write unit until the memory cell of the word line is completely activated, then other word lines are activated in sequence until the write operation is completed on the entire memory array to complete one test cycle, the test data is sequentially read, test data used in the next test cycle is obtained and written into the memory array again until a failure test is completed, using the test mode, the test data is written in the memory cell of the specified burst length as the write unit, test efficiency can be improved, and by setting the test data reasonably and combining with an update mode of sequential shift, voltage difference between adjacent devices connected with the memory cells can be screened out, a plurality of types of failures can be realized, and the memory chip can be further tested effectively, and the performance of the similar memory chips can be further unstable.

Wherein the first data in the 4-bit data is 1 and the second data is 0, or the first data in the 4-bit data is 0 and the second data is 1.

Tables 1 to 4 show test data obtained by performing cyclic sequential shifts based on different test periods.

As shown in table 1, in the first test cycle, the word line WL0 is activated first, and then 8-bit data 10001000,8-bit data of one burst length is written, which is composed of two sets of the same 4-bit data, and 1-bit first data is 1,3-bit second data is 0.

TABLE 1

	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0
	1	1	1	1	1	1	1	1
									BL1	0	0	0	0	0	0	0	0
BL2	0	0	0	0	0	0	0	0
									BL3	0	0	0	0	0	0	0	0
BL4	1	1	1	1	1	1	1	1
									BL5	0	0	0	0	0	0	0	0
BL6	0	0	0	0	0	0	0	0
									BL7	0	0	0	0	0	0	0	0

As shown in table 2, in the second test cycle, 10001000 was sequentially shifted to 01000100, and the test data was rewritten with 01000100.

TABLE 2

	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	0	0	0	0	0	0	0
BL1	1	1	1	1	1	1	1	1
									BL2	0	0	0	0	0	0	0	0
BL3	0	0	0	0	0	0	0	0
									BL4	0	0	0	0	0	0	0	0
BL5	1	1	1	1	1	1	1	1
									BL6	0	0	0	0	0	0	0	0
BL7	0	0	0	0	0	0	0	0

As shown in table 3, in the third test period, 01000100 is sequentially shifted to 00100010.

TABLE 3

	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	0	0	0	0	0	0	0
BL1	0	0	0	0	0	0	0	0
									BL2	1	1	1	1	1	1	1	1
BL3	0	0	0	0	0	0	0	0
									BL4	0	0	0	0	0	0	0	0
BL5	0	0	0	0	0	0	0	0
									BL6	1	1	1	1	1	1	1	1
BL7	0	0	0	0	0	0	0	0

As shown in table 4, in the fourth test cycle, 00100010 was sequentially shifted to 00010001.

TABLE 4

	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	0	0	0	0	0	0	0
BL1	0	0	0	0	0	0	0	0
									BL2	0	0	0	0	0	0	0	0
BL3	1	1	1	1	1	1	1	1
									BL4	0	0	0	0	0	0	0	0
BL5	0	0	0	0	0	0	0	0
									BL6	0	0	0	0	0	0	0	0
BL7	1	1	1	1	1	1	1	1

In the embodiment, by reasonably setting the test data and combining the writing mode with the Burst length, the regular writing test is realized, the test on a plurality of column failure types in the memory chip is realized in the writing test process, and the corresponding failure result is obtained, so that the test period is shortened, and the test efficiency is improved.

In an exemplary embodiment of the present disclosure, periodically writing the cyclically sequentially shifted test data to the memory cells in the memory array further comprises:

in periodically writing cyclically sequentially shifted test data to memory cells in a memory array, a column failure phenomenon is detected based on a signal transmission path, wherein the column failure phenomenon includes at least one of a bit line failure, a sense amplifier failure, and an equalizer failure.

As shown in fig. 3, the memory chip further includes a sense amplifier 304, two ends of the sense amplifier 304 are respectively connected to a bit line BL and a reference bit line/BL, and the bit line BL is electrically connected to the memory cell 302.

Specifically, as shown in fig. 3, based on the read/write operation of the test data, the bit line selector 308 selects the corresponding bit line BL, and the transmission paths of the corresponding signals are: memory cell 302-bit line BL-sense amplifier 304-equalizer 306 and output via LIO terminal.

The memory cell 302 is located at an intersection of a word line WL and a bit line BL and used for storing data, the sense amplifier 304 works with the bit line BL and a reference bit line/BL and is used for detecting and amplifying a Voltage difference between a pair of bit lines BL and the reference bit line/BL, the Equalizer 306 is located between the bit line BL and the reference bit line/BL and is used for providing an equalizing Voltage VEQ (Voltage of Equalizer) so that the bit line BL and the reference bit line/BL are restored to the same potential, the bit line selector 308 is used for selecting the bit line BL performing read-write operation and controlling the bit line BL to be turned on or off, namely controlling whether the read-write operation is performed on the memory cell 302 through the bit line and outputting the read data through the LIO terminal.

The detection of column failure types such as bit lines, sense amplifiers, equalizers and the like is realized by reading and writing test data.

In an exemplary embodiment of the present disclosure, further comprising: in writing test data, timing control of a delay time tRCD for transferring a row address to a column address of a memory cell is released.

tRCD is specifically the delay from RAS (row address signal) to CAS (column address signal), where a row corresponds to a wordline and a column corresponds to a bitline, i.e., the delay from when a wordline is activated to when the corresponding bitline address is found and the addressing is completed.

In this embodiment, because the tRCD has a large influence on the frequency of the memory chip, the tRCD is not limited, which is beneficial to realizing the high-frequency operation of the memory chip, so as to improve the test efficiency.

As shown in fig. 4, in one test cycle, the method for performing failure test of a memory chip includes:

in step S402, test data is written in a unit of a write unit of a memory cell of a specified burst length.

In step S404, an inversion operation is performed on the test data.

In step S406, the inverted test data is written into the memory cell with the specified burst length, and the voltages at the two ends of the sense amplifier are inversely changed based on the operation of writing the inverted test data, so as to test the inversion capability of the sense amplifier.

After step S406 is completed, the process returns to step S402, and for the next write unit, the original test data is written first, and then the test data after inversion is written.

Specifically, as shown in fig. 5, for any memory cell, if "0" is written based on the test data, VEQ is off, WL and SA are on, the potential of the reference bit line/BL is pulled high, the potential of the bit line BL is pulled low, and the test data is inverted, that is, "1" is written, at which time the potential of the bit line BL is pulled high and the potential of the reference bit line/BL is pulled low, and the inversion capability of the sense amplifier can be detected based on the sensing of the voltage change across the sense amplifier.

In this embodiment, for a group of memory cells with burst lengths, a group of test data and a group of inverted test data are continuously written to generate an inverse change in the voltage across the sense amplifier, and based on the inverse change in the voltage, the detection of the inversion capability of the sense amplifier can be synchronously achieved.

In addition, for the operation of writing "1", the operation of charging the capacitor in the memory cell corresponds, and for the operation of writing "0", the operation of discharging the capacitor in the memory cell corresponds, so that the operation of charging and discharging the word line WL is reflected on the word line WL, and therefore, by writing the inverted detection data, the damage to the weak position such as the easy breakage in the word line can be accelerated, and the failure detection can be accelerated.

Tables 5 to 8 show inverted test data obtained by inverting the test data in tables 1 to 4 and then performing cyclic order shift based on different test periods.

TABLE 5

As shown in table 6, in the second test cycle, 01110111 was sequentially shifted to 10111011, and was rewritten using 10111011 as test data.

TABLE 6

	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0
	1	1	1	1	1	1	1	1
									BL1	0	0	0	0	0	0	0	0
BL2	1	1	1	1	1	1	1	1
									BL3	1	1	1	1	1	1	1	1
BL4	1	1	1	1	1	1	1	1
									BL5	0	0	0	0	0	0	0	0
BL6	1	1	1	1	1	1	1	1
									BL7	1	1	1	1	1	1	1	1

As shown in Table 7, in the third test cycle, 10111011 was sequentially shifted to 11011101.

TABLE 7

As shown in table 8, in the fourth test cycle, 11011101 was sequentially shifted to result in 11101110.

TABLE 8

	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0
	1	1	1	1	1	1	1	1
									BL1	1	1	1	1	1	1	1	1
BL2	1	1	1	1	1	1	1	1
									BL3	0	0	0	0	0	0	0	0
BL4	1	1	1	1	1	1	1	1
									BL5	1	1	1	1	1	1	1	1
BL6	1	1	1	1	1	1	1	1
									BL7	0	0	0	0	0	0	0	0

As shown in fig. 6, in one test cycle, the method for performing failure test of a memory chip includes:

in step S602, test data is written in a unit of a memory cell with a specified burst length as a write unit.

In step S604, the negation operation is performed on the test data.

In step S606, the test data after inversion is written in the memory cell with the specified burst length.

In step S608, a precharge operation is performed on the active word line to close the active word line, and the precharge operation is used to change the direction of current in the active word line to accelerate aging of the high-resistance location in the active word line.

Specifically, the precharge command is used to precharge the activated row to end the active state, and after the precharge is ended, the activated row returns to the idle state, and may also be activated again.

Since the addressing of DRAM has exclusivity, after completing the read/write operation, if another row of the same bank (8 banks are included in one die, and one row of each bank has shared active and precharge circuits), the original working row is closed, the row/column address is retransmitted, the existing working row is closed, the operation of preparing to open a new row is the precharge operation, the precharge can be controlled by a command, or the chip can be automatically precharged after each read/write operation by an auxiliary setting.

In this embodiment, after the write operation of one group of the detection data and the inverted detection data is completed, the activated row, that is, the activated word line is precharged to close the word line, the word line is reactivated before the write operation of the next group of the memory cells is performed, and the word line is precharged again after the write operation, so that the word line can alternately generate a forward current and a reverse current by repeatedly and alternately performing the precharge and the activation operations, and further the aging of the high resistance position in the word line can be accelerated, thereby detecting the reliability of the high resistance position in the word line while detecting a plurality of devices connected to the memory cells.

In one exemplary embodiment of the present disclosure, the timing control of the precharge valid period tRP is released in the process of performing the precharge operation on the closed activated word line.

In this embodiment, a precharge validity period tRP (DRAM Row Cycle Time) refers to a minimum Time between two Row activation commands in the same bank, i.e., an interval from the end of one Row access to the restart, and by removing the limitation on the precharge validity period, it is advantageous to ensure the stability of the failure detection execution process.

In one exemplary embodiment of the present disclosure, writing test data in a unit of writing a memory cell of a specified burst length for an activated word line in a memory array until the memory array is completely written includes:

after performing the precharge operation, performing the active operation again on the closed active word line to perform the writing of the test data and the inverted test data on the next group of memory cells of the specified burst length on the active word line, and performing the precharge operation on the closed active word line until the writing operation on all the memory cells on the active word line is completed.

In one exemplary embodiment of the present disclosure, performing the activation operation again on the closed activated word line includes: in one test cycle, 64 or 128 activation operations are performed per word line.

In this embodiment, since each word line is connected to a plurality of memory cells, and the memory cell with the specified burst length is used as a write unit, the detection operation of one word line in one detection period is completed by operating the plurality of write units, so that reliable detection of a plurality of related failure positions on one word line is ensured.

In an exemplary embodiment of the present disclosure, after writing the test data in a unit of writing the memory cell of the specified burst length, the method further includes: reading test data written between two adjacent storage units; detecting whether the read result is consistent with the write result; whether a short circuit occurs between two adjacent memory cells is detected based on the detection result.

In an exemplary embodiment of the present disclosure, after writing the test data after inverting to the memory cell of the specified burst length, the method further includes: reading the inverted test data written between two adjacent storage units; detecting whether the read result is consistent with the write result; whether a short circuit occurs between two adjacent memory cells is detected based on the detection result.

In this embodiment, after the writing of the test data is completed, the data reading operation is performed on the memory cells, and whether the read result is consistent with the written test data or not is detected, so as to determine whether a short circuit phenomenon occurs between two adjacent memory cells based on the detection result.

In an exemplary embodiment of the present disclosure, the adjacent two memory cells include any one of diagonally adjacent two memory cells, horizontally or vertically adjacent two memory cells, and diagonally spaced by one memory cell.

Specifically, as shown in fig. 7, the failure detection scheme according to the present disclosure, taking C22 as an example, can detect a short circuit failure between C22 and C23, can also detect a short circuit failure between C22 and C11, detect a short circuit failure between C22 and C31, detect a short circuit failure between C22 and C32, detect a short circuit failure between C22 and C34, and detect a short circuit failure between C22 and C43, and the like.

As shown in fig. 8, in an exemplary embodiment of the present disclosure, before periodically writing the cyclically sequentially shifted test data to the memory cells in the memory array, the method further includes:

in step S802, an initialization operation is performed on the memory chip.

Step S804, in a detection period, activates the word line, and writes the test data in the unit of writing the memory cell with the specified burst length.

Step S806, perform an inversion operation on the test data, and write the inverted test data in the memory cell with the specified burst length.

In step S808, a precharge operation is performed on the activated word line to close the activated word line.

The steps S804 to S808 are repeatedly executed to execute the writing of the test data, the writing of the inverted test data, and the precharge operation of the activated word line on the memory cells of the second group with the specified burst length.

In step S810, the detection step is repeatedly executed 64 times or 128 times, and the detection of one word line in one detection period is completed.

And activating the next word line, and repeatedly executing the steps S804 to S810 until the detection of all the word lines on the memory array is completed.

Step S812, detecting that a test cycle is completed, sequentially shifting the test data to obtain test data corresponding to a next test cycle, so as to complete the test operation of the next test cycle.

In step S814, it is detected that the number of completed detection cycles reaches the cycle threshold, and failure detection is completed.

The failure test apparatus 900 of a memory chip according to one embodiment of the present invention is described below with reference to fig. 9, the memory chip includes a memory array, and the failure test apparatus 900 of the memory chip shown in fig. 9 is only an example and should not bring any limitation to the function and the use range of the embodiment of the present invention.

Expressed in the form of hardware modules, the components of the failure testing device 900 may include, but are not limited to: a writing module 902, configured to write cyclically and sequentially shifted test data into memory cells in a memory array periodically, where in a test period, for an activated word line in the memory array, the test data is written in a unit of writing in a memory cell with a specified burst length until the memory array is written, and in a next test period, the test data is sequentially shifted, and the shifted test data is written in the memory array until a failure test is completed.

Referring now to FIG. 10, shown is a block diagram of a computer system 1000 suitable for use in implementing the electronic devices of embodiments of the present disclosure. The computer system 1000 of the electronic device shown in fig. 10 is only an example, and should not bring any limitation to the function and the scope of use of the embodiments of the present disclosure.

As shown in fig. 10, the computer system 1000 includes a Central Processing Unit (CPU) 1001 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1002 or a program loaded from a storage section 1008 into a Random Access Memory (RAM) 1003. In the RAM 1003, various programs and data necessary for system operation are also stored. The CPU 1001, ROM 1002, and RAM 1003 are connected to each other by a bus 1004. An input/output (I/O) interface 1005 is also connected to bus 1004.

The following components are connected to the I/O interface 1005: an input section 1006 including a keyboard, a mouse, and the like; an output section 1007 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage portion 1008 including a hard disk and the like; and a communication section 1009 including a network interface card such as a LAN card, a modem, or the like. The communication section 1009 performs communication processing via a network such as the internet. The driver 1010 is also connected to the I/O interface 1005 as necessary. A removable medium 1011 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 1010 as necessary, so that a computer program read out therefrom is mounted into the storage section 1008 as necessary.

In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network through the communication part 1009 and/or installed from the removable medium 1011. The computer program executes the above-described functions defined in the system of the present application when executed by the Central Processing Unit (CPU) 1001.

It should be noted that the computer readable media shown in the present disclosure may be computer readable signal media or computer readable storage media or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer-readable signal medium may include a propagated data signal with computer-readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units described in the embodiments of the present disclosure may be implemented by software or hardware, and the described units may also be disposed in a processor. Wherein the names of the elements do not in some way constitute a limitation on the elements themselves.

As another aspect, the present application also provides a computer-readable medium, which may be contained in the electronic device described in the above embodiments; or may be separate and not incorporated into the electronic device. The computer readable medium carries one or more programs which, when executed by an electronic device, cause the electronic device to implement the failure test method of the memory chip as in the above embodiments.

For example, the electronic device may implement the following as shown in fig. 2: step S202, periodically writing test data circularly and sequentially shifted into the memory cells in the memory array, wherein in a test period, aiming at the activated word line in the memory array, the test data is written by taking the memory cell with the appointed burst length as a writing unit until the memory array is written, in the next test period, the test data is sequentially shifted, and the shifted test data is written into the memory array until the failure test is completed.

It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken into multiple step executions, etc.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, and may also be implemented by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice in the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A failure test method of a memory chip, wherein the memory chip includes a memory array, the failure test method comprising:

periodically writing cyclically sequentially shifted test data to memory cells in the memory array,

in one test period, aiming at an activated word line in the storage array, writing the test data by using a storage unit with a specified burst length as a writing unit until the storage array is written, sequentially shifting the test data in the next test period, and writing the shifted test data in the storage array until a failure test is completed.

2. The failure test method of a memory chip according to claim 1,

the test data includes two sets of identical 4-bit data, each set of 4-bit data including 1-bit first data and 3-bit second data.

3. The method of claim 1, further comprising:

in the process of writing the test data, the timing control of the delay time tRCD for the row address to column address transfer of the memory cell is released.

4. The method of claim 1, wherein the memory chip further comprises a sense amplifier, two ends of the sense amplifier are respectively connected to a bit line and a reference bit line, the bit line is electrically connected to the memory cell, and in one test cycle, after the test data is written in a unit of writing a memory cell with a specified burst length each time, the method further comprises:

performing an inversion operation on the test data, and writing the inverted test data in the memory cell with the specified burst length,

and on the basis of the operation of writing the test data after inversion, the voltage at two ends of the sensitive amplifier is reversely changed so as to test the inversion capability of the sensitive amplifier.

5. The method for testing the failure of the memory chip according to claim 4, wherein after the writing of the test data after the negation into the memory cell with the specified burst length, the method further comprises:

performing a precharge operation on the active wordline to close the active wordline, the precharge operation to change a direction of current in the active wordline to accelerate aging of a high resistance location in the active wordline.

6. The failure test method of a memory chip according to claim 5,

releasing the timing control of the precharge active period tRP during the precharge operation performed on the activated word line that is closed.

7. The method for testing the failure of the memory chip according to claim 5, wherein the writing the test data in a unit of writing a memory cell with a specified burst length for an activated word line in the memory array until the memory array is completely written comprises:

after the precharge operation is executed, the activation operation is executed again on the closed activation word line, so that the test data and the inverted test data are written into the next group of memory cells with the specified burst length on the activation word line, and the precharge operation is executed on the closed activation word line until the write operation on all the memory cells on the activation word line is completed.

8. The method of claim 7, wherein performing the activation operation again on the activated word line that is turned off comprises:

in one of the test periods, the activation operation is performed 64 times or 128 times per word line.

9. The method for testing the failure of the memory chip according to claim 1, further comprising, after writing the test data in units of memory cells of a specified burst length as writing units:

reading the test data written between two adjacent memory cells;

detecting whether the read result is consistent with the write result;

and detecting whether a short circuit occurs between two adjacent memory cells based on the detection result.

10. The method for testing the failure of the memory chip according to claim 4, wherein after the test data after the negation is written into the memory cell with the specified burst length, the method further comprises:

reading the inverted test data written between two adjacent storage units;

detecting whether the read result is consistent with the write result;

11. The failure test method of a memory chip according to claim 9 or 10,

the two adjacent memory cells include any one of two diagonally adjacent memory cells, two laterally or longitudinally adjacent memory cells, and two memory cells diagonally spaced by one memory cell.

12. The method of claim 1, wherein the periodically writing the cyclically sequentially shifted test data to the memory cells in the memory array further comprises:

in periodically writing the cyclically sequentially shifted test data to memory cells in a memory array, detecting a column failure phenomenon based on a signal transmission path,

wherein the column failure phenomenon comprises at least one of a bit line failure, a sense amplifier failure, and an equalizer failure.

13. The method of testing the failure of a memory chip according to any one of claims 1 to 10, further comprising, before periodically writing cyclically sequentially shifted test data to the memory cells in the memory array:

performing an initialization operation on the memory chip.

14. A failure test apparatus of a memory chip, the memory chip including a memory array, the failure test apparatus comprising:

a write module for periodically writing the cyclically sequentially shifted test data to the memory cells in the memory array,

15. A failure test apparatus of a memory chip, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the failure testing method of the memory chip of any one of claims 1 to 13 via execution of the executable instructions.

16. A computer-readable medium, on which a computer program is stored, which program, when being executed by a processor, carries out a method of failure testing of a memory chip according to any one of claims 1 to 13.