CN116964587A

CN116964587A - Circuit transplanting method and device

Info

Publication number: CN116964587A
Application number: CN202280005149.1A
Authority: CN
Inventors: 李定; 胡贻升; 廖恒; 龙子超; 孟祥隆; 丁翀俊
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-02-25
Filing date: 2022-02-25
Publication date: 2023-10-27
Also published as: WO2023159506A1

Abstract

The embodiment of the application provides a circuit transplanting method and device, relates to the technical field of chips, and can improve the circuit transplanting efficiency under different processes and reduce the complexity during transplanting. The method comprises the following steps: extracting a first device lookup table under a source process and a second device lookup table under a target process; determining a second circuit and a second simulation case which have preset corresponding relations with the first circuit and the first simulation case under the source process under the target process; obtaining a device characteristic value of the first circuit according to a simulation result of direct current simulation on the first circuit and a first device lookup table, and taking the device characteristic value of the first circuit as a first constraint condition for selecting a device of the second circuit; determining the device size of the second circuit meeting the first constraint condition according to the second device lookup table; and carrying out full simulation on the second circuit of the device size meeting the first constraint condition according to the second simulation use case. The embodiment of the application is used for circuit transplanting under different processes.

Description

Circuit transplanting method and device

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to a circuit transplanting method and device.

Background

When switching processes, designers use electronic design automation (Electronic design automation, EDA) software to migrate circuit diagrams and verification cases of original processes to target processes. And then, repeatedly running a device-level integrated circuit general simulation program (simulation program with integrated circuit emphasis, spice) to perform circuit simulation, and performing repeated iterative adjustment according to the circuit output of the simulation result and the standard condition presented by the working state of the device. When the circuit output of the simulation result does not reach the standard or the specification presented by the working state of the device does not reach the standard, the designer continuously adjusts the device parameters under the target process to perform one-time iterative adjustment.

It can be known that, in the iterative process, the designer depends on the spice simulation result to determine whether the working state of the circuit in the target process meets the expectations. However, spice simulation is the operating state of a circuit obtained by solving a circuit equation. When the circuit and the device model in the circuit are complex, the spice simulation is time-consuming, the architecture and the device parameters of the circuit are required to be adjusted through iteration of the spice simulation for a plurality of times, so that the expected device performance is obtained, and the efficiency of the circuit transplanting process is low.

Disclosure of Invention

The embodiment of the application provides a circuit transplanting method and device, which can improve the circuit transplanting efficiency under different processes and reduce the complexity during transplanting.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

in a first aspect, a circuit migration method is provided, the method comprising extracting a first device lookup table under a source process and a second device lookup table under a target process, the first device lookup table comprising device characteristic values of multiple types of devices under the source process, the second device lookup table comprising device characteristic values of multiple types of devices under the target process; determining a second circuit with a preset corresponding relation with the first circuit under the source process under the target process, and determining a second simulation case corresponding to the first simulation case under the source process under the target process; obtaining a device characteristic value of the first circuit according to a simulation result of direct current simulation on the first circuit and a first device lookup table, and taking the device characteristic value of the first circuit as a first constraint condition for selecting a device of the second circuit; determining the device size of the second circuit meeting the first constraint condition according to the second device lookup table; and carrying out full simulation on the second circuit of the device size meeting the first constraint condition according to the second simulation use case. The overall simulation can be understood as simulating the second circuit in a plurality of simulation modes to obtain the performance of the second circuit.

Therefore, the application can solve the problems of complex transplanting flow of the analog circuit integrated circuit under different processes, long iteration time and the like, takes the device characteristic value obtained by the simulation result of the first circuit under the source process as an optimization target (first constraint condition), and uses the second circuit under the target process to match the device characteristic value according to the optimization target, so that a designer can automatically adjust the size of the device by identifying the key device characteristic value of the device as the constraint condition of the circuit under the target process and utilizing the tuning device to achieve key parameter matching among processes, and reduces the design and verification workload of transplanting the circuit to different processes. In one possible design, the method further comprises: under the condition that the second circuit is comprehensively simulated and the specification of the second circuit does not meet the requirement, determining a second constraint condition, wherein the device characteristic value in the second constraint condition is proportional to the device characteristic value in the first constraint condition; determining the device size of the second circuit meeting the second constraint condition according to the second device lookup table, or performing direct current simulation on the second circuit to determine the device size of the second circuit meeting the second constraint condition; and carrying out comprehensive simulation on the second circuit according to the second simulation example, and determining whether the specification of the second circuit meets the requirement.

It should be understood that after the second circuit is fully simulated, if the device specification of some devices in the second circuit does not meet the requirement, for example, if the gain of a certain device does not meet the requirement, the device size may be adjusted, and meanwhile, the optimization target of the second circuit may be adjusted, and the second constraint condition may be used as the optimization target. In general, the original device characteristic value and the random mismatch value in the first constraint condition may be multiplied by a preset coefficient to obtain the original device characteristic value and the random mismatch value in the second constraint condition. In this way, the achievement of the second circuit specification can be finally achieved through the continuous repeated optimization of the small signal characteristic in the constraint condition, namely the original device characteristic value in the constraint condition and the random mismatch value corresponding to the original device characteristic value.

In one possible design, extracting the first device lookup table under the source process and the second device lookup table under the target process includes: scanning the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the source process to obtain the device characteristic values of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the source process; and scanning the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the target process to obtain the device characteristic values of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the target process. The device characteristic values here may include, for example, the transconductance (gm), the output transconductance (gds), the flicker noise (fn), the thermal noise (tn), the direct current (id), the threshold voltage (Vt), and the like of the device. Wherein for transconductance (gm) can be expressed as: gm=f (L, W, V _gs ，V _ds ，V _sb )。V _gs ，V _ds ，V _sb Representing a multi-dimensional voltage, L representing the deviceChannel length, W, represents the channel width of the device. For example, in a first device lookup table, W, L, V of devices may be looked up _gs ，V _ds ，V _sb And obtaining gm corresponding to the device.

In one possible design, the first constraint includes a device characteristic value of a portion of the critical devices in the second circuit configured by the user; the device characteristics of part of the key devices comprise transconductance, output transconductance, flicker noise, thermal noise, direct current and threshold voltage of the devices, and the device characteristic values of part of the key devices are the same as the device characteristic values of the first circuit. Here, the process corresponds to the process of the key information recognized by the second circuit through the GUI input, and the device characteristic value to be optimized is incorporated into the recognized partial device (which can be understood as a key device). The small signal characteristic value in the optimization target in the circuit transplanting process can be configured by a user.

In one possible design, the first constraint further includes key information of a portion of the devices in the second circuit identified by the tuning tool; the key information comprises turn-off information of part of devices in the second circuit, a dimensional proportion relation of part of devices and an input pair tube symmetrical relation of part of devices. Wherein the turn-off information is understood as a device in the second circuit that is turned off. The dimensional relationships of the devices in part are understood to be dimensional relationships from device to device. Wherein the turned-off device does not participate in the simulation when performing the circuit simulation.

In one possible design, the device feature values in the first device lookup table further include first random mismatch information corresponding to the device feature values of the devices in the lower part of the source process, where the first random mismatch information is used to indicate mismatch characteristics of the device feature values obtained by simulating the devices in the source process; the device characteristic values in the second device lookup table further comprise second random mismatch information corresponding to the device characteristic values of the part of devices under the target process, and the second random mismatch information is used for indicating mismatch characteristics of the device characteristic values obtained by simulating the devices under the target process. The first random mismatch information is a mismatch coefficient corresponding to the device, and the random mismatch value corresponding to the device can be determined according to the mismatch coefficient. The random mismatch value is used to indicate a bias range for a device characteristic value of the device, which is acceptable within the bias range. Therefore, when circuit transplanting is carried out, the efficiency of device characteristic value matching can be improved through the bias range.

In one possible design, obtaining the device characteristic value of the first circuit according to the simulation result of the direct current simulation on the first circuit and the first device lookup table includes: performing direct current simulation on the first circuit to obtain an original device characteristic value of part of devices of the first circuit; determining a random mismatch value of an original device characteristic value of a part of devices of the first circuit according to the random mismatch information in the first device lookup table; wherein the device characteristic value of the first circuit includes an original device characteristic value of a portion of the devices of the first circuit and a random mismatch value of the original device characteristic value of the portion of the devices of the first circuit. That is, the first constraint includes an original device characteristic value determined from the simulation result and a random mismatch value determined from random mismatch information in the first device lookup table. For example, the original device characteristic value is transconductance gm _{_org} Its random mismatch value is noted as gm _{_var} The device characteristic value of the device of the second circuit is gm _{_org} Gm between _{_var} All can include gm _{_org} And gm _{_var} . Therefore, a certain matching interval can be reserved in the device characteristic matching process, the tuning time can be effectively shortened, and the circuit transplanting efficiency is improved.

In one possible design, determining the device size of the second circuit that satisfies the first constraint based on the second device lookup table includes: and searching a device which satisfies the device characteristic value and the random mismatch value of the original device characteristic value in the first constraint condition in a second device lookup table, and determining the device size of the device which satisfies the kirchhoff law equation as the device size of the second circuit in the device which satisfies the device characteristic value and the random mismatch value of the original device characteristic value in the first constraint condition. The method directly searches the device size of the device which is matched with the first constraint condition and meets the kirchhoff equation in the second device lookup table, and a simulation tool is not needed, so that tuning time can be effectively shortened.

In one possible design, determining the device size of the second circuit that satisfies the first constraint based on the second device lookup table includes: DC simulation is carried out on the second circuit, the original device characteristic value of part of devices in the second circuit is obtained according to the simulation result, and the random mismatch value of the original device characteristic value of part of devices in the second circuit is obtained based on second random mismatch information in a second device lookup table; when the random mismatch value of the original device characteristic value of the partial device in the second circuit and the original device characteristic value of the partial device in the second circuit does not meet the first constraint condition and the kirchhoff law equation, the device size of the second circuit is adjusted; performing direct current simulation on the second circuit with the device size adjusted, obtaining the original device characteristic value of part of devices in the second circuit with the device size adjusted according to the simulation result, and obtaining the random mismatch value of the original device characteristic value of part of devices in the second circuit with the device size adjusted based on a second device lookup table; and determining whether the random mismatch value of the original device characteristic value of the partial device in the second circuit and the original device characteristic value of the partial device in the second circuit after the device size is adjusted meets a first constraint condition and a kirchhoff law equation.

The accuracy of the device size of the second circuit determined by the direct current simulation is relatively high compared with the accuracy of the device size determined directly from the second device lookup table.

In one possible design, the device characteristics of the same type of device may differ under the source and target processes. The device dimensions of the same type of device may also vary.

In a second aspect, there is provided a tuning device comprising a processor coupled to a memory; a memory for storing a computer program or instructions; a processor for executing a computer program or instructions stored in a memory to cause a tuning device to perform the following process: extracting a first device lookup table under a source process and a second device lookup table under a target process, wherein the first device lookup table comprises device characteristic values of various types of devices under the source process, and the second device lookup table comprises device characteristic values of various types of devices under the target process; determining a second circuit with a preset corresponding relation with the first circuit under the source process under the target process, and determining a second simulation case corresponding to the first simulation case under the source process under the target process; obtaining a device characteristic value of the first circuit according to a simulation result of direct current simulation on the first circuit and a first device lookup table, and taking the device characteristic value of the first circuit as a first constraint condition for selecting a device of the second circuit; determining the device size of the second circuit meeting the first constraint condition according to the second device lookup table; and carrying out full simulation on the second circuit of the device size meeting the first constraint condition according to the second simulation use case.

The advantages of the second aspect can be seen from the description of the advantages in the first aspect.

In one possible design, the processor, when executing the computer program or instructions stored in the memory, performs the process performed by the tuning device further includes: under the condition that the second circuit is comprehensively simulated and the specification of the second circuit does not meet the requirement, determining a second constraint condition, wherein the device characteristic value in the second constraint condition is proportional to the device characteristic value in the first constraint condition; determining the device size of the second circuit meeting the second constraint condition according to the second device lookup table, or performing direct current simulation on the second circuit to determine the device size of the second circuit meeting the second constraint condition; and carrying out comprehensive simulation on the second circuit according to the second simulation example, and determining whether the specification of the second circuit meets the requirement.

In one possible design, the processor, when executing the computer program or instructions stored in the memory, includes extracting a first device lookup table under a source process and a second device lookup table under a target process, specifically includes: scanning the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the source process to obtain the device characteristic values of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the source process; and scanning the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the target process to obtain the device characteristic values of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the target process.

In one possible design, the first constraint includes a user-configured device characteristic value of a portion of the critical devices in the second circuit; the device characteristics of part of the key devices comprise transconductance, output transconductance, flicker noise, thermal noise, direct current and threshold voltage of the devices, and the device characteristic values of part of the key devices are the same as the device characteristic values of the first circuit.

In one possible design, the first constraint further includes key information of a portion of the devices in the second circuit identified by the tuning tool; the key information comprises turn-off information of part of devices in the second circuit, a dimensional proportion relation of part of devices and an input pair tube symmetrical relation of part of devices.

In one possible design, the device feature values in the first device lookup table further include first random mismatch information corresponding to the device feature values of the devices in the lower part of the source process, where the first random mismatch information is used to indicate mismatch characteristics of the device feature values obtained by simulating the devices in the source process; the device characteristic values in the second device lookup table further comprise second random mismatch information corresponding to the device characteristic values of the part of devices under the target process, and the second random mismatch information is used for indicating mismatch characteristics of the device characteristic values obtained by simulating the devices under the target process.

In one possible design, the processor is configured to execute a computer program or instructions stored in the memory, where the processor is configured to obtain a device characteristic value of the first circuit according to a simulation result of performing a dc simulation on the first circuit and the first device lookup table, and specifically includes: performing direct current simulation on the first circuit to obtain an original device characteristic value of part of devices of the first circuit; determining a random mismatch value of an original device characteristic value of a part of devices of the first circuit according to the random mismatch information in the first device lookup table; wherein the device characteristic value of the first circuit includes an original device characteristic value of a portion of the devices of the first circuit and a random mismatch value of the original device characteristic value of the portion of the devices of the first circuit.

In one possible design, the processor, when executing the computer program or instructions stored in the memory, includes determining the device size of the second circuit that satisfies the first constraint based on the second device lookup table, specifically includes: and searching a device which satisfies the device characteristic value and the random mismatch value of the original device characteristic value in the first constraint condition in a second device lookup table, and determining the device size of the device which satisfies the kirchhoff law equation as the device size of the second circuit in the device which satisfies the device characteristic value and the random mismatch value of the original device characteristic value in the first constraint condition.

In one possible design, the processor, when executing the computer program or instructions stored in the memory, includes determining the device size of the second circuit that satisfies the first constraint based on the second device lookup table, specifically includes: DC simulation is carried out on the second circuit, the original device characteristic value of part of devices in the second circuit is obtained according to the simulation result, and the random mismatch value of the original device characteristic value of part of devices in the second circuit is obtained based on second random mismatch information in a second device lookup table; when the random mismatch value of the original device characteristic value of the partial device in the second circuit and the original device characteristic value of the partial device in the second circuit does not meet the first constraint condition and the kirchhoff law equation, the device size of the second circuit is adjusted; performing direct current simulation on the second circuit with the device size adjusted, obtaining the original device characteristic value of part of devices in the second circuit with the device size adjusted according to the simulation result, and obtaining the random mismatch value of the original device characteristic value of part of devices in the second circuit with the device size adjusted based on a second device lookup table; and determining whether the random mismatch value of the original device characteristic value of the partial device in the second circuit and the original device characteristic value of the partial device in the second circuit after the device size is adjusted meets a first constraint condition and a kirchhoff law equation.

In one possible design, the device characteristics of the same type of device may differ under the source and target processes.

In a third aspect, there is provided a chip coupled to a memory for reading and executing program instructions stored in the memory to implement the method of the first aspect or any one of the first aspects.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the circuit migration method of any one of the above aspects and any one of the possible implementations.

In a fifth aspect, embodiments of the present application provide a computer program product which, when run on a computer or processor, causes the computer or processor to perform the circuit migration method of any one of the above aspects and any one of the possible implementations.

The corresponding advantages of the other aspects mentioned above may be found in the description of the advantages of the method aspects, and are not repeated here.

Drawings

Fig. 1 is a schematic flow chart of an analog circuit in a switching process according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an EDA software interface for an analog circuit design based on an analog integrated circuit design flow according to an embodiment of the present application;

Fig. 3 is a schematic flow chart of a circuit transplanting method according to an embodiment of the present application;

fig. 4 is a schematic flow chart of a circuit transplanting method according to an embodiment of the present application;

fig. 5 is a schematic circuit diagram of an operational amplifier according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a first circuit under a source process and a second circuit under a target process according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a tuning device according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a tuning device according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a chip according to an embodiment of the present application.

Detailed Description

For ease of understanding, a description of some of the concepts related to the embodiments of the application are given by way of example for reference. As shown below.

Process design kit (Process Design Kit, PDK): the complete set of process files provided for the design of analog/mixed signal integrated circuit (integrated circuit, IC) circuits is a data platform connecting the IC design and the IC process fabrication.

Electronic design automation (Electronic design automation, EDA): the design method is to use computer aided design (computer aided design, CAD) software to complete the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule check, etc.) and other processes of very large scale integrated circuit (Very Large Scale Integration, VLSI) chips.

Analog circuit migration: in analog integrated circuit design, analog circuit migration is a common design methodology for reusing source circuits for target circuits. Analog circuit migration generally includes circuit optimization of integrated circuit device parameter values at the circuit level and physical optimization of device locations and wiring at the layout level. Typically, the source circuit and the target circuit each include a plurality of devices connected at a plurality of nodes. The source circuit and the target circuit may be respectively divided into at least one corresponding module, such as a power module, a receiving module, an amplifying module, a signal processing module, and the like, according to the relatively independent functions implemented by the different circuit portions. Each module includes a portion of the devices, and the respective modules are connected at nodes between the modules, and the respective devices are connected at nodes within the modules and at nodes between the modules.

Source circuit simulation includes dc analysis, ac analysis, transient analysis, and other numerical analysis of the circuit for the entire source circuit.

Hough law (Kirchhoff law): the kirchhoff's first law, also known as kirchhoff's current law, is the manifestation of current continuity on lumped parameter circuits, and its physical background is the principles of conservation of charge. Kirchhoff's current law is a law that determines the relationship between the currents of branches at any node in a circuit, and is therefore also referred to as node current law.

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Wherein, in the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, in the description of the embodiments of the present application, "plurality" means two or more than two.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

The flow of a conventional analog circuit in switching processes can be as shown in fig. 1. The process includes the following steps.

1) Transplanting the circuit and the simulation case of the source process into a new process;

2) Determining the design specification of a circuit to be simulated on the basis that the PDK provides a parameterized device and a simulation model;

3) Manually inputting device parameters and adjustment parameters in the PDK;

4) Performing circuit simulation by repeatedly running a device-level integrated circuit general simulation program, and performing repeated iterative adjustment according to the circuit output of the simulation result and the specification achievement condition presented by the working state of the device;

5) After each adjustment, verifying whether the circuit specification meets the standard or not by using a simulation use case in a spice simulator of the circuit, and if the circuit specification meets the standard, determining that the circuit transplanting is completed;

6) If the circuit is not up to standard, a designer can adjust the size of the device in the circuit according to experience, and then the designer can continuously verify whether the circuit is up to standard through the simulation use case.

In the process of fig. 1, the schematic diagram of the provided circuit diagram and the device parameter editing interface, the simulation operation and the result display interface of the simulation operation, which may be based on the analog circuit design EDA software of the analog integrated circuit design process, may be shown in fig. 2. The designer can input a circuit diagram and adjust the size parameters of the device by operating the graphical window, set simulation conditions on the graphical interface, start simulation and check simulation results. The partial EDA software also provides gradient relation for exploring specific device characteristics and simulation specifications, and provides indication establishment related to circuit design for designers.

It can be seen that in the above iterative process, the designer determines whether the working state of the circuit meets the expectations according to the spice simulation result. However, spice simulation is a circuit operation state obtained by solving a circuit equation. When the circuit and the device model are complex, the spice simulation is time-consuming, and the architecture and the device parameters of the circuit are required to be determined through continuous spice simulation iteration, so that the expected performance is obtained. This process is time consuming, inefficient, and highly dependent on experienced designers.

There are also various ways to improve the design efficiency of analog circuit migration. It is common to use a computer and adjust the device parameters through a data optimization algorithm to find an optimal design for the transplanted circuit based on the variation of the simulation results. Generally, a designer specifies a design space range, such as a circuit structure, a device type, and a size selection range, and specifies design specification indexes, weights, and the like, so that computer software converts a design problem into a mathematical optimization problem, solves the problem through a numerical algorithm, and improves circuit design efficiency by using a computer-automated design.

For example, in the existing multi-objective bayesian optimization-based simulation circuit multi-objective optimization design method, the field of automatic optimization design of simulation circuit parameters in integrated circuit design is mentioned. In particular to a target-passing Bayesian optimization method of a Gaussian process model. In each circuit design iteration of the method, a Gaussian process model is built for each circuit index, a ground confidence interval function is built, and the point for carrying out circuit simulation next time is selected through multi-objective optimization of the low confidence interval function. Compared with the current international mainstream method, the method can greatly reduce the simulation times of the circuit, and find a group of optimal solutions in the multi-objective optimization problem to serve as the final optimization objective of the analog circuit.

Therefore, the automatic design optimizer of the circuit generally performs design exploration and judgment only according to the design space range, the design weight and the target which are input by a designer in advance, and the optimal design result or several optimal outputs are obtained by traversing the design space through an optimization algorithm so as to be selected by the designer. However, in such approaches, when there are too many possible circuit design goals and constraints, it is difficult to provide a complete compromise between all design goals and constraints in a reasonable time, and determining appropriate weights is difficult, typically relying on a designer to assign device parameters based on experience, and incorrect weight assignments may lead to improper design results. In addition, when the circuit scale is large, the more serious the difficulty in design, the lower the efficiency.

In another design, a circuit optimization method and apparatus for analog circuit migration is provided. The analog circuit migration is used to reuse source circuits for target circuits. In the circuit optimization method, a source circuit is divided into at least one direct current path; determining the order of at least one direct current path; the dc paths of the target circuits are optimized one by one in sequence. Although the circuit optimization method and the circuit optimization device can improve the circuit optimization in the analog circuit transplanting, the design aims at the application scene of the circuit transplanting, and when the performance matching adjustment is realized for each direct current path through spice simulation, the corresponding specification requirements are required to be combined for each direct current path, and the automatic design circuit cannot be realized.

Therefore, in the existing circuit design or circuit migration scene, the problems that the circuit design is complex to realize, the efficiency is low, or the automatic design cannot be realized exist. In view of the problems of complex flow and low design efficiency of circuit transplanting of the analog integrated circuit under different processes, the application provides a new automatic optimization method which can realize automatic transplanting of circuit design among different processes.

In some embodiments of the present application, the present application improves the flow of the analog circuit during the switching process, and achieves the overall circuit characteristic matching of the transplanted circuit by matching each device characteristic of the key devices of the same architecture circuit under different processes. The application adopts a mode based on device characteristic matching, such as a mode of device direct current small signal electric characteristic matching, can realize automatic optimization of the circuit by using less resource expenditure, and has lower realization complexity.

The application can be applied to chip technology, and is described with respect to the circuit transplanting process of the analog circuit in the chip during the switching process. The chip is, for example, a system-on-a-chip (SoC), the analog circuit is an analog IP part in the SoC, or the chip is a power management chip (power management unit, PMU) or the like, but of course, other types of chips are also possible, and the application is not limited to the chip scope.

In some embodiments, the switching process may be understood as a process switching of a size of a device in the circuit, for example, a process switching of a minimum channel length, and may specifically be a process switching of a minimum channel length of a portion of the device under a source process. For example, the minimum channel length of the device under the source process is 180nm and the minimum channel length of the device under the new process is 65nm.

A device according to the present application may be understood as, for example, a metal-oxide-semiconductor (MOS) field effect transistor, which is abbreviated as a MOS transistor in the present application.

In the application scene of the application, when circuit transplanting under different processes is realized, the device lookup table under the source process can be obtained by simulating the device under the source process, and the device lookup table under the new process can be obtained by simulating the device under the new process. And (3) automatically identifying the device table look-up table of the source process and manually defining certain device characteristics to obtain device characteristic values of key devices to be matched, which is equivalent to obtaining constraint conditions of the circuit under the condition of optimizing a new process. When the tuning device determines the constraint condition, the tuning device can perform mathematical tuning to obtain the size of the device meeting the constraint condition. And then performing spice simulation on the optimized circuit, and performing iterative processing according to spice simulation achievement conditions.

The circuit migration method of the present application will be described below.

Referring to fig. 3, an embodiment of the present application provides a circuit migration method, which includes the following procedures.

301. The tuning device extracts a first device lookup table under the source process and a second device lookup table under the target process, wherein the first device lookup table comprises device characteristic values of multiple types of devices under the source process, and the second device lookup table comprises device characteristic values of multiple types of devices under the target process.

The tuning device of the present application can be understood as a tuning device installed in a personal computer (personal computer, PC) terminal. The source process is understood to be a process before circuit implantation, and the target process is a new process after circuit implantation.

Under the source process and the target process, devices in the circuit are various, and Direct Current (DC) simulation and noise simulation can be performed on each type of device to obtain device characteristic values of various types of devices.

The device types in the present application include, for example, MOSFETs, bipolar junction transistors (Bipolar Junction Transistors, BJTs), etc., and the device characteristic values may include, for example, transconductance (gm), output transconductance (gds), flicker noise (fn), thermal noise (tn), etc., and may further include other device characteristic values, which are not limited by the present application.

In some embodiments, in the first device lookup table, the device characteristic value of each type of device includes, in addition to the device characteristic value obtained by simulating the device, first random mismatch (random mismatch) information corresponding to the device characteristic value, where the first random mismatch information is used to indicate mismatch characteristics of the device characteristic value obtained by simulating the device under the source process;

in the second device lookup table, the device characteristic value of each type of device comprises a second random mismatch information corresponding to the device characteristic value besides the device characteristic value obtained by simulating the device, and the second random mismatch information is used for indicating the mismatch characteristic of the device characteristic value obtained by simulating the device under the target process.

In the application, the tuning device can determine the random mismatch value according to the random mismatch information, and the random mismatch value is used for indicating the bias range of the device characteristic value, namely the device characteristic value in the bias range is acceptable.

302. The tuning device determines a second circuit with a preset corresponding relation with the first circuit under the source process under the target process, and determines a second simulation case corresponding to the first simulation case under the source process under the target process.

In some embodiments, the tuning device may store preset correspondence between the devices under the active process and the devices under the target process. When the tuning device determines that the first circuit is to be transferred from the source process to the target process, the tuning device determines a device corresponding to each device under the first circuit under the target process according to the preset corresponding relation.

For example, when the device is a MOS device, a MOS device with a standard threshold (SVT) of 0.9V under the source process corresponds to a MOS device with a conventional threshold (RVT) of 0.8V under the target process.

In some embodiments, the first simulation use case and the second simulation use case are the same. For example, in the first simulation example, the signal to noise ratio of the device can be obtained through transient simulation, and the linearity result of the device can be obtained through periodic steady-state simulation.

303. The tuning device obtains a device characteristic value of the first circuit according to a simulation result of direct current simulation on the first circuit and a first device lookup table, and takes the device characteristic value of the first circuit as a first constraint condition for selecting a device of the second circuit.

In some embodiments, the tuning apparatus may perform DC simulation and noise simulation on the device characteristics of the partial devices of the first circuit to obtain the original device characteristic values of the partial devices of the first circuit, and determine the bias range of the original device characteristic values of the partial devices of the first circuit according to the first random mismatch information in the first device lookup table.

That is, the first constraint of the present application may include the original device characteristic value of the partial device of the first circuit and the bias range of the original device characteristic value. The bias range is understood herein to mean that the bias values of the original device characteristic values are acceptable within the bias range.

304. The tuning means determines the device size of the second circuit satisfying the first constraint according to the second device lookup table.

In some embodiments, the tuning apparatus may directly search the second device lookup table extracted in step 301 for a device feature value that satisfies the first constraint condition according to the first constraint condition, and use a device size of a device corresponding to the device feature value that satisfies the first constraint condition as a device size of the second circuit that satisfies the first constraint condition.

In some embodiments, the tuning apparatus may perform DC simulation on the second circuit to obtain a device characteristic value of a part of devices of the second circuit, determine a random mismatch value of the device characteristic value according to the second device lookup table, and determine whether the device characteristic value and the random mismatch value satisfy the first constraint condition. If so, device sizing of the devices in the second circuit; if the random mismatch value does not meet the first constraint condition, the device size of the device in the second circuit can be adjusted, then simulation is continued, a random mismatch value of the device characteristic value is determined in the second device lookup table according to the device characteristic value simulated again, and whether the device characteristic value and the random mismatch value meet the first constraint condition at the moment is continuously determined. For example, the initial device size in the second circuit may be determined according to the corresponding device size in the first circuit before circuit migration, if the simulation result after DC simulation is performed on the devices in the second circuit based on the initial device size of the second circuit and the result determined by table lookup performed on the second device lookup table do not satisfy the first constraint condition, the DC simulation may be continued and the second device lookup table may be searched after the device size of the second circuit is continuously adjusted, so as to determine again whether the simulation result and the table lookup result satisfy the first constraint condition.

305. The tuning device comprehensively simulates the second circuit of the device size meeting the first constraint condition according to the second simulation case.

Under the condition that the device characteristic value and the device size of the second circuit are obtained through the step 304, the second circuit under the target process can be comprehensively simulated, namely, the second circuit is simulated through a plurality of simulation modes, and the performance of the second circuit is obtained. For example, the overall simulation includes obtaining the performance of the overall circuit through transient analysis, ac simulation, periodic steady state simulation (Periodic Steady State, PSS), monte carlo method simulation, etc., to determine whether the performance of the overall circuit meets the requirements. If the requirements are not met, the first constraint condition can be adjusted again, a new optimization target is determined, and the second circuit is subjected to comprehensive simulation again on the basis of adjusting the size of the device, so that whether the performance of the whole circuit after the optimization target meets the requirements is determined.

In this way, the specification of the second circuit is finally achieved by continuously and repeatedly optimizing the device characteristic value and the device size.

Therefore, the application can solve the problems of complex transplanting flow of the analog circuit integrated circuit, long iteration time and the like under different processes, and by adopting the method for matching the characteristic values of the devices, a designer can automatically adjust the size of the devices by using the tuning device by identifying the characteristic values of the key devices of the devices as constraint conditions of the circuits under the target process, so that the matching of key parameters among the processes is achieved, and the design and verification workload of transplanting the circuits to different processes is reduced.

The embodiments of the present application are further described below.

Referring to fig. 4, an embodiment of the present application provides a circuit migration method, which includes the following procedures.

401. The tuning device performs simulation analysis on the device under the source process and the device under the target process, and extracts a first device lookup table under the source process and a second device lookup table under the target process.

Under the source process and the target process, the device characteristic values of the devices of the same type are different.

The first device lookup table includes device characteristic values of a plurality of types of devices under a source process, and the second device lookup table includes device characteristic values of a plurality of types of devices under a target process.

In some embodiments, the tuning device scans the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the source process to obtain the device characteristic value of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the source process;

and scanning the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the target process to obtain the device characteristic values of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the target process.

The extraction of the device characteristic values in the first device lookup table and the second device lookup table in the present application may be understood as the small signal characteristics of the devices, and the first device lookup table and the second device lookup table may be referred to as lookup tables (LUTs) for subsequent processing by the tuning device.

For example, the simulation analysis in step 401 may be DC simulation and noise simulation, and the device characteristic values in the present application may include transconductance (gm), output transconductance (gds), flicker noise (fn), thermal noise (tn), direct current (id), threshold voltage (Vt), and the like of the device, and may further include other device characteristic values, which are not limited by the present application.

Multidimensional voltages, e.g. comprising V of devices _gs (voltage of gate to source), V _ds (drain voltage) and V _sb When the channel length of the device is denoted by L (length) and the width is denoted by (width, W), for example, the application is applied to a circuit in which an analog circuit is a common function circuit, and when the circuit of an operational amplifier is transplanted, as shown in fig. 5, the circuit of an operational amplifier is a circuit including devices such as MOS, resistor, capacitor, and the like, and at this time, after scanningThe calculation formula of the transconductance gm can be shown as formula (1).

g _m ＝f(L，W，V _gs ，V _ds ，V _sb ) Equation (1).

Other device characteristic values can also refer to the calculation mode of gm to obtain a corresponding calculation formula.

It should be noted that, when scanning devices in the source process or the target process, there may be various values of each device characteristic of each device, for example, when obtaining g of a certain type of device _m G at the time of _m There may be a plurality of values. This is because the multidimensional voltage during scanning can be ergodic, e.g. V during scanning a device _gs The range of (2) may be 0-1.2V to obtain multiple g _m Is a value of (2). Likewise, for V _ds And V _sb A certain voltage range may be traversed, corresponding to a plurality of gm values. Similarly, for other device characteristic values, various voltage values may correspond to various device characteristic values.

It will be appreciated that for the first device lookup table, a set of L, W, V _gs ，V _ds ，V _sb Corresponds to a gm value. For other device feature values gds, fn, tn, id and Vt, too, a set of parameters corresponds to one device feature value.

In addition, in some embodiments, the device feature values in the first device lookup table further include first random mismatch information corresponding to device feature values of a portion of the plurality of types of devices under the source process; the first random mismatch information is used for indicating mismatch characteristics of a device characteristic value obtained by simulating a device under a source process. The second device lookup table further comprises second random mismatch information corresponding to device characteristic values of part of devices in the multiple types of devices under the target process, wherein the second random mismatch information is used for indicating mismatch characteristics of the device characteristic values obtained by simulating the devices under the target process.

Wherein the random mismatch information (first random mismatch information and second random mismatch information) includes a mismatch coefficient of a device characteristic value. The random mismatch information is used to determine the deviation range of the device characteristic values, or random mismatch values, which are acceptable as long as the device characteristic values are within the deviation range.

Illustratively, when simulating a plurality of devices under a source process, the mismatch coefficient A of the threshold voltage Vt of the device is obtained by scanning the length of the device _vt . Thus, a lookup table of mismatch coefficients for each threshold voltage of each device can be obtained. A is that _vt The calculation of (2) can be as shown in the formula.

A _vt =f (L), equation (2).

Thus, when circuit migration is performed, a random mismatch value corresponding to a device characteristic value can be determined according to a mismatch coefficient of each device characteristic value, wherein the absolute value of the difference between the random mismatch value and the device characteristic value can be understood as a deviation range in the application.

402. The tuning device determines a second circuit with a preset corresponding relation with the first circuit under the source process under the target process, and determines a second simulation case corresponding to the first simulation case under the source process under the target process.

When determining that the circuit of the first circuit from the source process to the target process is to be transplanted, the optimizing device can firstly transplant the circuit and the simulation case under the condition that the size of the device is unchanged.

The tuning device may read the device type and the device size under the source process, and determine the corresponding device type and the device size under the target process according to the preset correspondence, so as to obtain the device type and the device size of the second circuit. At this time, the device type of the second circuit and the coupling relationship between the devices have been determined, and the device size at this time is only the initial device size, and then the device size of the second circuit needs to be adjusted according to the constraint condition, so that the second circuit meets the optimization objective.

In general, the first simulation case and the second simulation case are identical.

As shown in fig. 6, a schematic diagram of a first circuit under a source process and a second circuit under a target process is shown. It can be seen that the circuit architecture of the first circuit and the second circuit are the same. The difference is that the device parameters and dimensions in the circuit are different. The device parameters include transconductance (gm), output transconductance (gds), flicker noise (fn), thermal noise (tn), direct current (id), and threshold voltage (Vt) among others, above.

403. The tuning device obtains a device characteristic value of the first circuit according to a simulation result of direct current simulation on the first circuit and a first device lookup table, and takes the device characteristic value of the first circuit as a first constraint condition for selecting a device of the second circuit.

In some embodiments, the first constraint includes key information for a portion of the devices in the second circuit identified by the tuning tool.

The key information includes turn-off information of a part of devices in the second circuit, a dimensional proportion relation of the part of devices (for example, when the second circuit includes a current mirror circuit, the lengths of different devices are required to be the same by the current mirror circuit), and an input-pair tube symmetrical relation of the part of devices. The turn-off information may be understood as a device in the second circuit that is turned off.

Illustratively, when the user determines that the tuning tool is to be provided with the second circuit in step 402, the user may enter via a graphical user interface (Graphical User Interface, GUI) to trigger the tuning device to identify key information in the second circuit. The identification of the key information in the second circuit is understood to be the identification of the common electrical structure in the second circuit, and may include a current mirror, an input differential pair, a Photodiode (PD) device, a logic function module, and the like, in addition to the shutdown information, the dimensional proportion relationship, and the input pair symmetry relationship. The above-mentioned proportional relation may further include a proportional relation of the holding current mirror. In addition, the tuning device can identify the devices in the second circuit which do not need to be optimized, namely the devices are determined directly according to the preset corresponding relation among the devices.

For example, the devices requiring the dimensional scaling relationship include M5 and M6 in the second circuit, and the devices requiring no optimization include M7 in the second circuit.

When the tuning tool obtains the key information, a corresponding file can be generated, and the file is used for storing the key information.

In some embodiments, the first constraint further comprises a device characteristic value of a portion of the critical devices in the second circuit configured by the user, the device characteristic value of the portion of the critical devices being the same as the device characteristic value of the first circuit.

The device characteristic values of part of the key devices comprise transconductance (gm), output transconductance (gds), flicker noise (fn), thermal noise (tn), direct current (id), threshold voltage (Vt) and the like of the devices. Here, the key information identified by the second circuit is further processed corresponding to the input of the user through the GUI, and the device characteristic value required to be optimized is incorporated into the identified partial device (which can be understood as a key device). For example, some of the critical devices include M1, M2, M3, M4, M8, and the like in the circuit shown in fig. 6.

In some embodiments, the device characteristic value of the first circuit includes random mismatch information of the original device characteristic value in addition to the original device characteristic value obtained by DC-simulating a part of devices of the first circuit.

When the original device characteristic value and the random mismatch information of the first circuit are determined, the method is equivalent to determining a first constraint condition of selecting the device of the second circuit, namely, the original device characteristic value and the random mismatch information of the first circuit are used as the optimization target of the second circuit at the moment.

The tuning device may perform DC simulation and noise simulation on the first circuit under the source process to obtain an original device characteristic value of a part of devices of the first circuit, and determine a random mismatch value of the original device characteristic value of the part of devices according to random mismatch information of the part of devices under the first circuit.

Alternatively, the tuning device may perform DC simulation and noise simulation on the first circuit under the source process, and perform static characteristic analysis on the device to obtain small signal characteristics (such as g _m 、g _ds 、fnTn, id, vt, etc.), and assists LUKs under the source process in determining random mismatch values for each small signal feature.

Exemplary, in one of the device features g _m For example, the tuning device obtains the bias voltage V of one device of the first circuit through DC simulation _gs 、V _ds 、V _sb As well as the original device characteristics gm of the device _{_org} . Combining device parameters: the channel length L and the width W are searched for a first device lookup table to obtain random mismatch information of the threshold voltage Vt mismatch of the device, namely a mismatch coefficient A _vt 。

Further, by the mismatch coefficient A _vt The tuning device can combine the channel length L and the device width W to derive the standard deviation delta of the threshold voltage Vt of the device _vt 。δ _vt The calculation formula of (2) is shown as formula (3).

It can be appreciated that when the standard deviation delta of the threshold voltage Vt is determined _vt In this case, the standard deviation delta can be further used _vt Obtaining corrected V _gs V after correction _gs Is denoted as V _gs ' at the time V _gs The' calculation formula may be as shown in formula (4).

V _gs ’＝V _gs -n·δ _Vt Equation (4).

Where n is the coefficient of calculated deviation that the designer needs to consider, e.g., the value of n may be 3, indicating tolerance to 3Sigma fluctuations.

Then, V can be utilized _gs ' get device feature gm _{_org} Random mismatch value gm of (2) _{_var} ，gm _{_var} The calculation formula of (2) can be shown as formula (5).

gm _{_var} ＝f(L，W，V _gs ’，V _ds ，V _sb ) Equation (5).

At this time gm _{_org} It is understood that an original device characteristic value of the device, i.e. gm, is the value of an optimization target of the device in a first constraint _{_var} As the gm _{_org} Random mismatch values of (a). So long as the gm value and gm of the device corresponding to the device in the second circuit are the following pairs _{_org} Is at or near the value of (i.e., gm of the device corresponding to the device in the second circuit is gm _{_org} And gm _{_var} Within a range between (including gm _{_org} And gm _{_var} ) The gm value of the corresponding device in the second circuit may be considered to have satisfied the first constraint.

Other raw device feature values for gds, fn, tn, id and Vt, etc., and corresponding random mismatch values can be obtained by a method similar to gm. Thus, the first constraint includes a raw device characteristic value gm, gds, fn, tn, id and Vt for each device of the plurality of devices, and a random mismatch value for each raw device characteristic value.

404. The tuning means determines the device size of the second circuit satisfying the first constraint according to the second device lookup table. Step 406 is then performed.

And when the tuning device obtains the first constraint condition of the determined second circuit, starting the tuning process.

In some embodiments, the tuning apparatus may determine a device size of the second circuit satisfying the first constraint and Kirchhoff law, the device size including a channel length and a channel width of the device, from the second device lookup table.

The Kirchhoff Law comprises a Kirchhoff first Law and a Kirchhoff second Law, wherein the Kirchhoff first Law is a Kirchhoff Current Law (Kirchhoff's Current Law), and is abbreviated as KCL; the Kirchhoff second Law is called Kirchhoff's Voltage Law, KVL for short.

Illustratively, the second device lookup table includes device characteristic values of each type of device under the target process under the multidimensional voltage, the channel length and the channel width of the device, wherein the device characteristic values include device characteristic values and random mismatch information of the device obtained by simulating the device under the target process. When the tuning device determines the first constraint condition through step 403, the tuning device uses the first constraint condition as a tuning target, considers that each original device characteristic value in the first constraint condition corresponds to a random mismatch value, and for one device in the second circuit related to the first constraint condition, can search a plurality of groups of device characteristic values meeting the first constraint condition in the second device lookup table, and calculates random mismatch values corresponding to the plurality of groups of device characteristic values respectively. It should be understood that there are multiple sets of device feature values, and the mismatch range caused by the random mismatch value existing in the original device feature value in the first constraint condition, that is, the device feature value found in the second device lookup table and the calculated random mismatch value satisfy the original device feature value and the mismatch range in the first constraint condition are acceptable. Then, at least one set of device characteristic values meeting the KCL equation can be determined from the plurality of sets of device characteristic values and the corresponding random mismatch values, the device size corresponding to the at least one set of device characteristic values in the second device lookup table is selected, and one set of device sizes corresponding to the device characteristic values meeting the KCL equation is selected, so that the size of the device is determined.

The implementation mode of combining the second device lookup table to determine the device size does not need to use a simulation tool, and the tuning time can be effectively shortened.

405. And the tuning device carries out direct current simulation on the second circuit, and determines the device size of the second circuit meeting the first constraint condition according to the simulation result and the second device lookup table.

In some embodiments, when the tuning device obtains the first constraint condition, the direct current simulation and the noise simulation may be performed on the second circuit, and the device size of the second circuit is adjusted according to the simulation result and the second device lookup table, so that the adjusted simulation result of the second circuit satisfies the first constraint condition and kirchhoff law equation.

Exemplary, toneThe optimizing device can perform DC simulation on part of devices in the second circuit (the devices which are not required to be simulated are not involved in the simulation) to obtain bias voltage V of part of devices in the second circuit _gs 、V _ds And V _sb To further derive a portion of the original device characteristic values (e.g., transconductance gm, output transconductance gds, dc current Id, threshold voltage Vt, etc.) for each device in the second circuit based on the bias voltage. And performing noise simulation on part of devices in the second circuit to obtain another part of original device characteristic values (including flicker noise fn and thermal noise tn, for example) of part of devices in the second circuit.

When the original device characteristic value and the random mismatch value of the original device characteristic value in the first constraint condition are used as the optimization target for the second circuit at this time, the random mismatch value of the original device characteristic value obtained by performing DC simulation and noise simulation on part of devices in the second circuit can be obtained based on the second random mismatch information in the second device lookup table (similar to the process of calculating the random mismatch value of the original device characteristic value of the first circuit in step 403).

Determining whether the random mismatch values of the original device characteristic values of the partial devices in the second circuit and the original device characteristic values of the partial devices in the second circuit satisfy the first constraint condition and kirchhoff's law equation. In determining whether the first constraint is satisfied, it is understood that determining whether the random mismatch value of the original device characteristic value of the partial device in the second circuit and the original device characteristic value of the partial device in the second circuit is within the range of the original device characteristic value and the corresponding random mismatch value in the first constraint.

If the random mismatch value of the original device characteristic value of the part of devices in the second circuit and the original device characteristic value of the part of devices in the second circuit meets the first constraint condition, the regulator determines that the iterative processing of the device size in the second circuit is not continued at the moment.

If the random mismatch value of the original device characteristic value of the partial device in the second circuit and the original device characteristic value of the partial device in the second circuit does not meet the first constraint condition and kirchhoff law equation, the regulator can regulate the device size of the partial device in the second circuit, continuously perform DC simulation on the second circuit with the regulated device size, obtain the original device characteristic value of the partial device in the second circuit with the regulated device size according to the simulation result, and obtain the random mismatch value of the original device characteristic value of the partial device in the second circuit with the regulated device size based on the second device lookup table.

And determining whether the random mismatch value of the original device characteristic value of the partial device in the second circuit and the original device characteristic value of the partial device in the second circuit after the device size is adjusted meets a first constraint condition and a kirchhoff law equation. If the first constraint condition is met, determining the device size of part of devices in the second circuit, and if the first constraint condition is not met, continuing to adjust the device size until the original device characteristic value and the random mismatch value of the second circuit after adjustment meet the first constraint condition.

The accuracy of the device size of the second circuit determined by DC simulation and noise simulation in step 405 is higher than the accuracy of the device size determined directly from the second device lookup table in step 404.

406. The tuning device simulates the second circuit according to the second simulation example, and determines whether the specification of the second circuit meets the requirement.

After the second circuit is determined by step 404 or 405, it corresponds to a circuit that obtains the key small signal features at the device level. At this time, further simulation is performed through a second simulation case under the target process, and whether the specification of the second circuit meets the requirement is checked.

In some embodiments, whether the specification of the second circuit meets the requirement may be understood as whether the device in the second circuit meets the specification after the full simulation by the second simulation case. And if the devices in the second circuit meet the specification, determining that the second circuit is the finally realized transplanted circuit. If the specification indicated by the simulation result of at least one device in the second circuit does not meet the requirement, the process of matching the features of the key device needs to be entered again, that is, step 407 is performed.

In some embodiments, the process of performing the full simulation in step 406 using the second simulation case may be understood as performing DC simulation, transient simulation, ac simulation, periodic steady state (periodic stead state, PSS) simulation, monte carlo method simulation, etc. on the second circuit to obtain the performance or specification of the second circuit overall circuit. Taking a circuit with a second circuit as an operational amplifier as an example, device characteristic values such as transconductance, gate-source capacitance, output current noise and the like of MOS devices in the circuit can be obtained through DC simulation; performing Fourier analysis on the simulation result through transient simulation to obtain the signal-to-noise ratio of the MOS device; obtaining the linearity of the device through PSS simulation; and obtaining the random mismatch value of the input equivalent voltage of the device, the average value of the performance or specification of the device under different processes and the random mismatch value through simulation of a Monte Carlo method.

407. In the case where the specification of the second circuit does not meet the requirement, the tuning means determines a second constraint in which the device characteristic value is proportional to the device characteristic value in the first constraint.

If the performance or specification of at least one device in the second circuit does not meet the requirements, the process of matching the characteristic values of the key devices can be carried out again, new constraint conditions are determined, and an iteration is carried out again. Thus, the achievement of the second circuit specification is finally realized by continuously and repeatedly optimizing the device characteristic value.

In some embodiments, the device characteristic values in the second constraint may be determined according to a proportional relationship to the device characteristic values in the first constraint.

For example, the original device feature gm in the first constraint is noted as gm _{_org} The original device feature gm in the second constraint is noted as gm _{_target} Gm at the time of _{_target} And gm _{_org} The proportional relationship of (2) may be as shown in formula (6).

β _{0_low·} gm _{_org} ≤gm _{_target} ≤β _{0_high·} gm _{_org} Equation (6).

Wherein beta is _{0_low} And beta _{0_high} For determining original device features in a second constraint for a predetermined range coefficientValue gm _{_target} Is not limited in terms of the range of (a).

In some embodiments, β _{0_low} And beta _{0_high} The value of (2) may be obtained by looking up a first device look-up table. I.e., the first device lookup table may include therein the channel length L, width W, device characteristic values, mismatch coefficients, and beta for each type of device _{0_low} Beta _{0_high} The beta corresponding to the device can be obtained through searching the channel length L and the width W of the device _{0_low} And beta _{0_high} 。

Similarly, where the first constraint further includes a random mismatch value for the original device characteristic value, the random mismatch value for the original device characteristic value in the second constraint may also be determined. The random mismatch value of the raw device characteristic value gm in the first constraint is noted as gm _{_var} The random mismatch value of the original device characteristic value gm in the second constraint is recorded as gm _{_var_target} Gm at the time of _{_var_target} And gm _{_var} The proportional relationship of (2) may be as shown in formula (7).

β _{1_low·} gm _{_var} ≤gm _{_var_target} ≤β _{1_high·} gm _{_var} Equation (7).

Wherein beta is _{1_low} And beta _{1_high} For determining the original device characteristic value gm in the second constraint condition by using preset lower limit coefficient and upper limit coefficient _{_target} Random mismatch value gm of (2) _{_var_target} Is not limited in terms of the range of (a).

In some embodiments, β _{1_low} And beta _{1_high} The value of (2) may also be obtained by looking up the first device look-up table. I.e., the first device lookup table may include therein the channel length L, width W, device characteristic values, mismatch coefficients, and beta for each type of device _{0_low} Beta _{0_high} In addition to, beta may also be included _{1_low} And beta _{1_high} The corresponding beta of the device can be obtained through searching the channel length L and the width W of the device _{1_low} And beta _{1_high} Is a value of (2).

And determining the original device characteristic value gm in the second constraint condition _{_target} And random mismatch value gm _{_var_target} Other raw device feature values (e.g., gds, fn, tn, id and Vt) and corresponding random mismatch values in the second constraint may also be determined.

408. The tuning means determines the device size of the second circuit satisfying the second constraint according to the second device lookup table.

Similar to the embodiment of step 404, the tuning apparatus may determine a device size of the second circuit that satisfies the second constraint and kirchhoff's law equation from the second device lookup table, the device size including a channel length and a channel width of the device. For a specific implementation, see the description of step 404.

Similar to the embodiment of step 405, the tuning device may perform a dc simulation on the second circuit, and determine, according to the simulation result and the second device lookup report, a device size of the second circuit that satisfies the second constraint condition, so that the second circuit satisfies the constraint condition and kirchhoff's law equation. For a specific implementation, see the description of step 405.

409. The tuning device simulates the second circuit according to the second simulation example, and determines whether the specification of the second circuit meets the requirement.

The implementation of step 409 can be seen in the description of step 406.

In this way, the achievement of the second circuit specification is finally achieved by continuously and repeatedly optimizing the small signal characteristic, namely, the original device characteristic value and the random mismatch value corresponding to the original device characteristic value in the optimization constraint condition.

Therefore, the application can solve the problems of complex transplanting flow and long iteration time of the analog integrated circuit under different processes. The process can enable a designer to automatically adjust the size of the device by using software by identifying the key device characteristic value of the device in the circuit to be transplanted as a constraint condition for circuit tuning, thereby achieving the matching of key parameters among processes to reduce the design and verification workload of the circuit migration to different processes.

It will be appreciated that the tuning device, in order to implement the above-mentioned functions, includes corresponding hardware structures and/or software modules for performing the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Those skilled in the art may implement the described functionality using different approaches for each particular application, but such implementation is not to be considered as beyond the scope of the embodiments of the present application.

The embodiment of the application can divide the functional modules of the tuning device according to the method example, for example, each functional module can be divided corresponding to each function, and two or more functions can be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.

In the case of dividing the respective functional modules by the respective functions, fig. 7 shows a schematic diagram of one possible composition of the tuning device 70 involved in the above-described embodiment, and as shown in fig. 7, the tuning device 70 may include: an extraction unit 701, a determination unit 702, and a simulation unit 703.

Wherein the extraction unit 701 may be used to support the tuning device 70 to perform the above-described steps 301 and 401, etc., and/or other processes for the techniques described herein.

The determination unit 702 may be used to support the tuning device 70 to perform the above-described steps 303, 304, 402, 403, 404, 406, 407, 408, etc., and/or other processes for the techniques described herein.

The simulation unit 703 may be used to support the best device 70 to perform the steps 305, 405, 409, etc. described above, and/or other processes for the techniques described herein.

It should be noted that, all relevant contents of each step related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein.

The tuning device 70 provided in this embodiment is used for executing the circuit transplanting method, so that the same effects as those of the implementation method can be achieved.

In the case of using an integrated unit, as shown in fig. 8, an embodiment of the present application discloses a tuning device 80, where the tuning device 80 may be a chip in the above embodiment. The tuning device 80 may include a processing module 801 and a storage module 802.

The processing module 801 may be configured to control and manage the actions of the tuning device 80, for example, may be configured to support the tuning device 80 to perform the functions of the extracting unit 701, the determining unit 702, and the simulating unit 703. The memory module 802 may be used to support the tuning device 80 to store program code, data, and the like. For example, the data stored by the memory module 802 includes a first device lookup table and a second device lookup table, and a first constraint and a second constraint, etc. in the present application. The processing module 801 may be used to load the program code stored by the storage module 802 to perform the functions of the extraction unit 701, the determination unit 702, and the simulation unit 703.

Of course, the unit modules in the tuning device 80 include, but are not limited to, the processing module 801 and the storage module 802. For example, the tuning device 80 may further include a power module. The power module is used to power the tuning device 80.

Wherein the processing module 801 may be a processor or controller. Which may implement or perform the various exemplary logic blocks, modules and circuits described in connection with this disclosure. A processor may also be a combination that performs computing functions, e.g., including one or more microprocessors, digital signal processing (digital signal processing, DSP) and microprocessor combinations, and the like. The memory module 802 may be a memory.

The tuning device 80 provided in the embodiment of the present application may be a chip 90 shown in fig. 9. Wherein the processor and the memory etc. may be connected together, for example by a bus.

The embodiment of the application also provides a tuning device which comprises one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, the one or more memories being operable to store computer program code comprising computer instructions that, when executed by the one or more processors, cause the communications apparatus to perform the related method steps described above to implement the method of circuit migration in the above-described embodiments.

The embodiment of the present application also provides a computer readable storage medium, in which a computer program code is stored, and when the processor executes the computer program code, the tuning device executes the circuit transplanting method in the above embodiment.

The embodiment of the application also provides a computer program product, which when run on a computer, causes the computer to execute the above related steps to implement the method for circuit transplanting executed by the tuning device in the above embodiment.

The tuning device, the computer storage medium, the computer program product or the chip provided in this embodiment are all configured to execute the corresponding method provided above, so that the beneficial effects achieved by the tuning device, the computer storage medium, the computer program product or the chip can refer to the beneficial effects in the corresponding method provided above, and are not described herein again.

It will be appreciated by those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another apparatus, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and the parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a device (may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A method of circuit migration, the method comprising:

extracting a first device lookup table under a source process and a second device lookup table under a target process, wherein the first device lookup table comprises device characteristic values of multiple types of devices under the source process, and the second device lookup table comprises device characteristic values of multiple types of devices under the target process;

determining a second circuit with a preset corresponding relation with the first circuit under the source process under the target process, and determining a second simulation case corresponding to the first simulation case under the source process under the target process;

obtaining a device characteristic value of the first circuit according to a simulation result of direct current simulation on the first circuit and the first device lookup table, and taking the device characteristic value of the first circuit as a first constraint condition for selecting a device of the second circuit;

determining a device size of the second circuit that satisfies the first constraint according to the second device lookup table;

and carrying out comprehensive simulation on the second circuit of the device size meeting the first constraint condition according to the second simulation use case.
The method according to claim 1, wherein the method further comprises:

Under the condition that the second circuit is comprehensively simulated and the specification of the second circuit does not meet the requirement, determining a second constraint condition, wherein the device characteristic value in the second constraint condition is proportional to the device characteristic value in the first constraint condition;

determining the device size of the second circuit meeting the second constraint condition according to the second device lookup table, or performing direct current simulation on the second circuit to determine the device size of the second circuit meeting the second constraint condition;

and carrying out comprehensive simulation on the second circuit according to the second simulation example, and determining whether the specification of the second circuit meets the requirement.
The method of claim 1 or 2, wherein extracting the first device lookup table under the source process and the second device lookup table under the target process comprises:

scanning the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the source process to obtain the device characteristic values of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the source process;

and scanning the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the target process to obtain the device characteristic values of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the target process.
A method according to any one of claim 1 to 3, wherein,

the first constraint condition comprises a device characteristic value of a part of key devices in the second circuit configured by a user;

the device characteristics of the part of key devices comprise transconductance, output transconductance, flicker noise, thermal noise, direct current and threshold voltage of the devices, and the device characteristic values of the part of key devices are the same as the device characteristic values of the first circuit.
The method of claim 4, wherein the step of determining the position of the first electrode is performed,

the first constraint condition further comprises key information of part of devices in the second circuit, which is identified by a tuning tool;

the key information comprises turn-off information of part of devices in the second circuit, a dimensional proportion relation of part of devices and an input pair transistor symmetrical relation of part of devices.
The method according to any one of claims 1 to 5, wherein,

the device characteristic values in the first device lookup table further comprise first random mismatch information corresponding to the device characteristic values of the devices of the part under the source process, wherein the first random mismatch information is used for indicating mismatch characteristics of the device characteristic values obtained by simulating the devices under the source process;

The device characteristic values in the second device lookup table further comprise second random mismatch information corresponding to the device characteristic values of the part of devices under the target process, and the second random mismatch information is used for indicating mismatch characteristics of the device characteristic values obtained by simulating the devices under the target process.
The method of claim 6, wherein obtaining the device characteristic value of the first circuit based on the simulation result of the dc simulation of the first circuit and the first device lookup table comprises:

performing direct current simulation on the first circuit to obtain an original device characteristic value of part of devices of the first circuit;

determining a random mismatch value of an original device characteristic value of a part of devices of the first circuit according to the random mismatch information in the first device lookup table;

the device characteristic value of the first circuit comprises an original device characteristic value of a part of devices of the first circuit and a random mismatch value of the original device characteristic value of the part of devices of the first circuit.
The method of claim 7, wherein determining the device size of the second circuit that satisfies the first constraint based on the second device lookup table comprises:

And searching a device characteristic value and a random mismatch value which meet the original device characteristic value in the first constraint condition in the second device lookup table, and determining the device size of the device which meets the kirchhoff law equation as the device size of the second circuit in the device characteristic value and the random mismatch value which meet the original device characteristic value in the first constraint condition.
The method of claim 7, wherein determining the device size of the second circuit that satisfies the first constraint based on the second device lookup table comprises:

performing direct current simulation on the second circuit, obtaining an original device characteristic value of a part of devices in the second circuit according to a simulation result, and obtaining a random mismatch value of the original device characteristic value of the part of devices in the second circuit based on second random mismatch information in the second device lookup table;

when the random mismatch value of the original device characteristic value of part of devices in the second circuit and the original device characteristic value of part of devices in the second circuit does not meet the first constraint condition and the kirchhoff law equation, adjusting the device size of the second circuit;

Performing direct current simulation on the second circuit with the device size adjusted, obtaining the original device characteristic values of part of devices in the second circuit with the device size adjusted according to a simulation result, and obtaining random mismatch values of the original device characteristic values of part of devices in the second circuit with the device size adjusted based on the second device lookup table;

and determining whether random mismatch values of original device characteristic values of partial devices in the second circuit and original device characteristic values of partial devices in the second circuit after device size adjustment meet the first constraint condition and the kirchhoff law equation.
The method of any of claims 1-9, wherein device characteristic values of the same type of device are different under the source process and the target process.
A tuning device comprising a processor coupled to a memory; the memory is used for storing a computer program or instructions; the processor is configured to execute a computer program or instructions stored in the memory, so that the tuning device performs the following procedure:

extracting a first device lookup table under a source process and a second device lookup table under a target process, wherein the first device lookup table comprises device characteristic values of multiple types of devices under the source process, and the second device lookup table comprises device characteristic values of multiple types of devices under the target process;

Determining a second circuit with a preset corresponding relation with the first circuit under the source process under the target process, and determining a second simulation case corresponding to the first simulation case under the source process under the target process;

obtaining a device characteristic value of the first circuit according to a simulation result of direct current simulation on the first circuit and the first device lookup table, and taking the device characteristic value of the first circuit as a first constraint condition for selecting a device of the second circuit; determining a device size of the second circuit that satisfies the first constraint according to the second device lookup table;

and carrying out comprehensive simulation on the second circuit of the device size meeting the first constraint condition according to the second simulation use case.
The tuning device of claim 11, wherein the processor, when configured to execute the computer program or instructions stored in the memory, performs the process further comprising:

under the condition that the second circuit is comprehensively simulated and the specification of the second circuit does not meet the requirement, determining a second constraint condition, wherein the device characteristic value in the second constraint condition is proportional to the device characteristic value in the first constraint condition;

Determining the device size of the second circuit meeting the second constraint condition according to the second device lookup table, or performing direct current simulation on the second circuit to determine the device size of the second circuit meeting the second constraint condition;

and carrying out comprehensive simulation on the second circuit according to the second simulation example, and determining whether the specification of the second circuit meets the requirement.
Tuning apparatus according to claim 11 or 12, wherein the processor, when executing the computer program or instructions stored in the memory, comprises extracting a first device lookup table under a source process and a second device lookup table under a target process, comprises:

scanning the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the source process to obtain the device characteristic values of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the source process;

and scanning the multidimensional voltage, the channel length and the width of each type of device in the multiple types of devices under the target process to obtain the device characteristic values of each type of device under the multidimensional voltage, the channel length and the channel width of the device under the target process.
The tuning apparatus of any one of claims 11-13, wherein the first constraint comprises a user-configured device characteristic value of a portion of critical devices in the second circuit;

the device characteristics of the part of key devices comprise transconductance, output transconductance, flicker noise, thermal noise, direct current and threshold voltage of the devices, and the device characteristic values of the part of key devices are the same as the device characteristic values of the first circuit.
The tuning apparatus of claim 14, wherein the first constraint further comprises key information of a portion of the devices in the second circuit identified by a tuning tool;

the key information comprises turn-off information of part of devices in the second circuit, a dimensional proportion relation of part of devices and an input pair transistor symmetrical relation of part of devices.
The tuning device according to any one of claims 11-15, wherein,

the device characteristic values in the first device lookup table further comprise first random mismatch information corresponding to the device characteristic values of the devices of the part under the source process, wherein the first random mismatch information is used for indicating mismatch characteristics of the device characteristic values obtained by simulating the devices under the source process;

The device characteristic values in the second device lookup table further comprise second random mismatch information corresponding to the device characteristic values of the part of devices under the target process, and the second random mismatch information is used for indicating mismatch characteristics of the device characteristic values obtained by simulating the devices under the target process.
The tuning apparatus of claim 16, wherein the processor, when executing the computer program or the instructions stored in the memory, comprises obtaining the device characteristic value of the first circuit according to the simulation result of the dc simulation performed on the first circuit and the first device lookup table, specifically includes:

performing direct current simulation on the first circuit to obtain an original device characteristic value of part of devices of the first circuit;

determining a random mismatch value of an original device characteristic value of a part of devices of the first circuit according to the random mismatch information in the first device lookup table;

the device characteristic value of the first circuit comprises an original device characteristic value of a part of devices of the first circuit and a random mismatch value of the original device characteristic value of the part of devices of the first circuit.
The tuning apparatus of claim 17, wherein the processor, when executing the computer program or instructions stored in the memory, comprises determining a device size of the second circuit that satisfies the first constraint based on the second device lookup table, comprises:

And searching a device characteristic value and a random mismatch value which meet the original device characteristic value in the first constraint condition in the second device lookup table, and determining the device size of the device which meets the kirchhoff law equation as the device size of the second circuit in the device characteristic value and the random mismatch value which meet the original device characteristic value in the first constraint condition.
The tuning apparatus of claim 17, wherein the processor, when executing the computer program or instructions stored in the memory, comprises determining a device size of the second circuit that satisfies the first constraint based on the second device lookup table, comprises:

performing direct current simulation on the second circuit, obtaining an original device characteristic value of a part of devices in the second circuit according to a simulation result, and obtaining a random mismatch value of the original device characteristic value of the part of devices in the second circuit based on second random mismatch information in the second device lookup table;

when the random mismatch value of the original device characteristic value of part of devices in the second circuit and the original device characteristic value of part of devices in the second circuit does not meet the first constraint condition and the kirchhoff law equation, adjusting the device size of the second circuit;

Performing direct current simulation on the second circuit with the device size adjusted, obtaining the original device characteristic values of part of devices in the second circuit with the device size adjusted according to a simulation result, and obtaining random mismatch values of the original device characteristic values of part of devices in the second circuit with the device size adjusted based on the second device lookup table;

and determining whether random mismatch values of original device characteristic values of partial devices in the second circuit and original device characteristic values of partial devices in the second circuit after device size adjustment meet the first constraint condition and the kirchhoff law equation.
Tuning apparatus in accordance with any one of claims 11-19, wherein the device characteristic values of the same type of device are different in the source process and the target process.
A computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any of the preceding claims 1-10.