CN115345097A - Method for improving temperature immunity of digital circuit and electronic equipment - Google Patents
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Abstract
The invention discloses a method for improving the temperature immunity of a digital circuit and electronic equipment, wherein the method comprises the following steps: selecting a standard unit to perform transient simulation; tracking a current track and a voltage track of the device and selecting a voltage sampling point; calculating the effective driving current and the temperature dependence of the device; determining a zero-temperature delay working point; establishing a zero-temperature delay working point database of a standard unit library, and determining zero-temperature delay working points from a device level to the standard unit level; taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to finish the logic synthesis process; generating a gate-level netlist of the circuit according to a time sequence analysis result of the logic synthesis; and carrying out physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay working point facing the large-scale digital circuit. The invention can relieve the heat effect in the digital circuit and reduce the temperature dependence of the electrical characteristics, and can be widely applied to the technical field of integrated circuits.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method for improving the temperature immunity of a digital circuit and electronic equipment.
Background
In recent years, with the progress of manufacturing processes, the miniaturization process of integrated circuits is further advanced, the size of a transistor in the circuit is continuously reduced, the transistor structure is also changed from a traditional planar device into a three-dimensional device, even a wrap gate structure device, the integration density is greatly improved, and meanwhile, the heat effect in a chip is more obvious. In addition, temperature changes caused by external environments and operating conditions are also one of the important factors causing fluctuations in device and circuit characteristics. From a device perspective, thermal effects reduce carrier mobility, resulting in degradation of device performance. From the circuit perspective, the driving capability of the circuit is degraded due to the rise of the temperature on the chip caused by the heat effect, the time delay is increased, and the leakage current is increased sharply. Therefore, the performance stability and system reliability of the whole circuit are seriously threatened by the working temperature of the chip and the change of the external temperature born by the chip.
The thermal effect is one of the key factors which cause circuit aging and further restrict the performance of the integrated circuit, and the optimization design method taking the thermal effect as a breakthrough is expected to enhance the performance and the reliability of the circuit. Therefore, how to take advantage of the advantages of the process progress as much as possible while meeting the performance and reliability requirements expected by the circuit design is a critical issue that needs to be solved.
In the technology of relieving or avoiding negative effects caused by thermal effects in chip design, the following problems exist:
a timing protection band related to heat is introduced in the design stage, namely, a delay margin resisting the temperature influence is added on the basis of the delay of a circuit critical path to overcome the influence of a thermal effect. However, this design strategy does not fundamentally eliminate the negative effects of heat effects, and inevitably reduces circuit frequency, resulting in some performance penalties.
The technical scheme is that a compensation measure aiming at temperature change introduces larger design overhead, including increasing chip area and power consumption.
The optimized design of heat dissipation is carried out at the chip packaging level, the heat dissipation environment of the circuit is improved, and therefore the temperature rise of the chip is reduced, but the temperature dependence of circuit characteristics such as time delay cannot be changed or reduced essentially by the scheme, so that the sensitivity of a circuit system to the temperature still exists, and the performance difference of the circuit system at different temperatures is caused.
The core of the existing temperature fluctuation resisting technology for improving the circuit based on the zero temperature coefficient point, which is provided for an analog circuit, is to enable the bias of the circuit to be at a fixed static working point, namely, the drain current under a certain grid voltage does not change along with the temperature, but the technology is not suitable for a digital circuit, because the grid voltage cannot be kept constant under the switching operation of the digital circuit, and the digital circuit mainly concerns time delay information. Therefore, the zero temperature coefficient point technique currently applied to analog circuits cannot be used to enhance the temperature immunity characteristics of digital circuits.
Disclosure of Invention
Embodiments of the present invention provide a method and an electronic device for improving temperature immunity of a digital circuit, so as to alleviate thermal effects in the digital circuit and reduce temperature dependence of electrical characteristics.
One aspect of the embodiments of the present invention provides a method for improving temperature immunity of a digital circuit, including:
determining zero-temperature delay working points from a device level to a standard unit level; determining an optimal zero-temperature delay working point for the large-scale digital circuit;
the determination of the zero-temperature delay operating point from the device level to the standard unit level comprises the following steps:
selecting a standard unit to perform transient simulation;
tracking a current track and a voltage track of the device and selecting a voltage sampling point;
calculating the effective driving current of the device and the temperature dependence of the device;
determining a zero-temperature delay working point of each standard unit;
establishing a zero-temperature delay working point database of a standard unit library, and determining zero-temperature delay working points from a device level to the standard unit level;
the determination of the optimal zero-temperature delay working point for the large-scale digital circuit comprises the following steps:
taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to finish the logic synthesis process;
generating a gate-level netlist of the circuit according to the time sequence analysis result of the logic synthesis;
and carrying out physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay working point facing the large-scale digital circuit.
Optionally, the selecting a standard cell for transient simulation includes:
acquiring transient voltage and current curves of the standard unit;
acquiring a first time interval between the time when the rising edge of the output voltage reaches 50% of the power supply voltage and the time when the falling edge of the input voltage reaches 50% of the power supply voltage;
acquiring a second time interval between the time when the falling edge of the output voltage reaches 50% of the working voltage and the time when the rising edge of the input voltage reaches 50% of the working voltage;
and calculating the propagation delay according to the first time interval and the second time interval.
Optionally, tracking the current trajectory and the voltage trajectory of the device, and selecting a voltage sampling point includes:
determining a leading device influencing the standard unit time delay from the current transient response;
acquiring a working voltage track of the leading device;
and selecting a proper sampling point on the voltage track according to the working voltage track of the master device.
Optionally, calculating the effective drive current of the device and the temperature dependence of the device comprises:
after a voltage sampling point is obtained, performing integral averaging on the current of the device working under the voltage combination of VGS and VDS to obtain effective driving current;
performing mixed-mode simulation of TCAD devices at different temperatures or simulation of SPICE circuits at different temperatures on the devices to obtain effective currents and effective current curves of the devices at different temperatures, and calculating effective currents corresponding to propagation delay at different temperatures;
and finding out a point, which does not change with the temperature, of the effective current curve as a zero-temperature delay working point of the standard cell.
Optionally, the determining the zero-temperature delay operating point of each standard cell includes:
and transforming different circuit load and signal conversion rate combinations, counting zero-temperature delay working points determined by the delay of each standard unit, and establishing a zero-temperature delay working point database which can be searched through the types and working conditions of the standard units.
Optionally, the process of performing logic synthesis by using the statistical average of the zero temperature coefficient points of the standard cell library as an initial power supply voltage includes:
preparing a behavior description file describing expected logic functions of the circuit;
and performing logic synthesis on the netlist by adopting a logic synthesis tool according to the behavior description file and the timing constraint file to generate a gate-level netlist meeting the requirements of the timing constraint file.
Optionally, the performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay operating point for a large-scale digital circuit includes:
performing layout planning by adopting a layout planning tool to divide a gate-level netlist;
electrically connecting the divided netlists according to the positions and the relations of circuit units or modules by using an automatic layout and wiring tool, performing two steps of design rule verification and layout and schematic diagram comparison on the generated layout, entering a parasitic parameter extraction process, acquiring parasitic parameters of the layout, and performing time sequence simulation;
wherein, the time sequence simulation tool is a PrimeTime time sequence analysis tool.
The embodiment of the invention also provides a device for improving the temperature immunity of the digital circuit, which comprises a first module and a second module;
the first module is used for determining a zero-temperature delay working point from a device level to a standard unit level;
the second module is used for determining the optimal zero-temperature delay working point facing the large-scale digital circuit;
wherein the first module is specifically configured to:
selecting a standard unit to perform transient simulation;
tracking a current track and a voltage track of the device and selecting a voltage sampling point;
calculating the effective driving current of the device and the temperature dependence of the device;
determining a zero-temperature delay working point of each standard unit;
establishing a zero-temperature delay working point database of a standard unit library, and determining zero-temperature delay working points from a device level to the standard unit level;
the second module is specifically configured to:
taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to finish the logic synthesis process;
generating a gate-level netlist of the circuit according to the time sequence analysis result of the logic synthesis;
and carrying out physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay working point facing the large-scale digital circuit.
Another aspect of the embodiments of the present invention further provides an electronic device, which includes a processor and a memory;
the memory is used for storing programs;
the processor executes the program to implement the method as described above.
Yet another aspect of the embodiments of the present invention provides a computer-readable storage medium, which stores a program, which is executed by a processor to implement the method as described above.
The embodiment of the invention also discloses a computer program product or a computer program, which comprises computer instructions, and the computer instructions are stored in a computer readable storage medium. The computer instructions may be read by a processor of a computer device from a computer-readable storage medium, and the computer instructions executed by the processor cause the computer device to perform the foregoing method.
The method of the embodiment of the invention comprises the following steps: determining zero-temperature delay working points from a device level to a standard unit level; determining an optimal zero-temperature delay working point for the large-scale digital circuit; the determination of the zero-temperature delay operating point from the device level to the standard unit level comprises the following steps: selecting a standard unit to perform transient simulation; tracking a current track and a voltage track of the device and selecting a voltage sampling point; calculating the effective driving current of the device and the temperature dependence of the device; determining a zero-temperature delay working point of each standard unit; establishing a zero-temperature delay working point database of a standard unit library, and determining zero-temperature delay working points from a device level to the standard unit level; the determination of the optimal zero-temperature delay working point for the large-scale digital circuit comprises the following steps: taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to finish the logic synthesis process; generating a gate-level netlist of the circuit according to the time sequence analysis result of the logic synthesis; and carrying out physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay working point facing the large-scale digital circuit. The invention can alleviate the thermal effect in the digital circuit and reduce the temperature dependence of the electrical characteristics.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flow chart illustrating a determination process of zero-temperature delay operating points of each unit in a standard cell library according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating transient response simulation results of a standard cell;
FIG. 3 is a diagram illustrating the relationship between the effective current and the power supply voltage of the device at different temperatures;
fig. 4 is a schematic diagram of the circuit operating frequency affected by temperature.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In view of the problems in the prior art, an aspect of the embodiments of the present invention provides a method for improving temperature immunity of a digital circuit, including:
determining zero-temperature delay working points from a device level to a standard unit level; determining an optimal zero-temperature delay working point for the large-scale digital circuit;
the determination of the zero-temperature delay operating point from the device level to the standard unit level comprises the following steps:
selecting a standard unit to perform transient simulation;
tracking a current track and a voltage track of the device and selecting a voltage sampling point;
calculating the effective driving current of the device and the temperature dependence of the device;
determining zero-temperature delay working points of the standard units;
establishing a zero-temperature delay working point database of a standard unit library, and determining zero-temperature delay working points from a device level to the standard unit level;
the determination of the optimal zero-temperature delay working point for the large-scale digital circuit comprises the following steps:
taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to finish the logic synthesis process;
generating a gate-level netlist of the circuit according to the time sequence analysis result of the logic synthesis;
and carrying out physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay working point facing the large-scale digital circuit.
Optionally, the selecting a standard cell for transient simulation includes:
acquiring transient voltage and current curves of the standard unit;
acquiring a first time interval between the time when the rising edge of the output voltage reaches 50% of the power supply voltage and the time when the falling edge of the input voltage reaches 50% of the power supply voltage;
acquiring a second time interval between the time when the falling edge of the output voltage reaches 50% of the working voltage and the time when the rising edge of the input voltage reaches 50% of the working voltage;
and calculating the propagation delay according to the first time interval and the second time interval.
Optionally, tracking the current trajectory and the voltage trajectory of the device, and selecting a voltage sampling point includes:
determining a leading device influencing the standard cell delay from the current transient response;
acquiring a working voltage track of the leading device;
and selecting a proper sampling point on the voltage track according to the working voltage track of the master device.
Optionally, calculating the effective drive current of the device and the temperature dependence of the device comprises:
after a voltage sampling point is obtained, performing integral averaging on the current of the device working under the voltage combination of VGS and VDS to obtain effective driving current;
performing mixed-mode simulation of TCAD devices at different temperatures or simulation of SPICE circuits at different temperatures on the devices to obtain effective currents and effective current curves of the devices at different temperatures, and calculating effective currents corresponding to propagation delay at different temperatures;
and finding out a point, which does not change with the temperature, of the effective current curve as a zero-temperature delay working point of the standard cell.
Optionally, the determining the zero-temperature delay operating point of each standard cell includes:
and transforming different circuit load and signal conversion rate combinations, counting zero-temperature delay working points determined by the delay of each standard unit, and establishing a zero-temperature delay working point database which can be searched through the types and working conditions of the standard units.
Optionally, the process of performing logic synthesis by using the statistical average of the zero temperature coefficient points of the standard cell library as an initial power supply voltage includes:
preparing a behavior description file describing expected logic functions of the circuit;
and performing logic synthesis on the netlist by adopting a logic synthesis tool according to the behavior description file and the timing constraint file to generate a gate-level netlist meeting the requirements of the timing constraint file.
Optionally, the performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay operating point for the large-scale digital circuit includes:
performing layout planning by adopting a layout planning tool to divide a gate-level netlist;
electrically connecting the divided netlists according to the positions and the relations of circuit units or modules by using an automatic layout and wiring tool, performing two steps of design rule verification and layout and schematic diagram comparison on the generated layout, entering a parasitic parameter extraction process, acquiring parasitic parameters of the layout, and performing time sequence simulation;
wherein, the time sequence simulation tool is a PrimeTime time sequence analysis tool.
The embodiment of the invention also provides a device for improving the temperature immunity of the digital circuit, which comprises a first module and a second module;
the first module is used for determining a zero-temperature delay working point from a device level to a standard unit level;
the second module is used for determining the optimal zero-temperature delay working point facing the large-scale digital circuit;
wherein the first module is specifically configured to:
selecting a standard unit to perform transient simulation;
tracking a current track and a voltage track of the device and selecting a voltage sampling point;
calculating the effective driving current of the device and the temperature dependence of the device;
determining zero-temperature delay working points of the standard units;
establishing a zero-temperature delay working point database of a standard unit library, and determining zero-temperature delay working points from a device level to the standard unit level;
the second module is specifically configured to:
taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to finish the logic synthesis process;
generating a gate-level netlist of the circuit according to the time sequence analysis result of the logic synthesis;
and carrying out physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay working point facing the large-scale digital circuit.
Another aspect of the embodiments of the present invention further provides an electronic device, including a processor and a memory;
the memory is used for storing programs;
the processor executes the program to implement the method as described above.
Another aspect of the embodiments of the present invention also provides a computer-readable storage medium, which stores a program, and the program is executed by a processor to implement the method as described above.
The embodiment of the invention also discloses a computer program product or a computer program, which comprises computer instructions, and the computer instructions are stored in a computer readable storage medium. The computer instructions may be read by a processor of a computer device from a computer-readable storage medium, and the computer instructions executed by the processor cause the computer device to perform the foregoing method.
The invention is described in detail below with reference to the accompanying drawings:
the thermal effect is one of the key factors which cause circuit aging and further restrict the performance of the integrated circuit, and the optimization design method taking the thermal effect as a breakthrough is expected to enhance the performance and the reliability of the circuit. Therefore, how to utilize the advantages brought by the process progress as much as possible while satisfying the performance and reliability requirements expected by the circuit design is a key issue to be solved urgently. The core of solving this problem is to reduce the negative effects of thermal effects from a physical source. The starting point of the invention is to relieve the thermal effect in the digital circuit and reduce the temperature dependence of the electrical characteristics, and the specific idea is realized as follows: the invention provides a method for rapidly determining a zero-temperature delay working point of a standard unit from a device level by introducing a design strategy of zero-temperature delay (the influence of circuit delay on temperature change is close to zero), simultaneously establishes a corresponding implementation flow for determining the optimal zero-temperature delay working point of a large-scale digital circuit level, and enhances the immunity of a digital circuit to temperature by providing an accurate zero-temperature delay working point range and a corresponding design scheme for chip design.
The invention provides a method, a system, equipment and a medium for improving the temperature immunity of a digital circuit, and aims to enhance the temperature immunity of the digital circuit delay based on the proposed zero-temperature delay working point design strategy, further relieve the heat effect under the advanced process, improve the reliability of the digital circuit and the system on the premise of balancing the performance and the power consumption, and particularly serve the digital circuit design based on a standard unit under the advanced process.
The operation steps of the invention are two parts, and the core content and the purpose of each part are summarized as follows:
the first part is the determination of zero-temperature delay operating points from a device level to a standard unit level, and the output information is the distribution range of the zero-temperature delay operating points of each standard unit in a standard unit library, as shown in fig. 1; the second part is to determine the optimal zero-temperature delay working point of the large-scale digital circuit by using a zero-temperature delay working point database of a standard unit level, and the output information is the key path of the circuit and the optimal zero-temperature delay working point thereof.
It should be noted that the present invention relates to two levels of zero-temperature delay operating points, namely, the zero-temperature delay operating point of the standard cell and the zero-temperature delay operating point of the digital circuit, which are different but closely related. The power supply voltage at which the delay of the standard cell is least affected by temperature variation is defined as the zero temperature delay operating point of the standard cell. Generally, since a digital circuit design is formed by combining a large number of standard cells according to their logic functions, and the difference between different standard cells due to their circuit structures and operating waveforms causes the zero-temperature delay operating points of the cells to be different, the zero-temperature delay operating point of the digital circuit refers to the power supply voltage at which the delay temperature dependency of the critical path of the digital circuit is minimal, and the zero-temperature delay operating point of the digital circuit is determined by each standard cell on its critical path. The zero temperature coefficient point is referred to as a device, and the working voltage value corresponding to the device when the effective drain current of the device changes minimally along with the temperature is expressed.
The first part is the determination of zero-temperature delay working points from a device level to a standard unit level, and the specific operation steps are as follows:
the method comprises the following steps: in the standard cell transient simulation, firstly, a standard cell is selected to perform transient response simulation, referring to fig. 2, the inverter is taken as an example, available processes include TCAD (computer aided design) and SPICE (integrated circuit simulation software), and transient voltage and current curves of the standard cell can be obtained. The delay in the transient response is defined by the output voltage (V) OUT ) Reaches 50% of the supply voltage and the input voltage (V) on the rising edge IN ) The time interval at which the falling edge reaches 50% of the supply voltage, defined as t pLH The time interval between the time when the output voltage reaches 50% of the operating voltage at the falling edge and the time when the input voltage reaches 50% of the operating voltage at the rising edge is defined as t pHL 。t pLH And t pLH Is defined as the propagation delay t p . In FIG. 2, (a) is the input-output voltage transient response waveform of the standard cell of the inverter, (b) is the transient current response of the NFET and PFET in the inverter, and (c) is a schematic diagram of the voltage waveform experienced by the NFET in the inverter;
the calculation of each time delay at different temperatures is shown below:
wherein, t pHL (T)，t pLH (T)，t p (T) represents the standard cell circuit delay at different temperatures, C L Load capacitance of standard cell, V DD As a standard cellSupply voltage of V GS Is the voltage between the gate node and the source node of the transistor in the standard cell, V DS Is the voltage between the drain node and the source node of the transistor in the standard cell, I DS Is the current between the drain node and the source node of the transistor in the standard cell, I DS And V GS 、V DS Is dependent on temperature, I DS Is I of all transistors in standard cell DS And (4) summing.
Step two: tracking device current and voltage tracks and selecting voltage sampling points, wherein the step comprises the following steps: determining a leading device influencing the time delay of the standard unit from the current transient response, acquiring a working voltage track of the device, and then selecting a proper sampling point on the voltage track. From the equations (1) and (2), the delay of the standard cell at different temperatures is determined by the effective driving current of the device in the corresponding delay interval, as shown in fig. 2 (b). Through the simulation result of the first step, time intervals of various delays can be obtained according to the input and output voltage response waveforms of the standard cell, and a delay parameter t can be judged according to a transient current curve of a device (N-type field effect transistor (NFET)/P-type field effect transistor (PFET)) in the standard cell pHL ，t pLH Which device/devices (NFET/PFET) is/are dominant. Secondly, in order to conveniently and rapidly determine the effective current of the device in the standard cell during operation at the device level, the voltage V between the nodes is extracted from the obtained delay time interval GS And V DS The operating voltage trace of the device is formed, as shown in fig. 2 (c). As can be seen from FIG. 2 (c), as the power voltage decreases, the shape of the voltage trace also decreases approximately in equal proportion, so the sampling points in the voltage trace are selected based on the power voltage as a reference, and the selection principle suggests that the horizontal and vertical distances between two adjacent voltage sampling points should be 0.1-0.25V DD Within the scope, the selection principle can realize better balance on the complexity and the precision of the calculation. Taking inverter as an example, according to this principle, it is recommended to select three voltage sampling points, respectively (V) GS ＝±0.5V DD ,V DS ＝±V DD )，(V GS ＝±V DD ,V DS ＝±0.5V DD ) And (V) GS ＝±0.75V DD ,V DS ＝±0.75V DD ) Wherein, taking "+" as the representative means to calculate the time delay t pHL Taking "-" as the representative of the calculated time delay t pLH Voltage sampling points of (a). The specific number of sampling points in the voltage trace depends on the voltage waveform experienced by the device in the standard cell and the voltage sampling point selection principle.
Step three: calculating effective drive current of the device influencing the standard unit time delay, and after the voltage sampling point is obtained in the second step, working the device at V GS And V DS The current under the voltage combination is subjected to integral averaging, as shown in formulas (1) and (2), and the obtained value is the effective driving current I eff . Performing mixed-mode simulation of TCAD (ternary content addressable memory) devices at different temperatures or simulation of SPICE (static random Access memory) circuit at different temperatures on the device to further obtain I (internal temperature) of the device at different temperatures effLH (T) and I effHL (T) curve, as shown in FIG. 3, wherein (a) is I effLH (b)I effHL (c)I eff Wherein V is from left to right in the figure ZTC Values respectively corresponding to t pHL ，t pLH And t p The zero-temperature delay operating point of (c) is shown in fig. 3 (a) and 3 (b), and t at different temperatures is calculated by formula (4) p Corresponding effective current I eff (T) represented by the following formula:
wherein, I effHL (T) is T pHL Corresponding to the effective current at different temperatures, I effLH (T) is T pLH Corresponding to the effective current at different temperatures. Plotting t p Corresponding effective current I eff (T) along with the change curve of the working voltage and the temperature, as shown in fig. 3 (c), finding out the point of the curve where the effective current does not change along with the temperature, and the voltage value corresponding to the point is the zero-temperature delay working point of the standard unit. Thus, the problem of delayed immunity to temperature of the standard unit is converted into the effectiveness of the deviceIn the problem of current-to-temperature immunity, the zero temperature coefficient point of the effective current of the device in the figure can be regarded as the zero temperature delay working point of the standard unit. In particular, the average propagation delay t is taken p I.e. dI eff And (T)/dT =0 is taken as the zero-temperature delay operating point of the standard unit.
Step four: counting zero-temperature delay working points of a standard cell library, wherein the types of standard cells used in circuit design are considered; secondly, different working conditions such as circuit load and the slope of the input signal have certain influence on the zero-temperature delay working point. Therefore, the steps from the first step to the third step are repeated for other standard units in the standard unit library, different circuit load and signal conversion rate combinations are simultaneously converted, the typical values can be set by referring to the table 1, and the delay t of each standard unit is automatically counted in a script mode p I.e. I eff And establishing a zero-temperature delay working point database which can be searched by the standard unit type and the working condition so as to facilitate the use of the subsequent second part.
TABLE 1 typical value ranges for the load capacitance and input slope parameter settings of standard cells, e.g. C L ＝10fF，T SL ＝10ns
The second part is the determination of the optimal zero-temperature delay working point for the large-scale digital circuit, and the specific operation steps are as follows:
the method comprises the following steps: and (3) taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to finish the logic synthesis process: the files that need to be prepared at this step include behavioral description files that describe the expected logic function of the circuit, such as Verilog or Verilog HDL files, formatted as.v files, followed by logic synthesis of the netlist using logic synthesis tools such as Design Compiler, encounter RTL Compiler, etc. The specific operation is to import the netlist into a logic synthesis tool, input a sequential constraint file in an sdc format, where the initial power supply voltage setting value is the statistical average of the zero-temperature delay operating points of all the standard units obtained in the first part, and the synthesis tool performs logic synthesis on the netlist according to the sequential constraint file, the power supply voltage and other settings, that is, optimizes the area and power consumption of the circuit. And the gate-level netlist generated after the logic synthesis is the gate-level netlist meeting the requirements of the timing constraint file, and comprises various standard units meeting the process conditions.
Step two: according to the time sequence analysis result after the logic synthesis in the step one, a logic synthesis tool is used for screening out a key path, all standard units on the path are output, the types of the standard units appearing on the path are counted, based on the zero-temperature delay working point data of each standard unit obtained in the step one, weighted average is carried out according to the proportion of each standard unit appearing, the zero-temperature delay working point under the key path is obtained and compared with the initial power supply voltage value, if the zero-temperature delay working point under the key path is different from the initial power supply voltage value in the step one, the zero-temperature delay working point under the key path is required to be used as a new power supply voltage value of the circuit, the logic synthesis in the step one and the extraction and comparison operation of the zero-temperature delay working point of the key path in the step two are carried out again, and iteration is carried out until the power supply voltage value is consistent with the zero-temperature delay working point under the key path or the difference value is smaller than 0.01V.
Step three: and C, performing subsequent physical design on the gate-level netlist generated in the step two, wherein the physical design is a process of converting the circuit gate-level netlist into a layout. The specific process comprises the following steps: firstly, carrying out layout planning, and dividing a gate-level netlist by adopting a layout planning tool such as an IC Compiler; and then, performing layout and wiring, wherein the step of electrically connecting the divided netlists according to the positions and the relations of circuit units or modules by using an automatic layout and wiring tool, performing two steps of design rule verification and layout and schematic diagram comparison on the generated layout, entering a parasitic parameter extraction process, acquiring parasitic parameters of the layout, and performing time sequence simulation. The final physical layout is delivered to the foundry in GDSII format. Fig. 4 shows that the influence of temperature on the operating frequency of the circuit designed based on the zero-temperature delay operating point is greatly reduced, and meanwhile, the thermal effect is relieved, the temperature is reduced by 1.9 times compared with that of 0.9V, and meanwhile, the power consumption delay square product obtains the minimum value under the zero-temperature delay operating point, and the performance, the power consumption and the reliability are well balanced. As can be seen from (a) in fig. 4, the fluctuation of the circuit frequency at the zero-temperature delay-based operating point is greatly reduced by the influence of the temperature; as can be seen from (b) in fig. 4, the zero-temperature delay operating point is selected as the self-heating effect mitigation brought by the power supply voltage and the power consumption and performance tradeoff effect.
In summary, the present invention can determine the zero-temperature delay operating point for improving the temperature immunity according to the digital circuit design, and use the operating point as the power supply voltage of the circuit, thereby achieving the purposes of alleviating the self-heating effect and reducing the temperature dependence of the circuit delay, suppressing the adverse effect of temperature fluctuation on the circuit performance with the lowest design cost, realizing the balance of performance, power consumption and reliability, and facilitating the development of the digital circuit in the field of the design requirements of low power consumption and high reliability.
Compared with the prior art, the invention has the following characteristics:
1. the design strategy based on the zero-temperature delay working point is as follows: by utilizing the characteristic that the temperature dependence of the circuit delay under a certain power supply voltage is close to zero due to the competitive relationship between the mobility and the threshold voltage on the temperature dependence, the zero-temperature delay working point is used as the power supply voltage in the design of the digital circuit, so that the performance degradation influence caused by the thermal effect is reduced as much as possible from the physical source, and the reliability of the digital circuit under the advanced process is enhanced.
2. The method for determining the zero-temperature delay working point from the device level to the standard unit level comprises the following steps: the method comprises the steps of tracking key devices contributing to standard unit time delay through current waveforms, sampling voltage waveforms of the key devices when the key devices work, carrying out integral averaging on currents corresponding to voltage sampling points to obtain effective driving currents, and taking the power voltage with the minimum temperature dependency of the effective driving currents of the devices as a zero-temperature time delay working point of a standard unit.
3. A large-scale circuit design method based on zero-temperature delay working points comprises the following steps: the method comprises the steps of determining standard units influencing digital circuit delay according to a critical path determined by time sequence analysis on the basis of data of a zero-temperature delay working point of a standard unit library, determining an optimal zero-temperature delay point by a weighted average statistical method, and realizing the balance of performance, power consumption and reliability of the digital circuit on the basis of the principle.
Compared with the prior art, the invention has the following advantages:
1. the zero-temperature delay working point is used as the working voltage, so that the dependence of the key index delay of the digital circuit on the temperature is fundamentally reduced, the time sequence protective band related to heat is prevented from being introduced during design, and the performance loss caused by the heat time sequence protective band can be reduced.
2. The method has the advantages that extra design overhead is not required to be introduced, such as chip area is increased, meanwhile, since the zero-temperature delay working point is only correspondingly adjusted according to the power supply voltage, the method is simple to realize, the power consumption is reduced, the heat effect is relieved, the reliability of the chip is improved, better balance among the power consumption, the performance and the reliability is realized, and the method is particularly suitable for application scenes with low power consumption and high reliability requirements.
3. Different from the application of zero temperature coefficient points in analog circuits, the zero temperature delay working point design strategy provided by the invention is a customized scheme aiming at digital circuit design, provides an efficient and rapid determination method from devices to standard units and to large-scale circuits, and is convenient for users to determine the working points providing the circuit temperature immunity according to the own circuit design.
In alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flow charts of the present invention are provided by way of example in order to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of larger operations are performed independently.
Furthermore, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the described functions and/or features may be integrated in a single physical device and/or software module, or one or more functions and/or features may be implemented in a separate physical device or software module. It will also be understood that a detailed discussion of the actual implementation of each module is not necessary for an understanding of the present invention. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be understood within the ordinary skill of an engineer, given the nature, function, and internal relationship of the modules. Accordingly, those skilled in the art can, using ordinary skill, practice the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative of and not intended to limit the scope of the invention, which is to be determined from the appended claims along with their full scope of equivalents.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part thereof which substantially contributes to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following technologies, which are well known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method for improving temperature immunity of a digital circuit, comprising:
determining zero-temperature delay working points from a device level to a standard unit level; determining an optimal zero-temperature delay working point for the large-scale digital circuit;
the determination of the zero-temperature delay operating point from the device level to the standard unit level comprises the following steps:
selecting a standard unit to perform transient simulation;
tracking a current track and a voltage track of the device and selecting a voltage sampling point;
calculating the effective driving current of the device and the temperature dependence of the device;
determining zero-temperature delay working points of the standard units;
establishing a zero-temperature delay working point database of a standard unit library, and determining zero-temperature delay working points from a device level to the standard unit level;
the determination of the optimal zero-temperature delay working point for the large-scale digital circuit comprises the following steps:
taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to finish the logic synthesis process;
generating a gate-level netlist of the circuit according to the time sequence analysis result of the logic synthesis;
and carrying out physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay working point facing the large-scale digital circuit.
2. The method as claimed in claim 1, wherein the selecting standard cells for transient simulation comprises:
acquiring transient voltage and current curves of the standard unit;
acquiring a first time interval between the time when the rising edge of the output voltage reaches 50% of the power supply voltage and the time when the falling edge of the input voltage reaches 50% of the power supply voltage;
acquiring a second time interval between the time when the falling edge of the output voltage reaches 50% of the working voltage and the time when the rising edge of the input voltage reaches 50% of the working voltage;
and calculating the propagation delay according to the first time interval and the second time interval.
3. The method of claim 1, wherein tracking device current and voltage traces and selecting voltage sampling points comprises:
determining a leading device influencing the standard cell delay from the current transient response;
acquiring a working voltage track of the leading device;
and selecting a proper sampling point on the voltage track according to the working voltage track of the master device.
4. The method of claim 1, wherein calculating the effective drive current of the device and the temperature dependence of the device comprises:
after a voltage sampling point is obtained, performing integral averaging on the current of the device working under the voltage combination of VGS and VDS to obtain effective driving current;
performing mixed-mode simulation of TCAD devices at different temperatures or simulation of SPICE circuits at different temperatures on the devices to obtain effective currents and effective current curves of the devices at different temperatures, and calculating effective currents corresponding to propagation delay at different temperatures;
and finding out a point of the effective current curve, wherein the effective current does not change along with the temperature, and using the point as a zero-temperature delay working point of the standard unit.
5. The method as claimed in claim 1, wherein the determining the zero temperature delay operating point of each standard cell comprises:
and transforming different circuit load and signal conversion rate combinations, counting zero-temperature delay working points determined by the delay of each standard unit, and establishing a zero-temperature delay working point database which can be searched through the types and working conditions of the standard units.
6. The method of claim 1, wherein the performing of the logic synthesis process with the zero temperature coefficient point statistical average of the standard cell library as the initial power supply voltage comprises:
preparing a behavior description file describing expected logic functions of the circuit;
and according to the behavior description file and the timing constraint file, performing logic synthesis on a netlist by adopting a logic synthesis tool to generate a gate-level netlist meeting the requirements of the timing constraint file.
7. The method for improving temperature immunity of a digital circuit according to claim 1, wherein the physical design is performed according to the gate-level netlist, the gate-level netlist is converted into a layout, and an optimal zero-temperature delay operating point facing a large-scale digital circuit is determined, including:
performing layout planning by adopting a layout planning tool to divide the gate-level netlist;
electrically connecting the divided netlists according to the positions and the relations of the circuit units or modules by using an automatic layout and wiring tool, performing two steps of design rule verification and layout and schematic diagram comparison on the generated layout, entering a parasitic parameter extraction process, acquiring parasitic parameters of the layout, and performing time sequence simulation;
wherein, the time sequence simulation tool is a PrimeTime time sequence analysis tool.
8. The device for improving the temperature immunity of the digital circuit is characterized by comprising a first module and a second module;
the first module is used for determining a zero-temperature delay working point from a device level to a standard unit level;
the second module is used for determining the optimal zero-temperature delay working point facing the large-scale digital circuit;
wherein the first module is specifically configured to:
selecting a standard unit to perform transient simulation;
tracking a current track and a voltage track of the device and selecting a voltage sampling point;
calculating the effective driving current of the device and the temperature dependence of the device;
determining a zero-temperature delay working point of each standard unit;
establishing a zero-temperature delay working point database of a standard unit library, and determining zero-temperature delay working points from a device level to the standard unit level;
the second module is specifically configured to:
taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to finish the logic synthesis process;
generating a gate-level netlist of the circuit according to the time sequence analysis result of the logic synthesis;
and carrying out physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining an optimal zero-temperature delay working point facing the large-scale digital circuit.
9. An electronic device comprising a processor and a memory;
the memory is used for storing programs;
the processor executing the program realizes the method of any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that the storage medium stores a program which is executed by a processor to implement the method of any one of claims 1 to 7.
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