CN113868991A - Design method of digital standard unit under near-threshold power supply voltage - Google Patents
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Abstract
The invention discloses a design method of a digital standard unit under a near-threshold power supply voltage, and belongs to the technical field of low-power-consumption chip design. Firstly, determining the optimal power supply voltage; secondly, under the optimal power supply voltage, obtaining the curve relation between the channel length of each MOS tube and the target function through simulation, and determining the optimal channel length of each MOS tube; then, substituting the optimal power supply voltage and the optimal channel length of each MOS tube into a corresponding MOS tube current model under the near-threshold power supply voltage; on the basis that the conduction currents of the pull-up network and the pull-down network are equal, an equation set comprising the channel width and the threshold voltage of each MOS tube is constructed; and finally, solving the equation set by using a numerical method to obtain the optimal channel width of each MOS tube. The method can rapidly measure the time sequence characteristics of the digital standard cell on the premise of ensuring extremely high accuracy, and obviously reduces the time cost of developing the digital standard cell library under the condition of close threshold power supply voltage.
Description
Technical Field
The invention belongs to the technical field of low-power chip design, and particularly relates to a design method of a digital standard unit under a near-threshold power supply voltage.
Background
In recent years, with the rapid iteration of chip process nodes, the integration level of a chip and the working frequency of a circuit are higher and higher, and the power density of the chip is also increased sharply, so that not only is a large amount of energy consumed on heating, but also the service life of the chip is shortened by an excessively high temperature, and even the chip cannot work at all. In addition, with the application of the internet of things and the rapid development of the performance of mobile terminal equipment, the battery-powered electronic product puts higher and higher requirements on endurance time. Therefore, low power consumption techniques play an increasingly critical role in the way integrated circuits continue to evolve.
At present, in the technical field of low-power chip design, a clock gating technology is mainly adopted, and traditional methods such as multi-voltage domain power supply, RTL (register transfer level) logic improvement, algorithm optimization and the like are adopted. Compared with the conventional method, reducing the overall power supply voltage of the chip is the most direct and efficient energy-saving method, but if the power supply voltage is directly reduced to the sub-threshold voltage region of the transistor, the performance deterioration such as reliability, working frequency, delay and the like is caused. However, research shows that when the power supply voltage of the chip circuit is near (slightly higher or slightly lower) the transistor starting voltage, namely near the threshold voltage, the chip can not only significantly reduce the power consumption, but also ensure the working frequency to a certain extent. Therefore, it is important to research chips operating at near threshold voltages.
The traditional digital standard cell can not normally work under the near-threshold voltage, so the chip design under the near-threshold voltage can not be directly carried out by adopting the existing digital standard cell library, the structure and the size of the cell need to be optimized, and the digital standard cell library under the near-threshold power supply voltage can be redeveloped.
On the premise of determining the structure of the digital standard unit, the digital standard unit also needs to be designed in size. Even with the same structure, the difference in the dimensional parameters leads to a large difference between the cell performances, and therefore the dimensional design is of utmost importance. Because there is no perfect near-threshold voltage model at present, if a traditional design process is adopted, only size scanning can be performed on each digital unit, and then an optimal size parameter is found out according to a simulation result and in combination with an objective function, which not only consumes a lot of manpower and computing power, but also the design cycle becomes quite long (even if a complete simulation of a simple unit takes at least several months). Therefore, how to design a set of digital standard cell library suitable for the near-threshold power supply voltage quickly and efficiently becomes a problem to be solved urgently.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a design method of a digital standard unit under a near-threshold power supply voltage, which not only brings the process deviation of the digital standard unit into model calculation, can improve the reliability of design, but also can solve the problem of complexity and slowness of the traditional development process, and obviously reduces the time cost consumed by the development process on the premise of ensuring extremely high accuracy.
In order to achieve the above object, the present invention provides a method for designing a digital standard cell under a near-threshold supply voltage, comprising the following steps:
s1, adopting a plurality of MOS tubes to construct a standard unit circuit, taking the power supply voltage as a scanning variable, and scanning the standard unit circuit to obtain the energy consumption and the time delay of the standard unit circuit under different power supply voltages; determining an optimal supply voltage in combination with an objective function regarding said energy consumption and time delay;
s2, under the optimal power supply voltage, obtaining a curve relation between the channel length of each MOS tube and the target function through simulation, and determining the optimal channel length of each MOS tube;
s3, substituting the optimal power supply voltage and the optimal channel length of each MOS tube into a corresponding MOS tube current model under the near-threshold power supply voltage; on the basis that the conduction currents of the pull-up network and the pull-down network are equal, an equation set comprising the channel width and the threshold voltage of each MOS tube is constructed;
and S4, solving the equation set by using a numerical method to obtain the optimal channel width of each MOS tube.
Further, in S1, the objective function F ═ EmDelay, where E represents energy consumption, Delay represents time Delay, and m is a positive number.
Further, in S1, determining an optimal power supply voltage in combination with the objective function regarding the power consumption and the delay time includes: and determining the optimal power supply voltage by taking the minimized objective function F as a target.
Further, the S2 includes:
s21, under the optimal power supply voltage, obtaining the curve relation between the channel length of each MOS tube and the objective function through simulation, and recording the corresponding channel length when the objective function value is minimum as a first channel length LoThe corresponding objective function value is denoted as Fo；
S22, for the first channel length L of each MOS tubeoCarrying out Monte Carlo simulation, and recording the standard deviation of the conduction current of the MOS tube as sigma;
s23, performing monte carlo simulation on the channel length of each MOS transistor, and recording the channel length corresponding to the standard deviation x σ of the on-state current as a second channel length Lox，0.7≤x≤0.9；
S24, the channel length of each MOS transistor is the second channel length LoxThen, DC scanning simulation is carried out on the standard unit circuit to obtain a new objective function value FoxIf F isox≤yFoThen take LoxTo an optimal channel length; if Fox>yFoThen, DC scanning simulation is carried out on the channel length of each MOS, and the objective function value is taken as yFoThe corresponding channel length is the optimal channel length, and y is more than or equal to 1.1 and less than or equal to 1.2.
Further, the S4 includes: segmenting the channel width value range of each MOS tube, determining the threshold voltage corresponding to each segment range and substituting the threshold voltage into the equation set; and solving the equation set by using a numerical method to obtain the optimal channel width of each MOS tube.
Further, the standard cell circuit is a two-input nand gate standard cell circuit.
Further, the MOS tube comprises an NMOS tube and a PMOS tube.
Generally, by the above technical solution conceived by the present invention, the following beneficial effects can be obtained:
the method comprises the steps of modeling conducting current of the MOS tube under the voltage close to a threshold value, and fitting the model by utilizing simulation data to obtain relevant characteristic parameters; further deducing the current model by using a statistical principle and process characteristics under corresponding process nodes to obtain a current model under the influence of process deviation; carrying out simulation analysis on each size parameter of the MOS tube, summarizing correlation, enabling the size parameters with small correlation to be independent, and designing a target function to obtain an optimal value of the independent parameters so as to reduce the number of variables in the model; a standard unit size design matching principle is provided, and a size parameter equation set is constructed by utilizing the derived current distribution model under the principle; solving a size parameter equation set by using mathematical analysis methods such as threshold voltage segmentation by ratio, series node voltage piecewise linearity and the like; compared with the actual simulation result, the model and the method can rapidly measure the time sequence characteristics of the digital standard unit on the premise of ensuring extremely high accuracy, remarkably reduce the time cost of digital standard unit library development under the condition of near-threshold power supply voltage, comprehensively consider various indexes such as time delay, energy consumption, conversion time and the like, and have application value.
Drawings
Fig. 1 is a flowchart of a method for designing a digital standard cell under a near-threshold power supply voltage according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a two-input NAND standard cell circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a situation where only one PMOS transistor of a pull-up network in a two-input NAND gate according to an embodiment of the present invention is turned on;
fig. 4 is a schematic diagram illustrating a situation that two NMOS transistors of a pull-down network in a two-input nand gate are both turned on according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In the present application, the terms "first," "second," and the like (if any) in the description and the drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Referring to fig. 1, the present invention will be further explained with reference to fig. 2 to 4. Fig. 1 is a flowchart of a method for designing a digital standard cell under a near-threshold power supply voltage according to an embodiment of the present invention, including the following steps:
s1, adopting a plurality of MOS tubes to construct a standard unit circuit, taking the power supply voltage as a scanning variable, and scanning the standard unit circuit to obtain the energy consumption and the time delay of the standard unit circuit under different power supply voltages; determining an optimal supply voltage in combination with an objective function regarding said energy consumption and time delay;
s2, under the optimal power supply voltage, obtaining a curve relation between the channel length of each MOS tube and the target function through simulation, and determining the optimal channel length of each MOS tube;
s3, substituting the optimal power supply voltage and the optimal channel length of each MOS tube into a corresponding MOS tube current model under the near-threshold power supply voltage; on the basis that the conduction currents of the pull-up network and the pull-down network are equal, an equation set comprising the channel width and the threshold voltage of each MOS tube is constructed;
and S4, solving the equation set by using a numerical method to obtain the optimal channel width of each MOS tube.
In this embodiment, taking a two-input nand gate unit in a digital standard cell library as an example, as shown in fig. 2, a design method of a digital standard cell under a near-threshold power supply voltage is provided based on a 55nm technology of a rainbow semiconductor, and includes the following steps:
for Chinese rainbow-based semi-ringsAnd (4) performing spot simulation on the NAND gate standard unit under the normal power supply voltage of the conductor 55nm process. The two-input nand gate circuit in fig. 2 is scanned with VDD (supply voltage) as a scanning variable to obtain energy consumption (E) and Delay (Delay) corresponding to different VDD (supply voltage), and a corresponding Energy Delay Product (EDP) is calculated. An optimal voltage range is obtained according to the compromise of three parameters of energy consumption, time delay and Energy Delay Product (EDP), wherein the energy consumption refers to the energy consumed by the circuit in one clock cycle and can be obtained by multiplying the integral of the power supply current in one cycle by the power supply voltage, namely
Delay refers to the time required between a 50% change in the input signal to a 50% change in the output signal; the energy Delay product is the product of the two, i.e., EDP ═ E · Delay).
In order to simulate the actual depth of a combinational logic cascade unit in a chip, a two-input NAND gate structure is utilized for cascade connection, a multi-stage four-fan-out NAND gate test link is built, a target frequency is selected, namely the frequency required to be met in the actual work of the chip, the NAND gate test link is subjected to scanning simulation in the range of the optimal power supply voltage, the optimal power supply voltage is determined by combining an objective function related to energy consumption and time delay, wherein the objective function F is EmAnd (4) Delay, wherein m is a positive number, the consideration proportion of the energy factor in the objective function is represented, and the size of m can be automatically adjusted according to the requirement.
After the optimal power supply voltage is determined, in order to reduce size design variables, simulation analysis is firstly carried out on all size parameters of a PMOS (P-channel metal oxide semiconductor) tube and an NMOS (N-channel metal oxide semiconductor) tube in an NAND gate unit, the correlation of all size parameters is summarized and analyzed, and the channel length L of the MOS tube is obtainedpAnd LnThe length of the channel of PMOS (NMOS) is approximately in the same minimum range to ensure that the target function F reaches the optimal solution F when the correlation between the parameters and other dimension parameters is minimum, namely other dimension parameters are differentpo(Fno) The channel length at this time is denoted as Lpo(Lno)。
At low voltages, MOS devices are more strongly affected by various deviations, mainly manifested as severe device on-currentAnd the variation leads to unstable working state of the device. Considering the process bias effect, we select the proper Wp(channel width of PMOS transistor), and the obtained PMOS channel length L under the optimum power supply voltagepoMonte Carlo (MC) simulation is carried out, and the standard deviation sigma of the PMOS breakover current at the moment is recorded1. Then, for LpPerforming MC scanning simulation, and enabling the standard deviation of the conduction current to be x1σ1(the smaller the standard deviation of the on-state current, the higher the deviation resistance, x is more or less than 0.71Less than or equal to 0.9, in this example x is taken10.8) is recorded as Lpox. At a channel length of LpoxIn the process, DC simulation is carried out on the NAND gate unit, and a new objective function value F is obtained through calculationpoxIf F ispox≤y1FpoThen take LpoxIs the final Lp(ii) a If Fpox>y1FpoThen, the channel length L to PMOSpPerforming DC scanning simulation, and taking the objective function value as y1FpoThe channel length of time is determined as Lp。1.1≤y11.2, preferably, in this example, y is taken11.1 as the ratio; by selection of the appropriate channel length, a highly robust dimensioning at the expense of less than 10% performance loss is achieved.
The NMOS transistor of the two-input NAND gate has a stacked structure, and the channel width (W) of the NMOS transistor at the near end is as indicated by the literatureL) Should be larger than the channel width (W) of the far-end NMOS transistorU) Large, so according to this principle, a suitable W is selectedLAnd WUFixing the length of the channel of the obtained stacked NMOS transistor at the optimum power supply voltagenoMonte Carlo (MC) simulation is carried out, and the standard deviation sigma of the NMOS breakover current at the moment is recorded2. Then, for LnPerforming MC scanning simulation, and enabling the standard deviation of the conduction current to be x2σ2(the smaller the standard deviation of the on-state current, the higher the deviation resistance, x is more or less than 0.72Less than or equal to 0.9, in this example x is taken20.8) is recorded as Lnox. At a channel length of LnoxIn the process, DC simulation is carried out on the NAND gate unit, and a new objective function value F is obtained through calculationnoxIf F isnox≤y2FnoThen take LnoxIs the final Ln(ii) a If Fnox>y2FnoChannel length L for NMOSnPerforming DC scanning simulation, and taking the objective function value as y2FnoThe channel length of time is determined as Ln。1.1≤y21.2, preferably, in this example, y is taken2＝1.1。
Two worst conditions of the two-input NAND gate standard unit during working are considered, wherein only one PMOS tube of the pull-up network is conducted, and two NMOS tubes of the pull-down network are conducted to form a path to the ground. The conduction current is the smallest in both cases. A standard cell size design matching principle is proposed, and in order to reduce the current mismatch between the pull-up network and the pull-down network and thus reduce the working error, the conduction currents in the two cases should be made equal as much as possible.
According to the MOSFET conduction current formula under the near threshold voltage, taking NMOS tube as an example, wherein Vth>0：
Where μ is the effective electron mobility, CoxIs the unit area oxide capacitance, n is the slope coefficient, L and W are the channel length and channel width, phi, respectivelytIs a thermal voltage, VthIs the threshold voltage, VgIs the gate voltage, VdIs the drain voltage, VsIs the source voltage, k0，k1And k2Is a process independent coefficient.
The on-current of the MOS tube is simulated to obtain the data of the simulation result, and the on-current formula of the MOS tube under the voltage close to the threshold value is used for fitting the simulation data to obtain the related characteristic parameters n, k in the formula0，k1And k2The specific numerical value of (1). Due to the randomness of the process variations, corresponding variations in the threshold voltage occur, and it is known from the literature that such random variations are normally distributed and thus probabilistically distributedKnowledge of theoretical and mathematical statistics can obtain that the current formula satisfies logarithmic skewed distribution, so that a mean value model of the current containing random process deviation information can be obtained by using the property of the logarithmic skewed distribution.
For the case that only one PMOS tube is conducted, as shown in FIG. 3, the conduction current is set as IpmosFrom V togb＝Vds＝-VDD,Vsb＝0V，VsVDD, where Vth<0, the conduction current equation at this time can be written as:
determining a slope coefficient n, and fitting the formula according to the simulation result to obtain a parameter k0，k1And k2In which V isg＝0，VsIs VDD, so IpmosIs not known and only V remainsthpAnd Wp. Taking into account process variations due to VthpNormally distributed, and according to the property of log-skewed distribution, E [ I ] can be obtainedpmos]。
For the condition that both NMOS transistors of the pull-down network are turned on, as shown in fig. 4, the turn-on current is IstackThen can obtain Istack＝IU＝IL. I can be replaced by the conduction current passing through the NMOS tube near the ground end in the NMOS tube stacking structurestackThe on-current at this time can be formulated as:
wherein VxFor the node voltage between two NMOS tubes, simulation shows that the node voltage is within a certain range with VthUAnd VthLIn an approximately linear relationship, i.e.
Vx＝a1 VthU+a2VthL+a3 (4)
Fitting the above formula by using a simulation result to obtain a1、a2、a3And substituting the formula (4) into the formula (3), wherein the parameter k0，k1And k2Is constant regardless of the process, and can therefore be derived from the fit IpmosSubstituting the obtained value into the formula, and leaving only V in unknown amountthU、VthLAnd WL. Taking into account process variations due to VthUAnd VthLNormally distributed, and according to the property of log-skewed distribution, E [ I ] can be obtainedL]。
Let E [ I ]pmos]＝E[IL]The unknown quantity W is contained in the equationpAnd WLAnd E [ V ]thp]、E[VthU]And E [ V ]thL]According to Vth(Vthp，VthU，VthL) Following W (W)p，WU，WL) The variation simulation result is to segment the variation range of W and to segment V in each segmentthApproximately to a constant value equal to the median value within the segment.
Combining V in a certain segmentth(Vthp，VthU，VthL) Substitution of median value into E [ I ]pmos]＝E[IL]E [ V ] in the equationthp]、E[VthU]And E [ V ]thL]So that only the unknown quantity W remains in the equationpAnd WLSolving the final equation by using Matlab software to obtain WpAnd WLIf the numerical solutions happen to fall within the segment of W, then these numerical solutions can be used as a set of solutions to the equation, with the selection corresponding to V at that timethUW of a numerical valueUIs matched to the set of solutions to obtain a set of dimensional design parameters.
And continuing to repeat the previous step until all the segment combination conditions related to W are solved.
And comparing the size design parameter sets, verifying by using a simulation tool, and selecting the optimal values in the sets as final size design parameters.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A design method of a digital standard cell under a near-threshold power supply voltage is characterized by comprising the following steps:
s1, adopting a plurality of MOS tubes to construct a standard unit circuit, taking the power supply voltage as a scanning variable, and scanning the standard unit circuit to obtain the energy consumption and the time delay of the standard unit circuit under different power supply voltages; determining an optimal supply voltage in combination with an objective function regarding said energy consumption and time delay;
s2, under the optimal power supply voltage, obtaining a curve relation between the channel length of each MOS tube and the target function through simulation, and determining the optimal channel length of each MOS tube;
s3, substituting the optimal power supply voltage and the optimal channel length of each MOS tube into a corresponding MOS tube current model under the near-threshold power supply voltage; on the basis that the conduction currents of the pull-up network and the pull-down network are equal, an equation set comprising the channel width and the threshold voltage of each MOS tube is constructed;
and S4, solving the equation set by using a numerical method to obtain the optimal channel width of each MOS tube.
2. The method according to claim 1, wherein in S1, the objective function F ═ EmDelay, where E represents energy consumption, Delay represents time Delay, and m is a positive number.
3. The method for designing a digital standard cell under a near-threshold power supply voltage according to claim 2, wherein the step of determining an optimal power supply voltage in combination with the objective function regarding the power consumption and the delay in step S1 comprises: and determining the optimal power supply voltage by taking the minimized objective function F as a target.
4. The method for designing a digital standard cell under a near-threshold supply voltage according to claim 2 or 3, wherein the step S2 comprises:
s21, under the optimal power supply voltage, obtaining the curve relation between the channel length of each MOS tube and the objective function through simulation, and recording the corresponding channel length when the objective function value is minimum as a first channel length LoThe corresponding objective function value is denoted as Fo；
S22, for the first channel length L of each MOS tubeoCarrying out Monte Carlo simulation, and recording the standard deviation of the conduction current of the MOS tube as sigma;
s23, performing monte carlo simulation on the channel length of each MOS transistor, and recording the channel length corresponding to the standard deviation x σ of the on-state current as a second channel length Lox，0.7≤x≤0.9；
S24, the channel length of each MOS transistor is the second channel length LoxThen, DC scanning simulation is carried out on the standard unit circuit to obtain a new objective function value FoxIf F isox≤yFoThen take LoxTo an optimal channel length; if Fox>yFoThen, DC scanning simulation is carried out on the channel length of each MOS, and the objective function value is taken as yFoThe corresponding channel length is the optimal channel length, and y is more than or equal to 1.1 and less than or equal to 1.2.
5. The method for designing a digital standard cell under a near-threshold supply voltage according to claim 4, wherein the step S4 comprises: segmenting the channel width value range of each MOS tube, determining the threshold voltage corresponding to each segment range and substituting the threshold voltage into the equation set; and solving the equation set by using a numerical method to obtain the optimal channel width of each MOS tube.
6. The method of claim 1 or 5, wherein the standard cell circuit is a two-input NAND standard cell circuit.
7. The method as claimed in claim 1 or 5, wherein the MOS transistor comprises an NMOS transistor and a PMOS transistor.
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