CN116963376A

CN116963376A - Electronic device

Info

Publication number: CN116963376A
Application number: CN202210410294.XA
Authority: CN
Inventors: 危莉华; 林铭祥; 陈世豪; 叶财金
Original assignee: Hongtong Technology Xiamen Co ltd
Current assignee: Hongtong Technology Xiamen Co ltd
Priority date: 2022-04-19
Filing date: 2022-04-19
Publication date: 2023-10-27

Abstract

An electronic device includes a circuit board, a shielding member, and test pins. The circuit board includes a ground region. The shielding member is positioned on one side of the circuit board and comprises a shielding layer and an insulating layer. The shielding layer is electrically connected to the grounding region. The insulating layer is positioned on one side of the shielding layer far away from the circuit board. The test pins are arranged on the circuit board and are electrically connected with the shielding layer. Thus, the inspector can use the open/short circuit inspection instrument to inspect the on-resistance at the inspection pins to confirm the conductivity between the shield and the grounding area of the circuit board.

Description

Electronic device

Technical Field

The present disclosure relates to an electronic device.

Background

For normal function of electromagnetic shielding tape (EMI tape) (i.e., whether it is in conduction with the grounding area of the circuit board), destructive inspection is currently used in the industry. Specifically, the electromagnetic shielding tape includes stacked insulating layers and metal shielding layers. When the electromagnetic shielding tape is to be measured to determine whether the grounding area of the circuit board is conducted, the insulation layer needs to be scraped off, so that the impedance between the metal shielding layer and the grounding area can be measured.

However, the foregoing destructive inspection methods may cause the appearance of the circuit board to be broken, which is not allowed by a qualified product. Moreover, the traces on the circuit board are also exposed, thereby affecting the performance of the circuit board.

Therefore, how to provide an electronic device capable of solving the above-mentioned problems is one of the problems of the current industry to be solved by the research and development resources.

Disclosure of Invention

Accordingly, an objective of the present disclosure is to provide an electronic device that can solve the above-mentioned problems.

In order to achieve the above object, according to one embodiment of the present disclosure, an electronic device includes a circuit board, a shielding member, and a test pin. The circuit board includes a ground region. The shielding member is positioned on one side of the circuit board and comprises a shielding layer and an insulating layer. The shielding layer is electrically connected to the grounding region. The insulating layer is positioned on one side of the shielding layer far away from the circuit board. The test pins are arranged on the circuit board and are electrically connected with the shielding layer.

In one or more embodiments of the present disclosure, the circuit board further includes a pin area. The test pins are located in the pin area.

In one or more embodiments of the present disclosure, the shield further comprises a conductive layer. The conductive layer is positioned between the circuit board and the shielding layer.

In one or more embodiments of the present disclosure, the circuit board further includes a circuit layer. The circuit layer contains test circuits. The test pins are located at the ends of the test lines.

In one or more embodiments of the present disclosure, the test line is located at the ground area.

In one or more embodiments of the present disclosure, the circuit board further includes a contact pad. The contact pad is located in the grounding area and electrically contacts the test circuit and the shielding layer.

In one or more embodiments of the present disclosure, the circuit layer further includes a ground circuit. The grounding circuit and the test circuit are electrically insulated in the circuit layer.

In one or more embodiments of the present disclosure, the circuit board further includes a pin area. The grounding line is provided with a grounding pin which is positioned in the pin area. The grounding pin is electrically connected with the shielding layer.

In one or more embodiments of the present disclosure, the circuit board further includes a contact pad. The contact pad is located in the grounding area and electrically contacts the grounding circuit and the shielding layer.

In one or more embodiments of the present disclosure, the electronic device further includes another test pin. The other test pin is electrically connected to the shielding layer.

In one or more embodiments of the present disclosure, the circuit board further includes a pin area. The other test pin is located in the pin area.

In one or more embodiments of the present disclosure, the circuit board further includes a circuit layer. The circuit layer contains test circuits. The other test pin is located at the end of the test line.

In summary, in the electronic device of the present disclosure, the shielding layer of the shielding member is electrically connected to the test pins disposed on the circuit board. Therefore, a detector can use the open circuit/short circuit detector to detect the conduction resistance of the test pin to confirm the conduction between the shielding piece and the grounding area of the circuit board, so that the problem of the appearance damage of the circuit board caused by the conventional destructive detection mode can be effectively solved.

The above description is merely illustrative of the problems to be solved by the present disclosure, the technical means for solving the problems, the effects thereof and the like, and the specific details of the present disclosure are set forth in the following description and related drawings.

Drawings

The foregoing and other objects, features, advantages and embodiments of the present disclosure will be apparent from the following description of the drawings in which:

FIG. 1 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a circuit board according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram illustrating a circuit layer of a circuit board according to an embodiment of the disclosure;

fig. 4 is a schematic diagram illustrating a circuit layer of a circuit board according to another embodiment of the disclosure.

[ symbolic description ]

100 electronic device

110 circuit board

111 base layer

112,212 line layer

112a signal line

112a1 signal pin

112b,212b ground line

112b1,212b1 ground pins

112c,112d test lines

112c1,112d1 test pins

113 cementing layer

114 cover layer

115,116,117 contact pad

120:

121 masking layer

122 insulating layer

123 conductive layer

Z1 routing area

Z2. Grounding region

Z3 pin area

Detailed Description

Various embodiments of the present disclosure are disclosed in the following figures, in which numerous practical details are set forth in the following description for purposes of clarity. However, it should be understood that these practical details are not to be used to limit the present disclosure. That is, in some embodiments of the present disclosure, these practical details are not necessary. Furthermore, for the sake of simplicity of the drawing, some conventional structures and elements are shown in the accompanying drawings in a simplified schematic manner.

Referring to fig. 1, a schematic cross-sectional view of an electronic device 100 according to an embodiment of the disclosure is shown. As shown in fig. 1, in the present embodiment, the electronic device 100 includes a circuit board 110 and a shielding member 120. The circuit board 110 includes a base layer 111, a circuit layer 112, a bonding layer 113 and a cover layer 114, and in particular, the circuit board 110 may be a flexible circuit board or a flexible circuit board. The circuit layer 112 is disposed on the base layer 111. The cover layer 114 is adhered to the circuit layer 112 via the adhesion layer 113. The shielding member 120 is located on one side of the circuit board 110, and includes a shielding layer 121, an insulating layer 122, and a conductive layer 123. The insulating layer 122 is located on a side of the shielding layer 121 away from the circuit board 110. The conductive layer 123 is located on a side of the shielding layer 121 near the circuit board 110 (i.e., between the circuit board 110 and the shielding layer 121), and is attached to the cover layer 114. The shielding member 120 is used for protecting the circuit layer 112 of the circuit board 110 from electromagnetic interference (Electromagnetic Interference, EMI) to avoid malfunction when the circuit board 110 is in the vicinity of the rf spectrum electromagnetic field generated by another electronic device.

In some embodiments, the material of the circuit layer 112 includes copper, but the disclosure is not limited thereto.

In some embodiments, the material of the cover 114 comprises plastic. For example, the plastic includes Polyimide (PI), but the disclosure is not limited thereto.

Referring to fig. 2, a schematic diagram of a circuit board 110 according to an embodiment of the disclosure is shown. As shown in fig. 1 and 2, in the present embodiment, the circuit board 110 includes a trace region Z1 and a ground region Z2 located at two opposite sides of the trace region Z1. The shielding layer 121 is electrically connected to the ground region Z2. Further, the electronic device 100 further includes test pins 112c1,112d 1. The test pins 112c1 and 112d1 are disposed on the circuit board 110 and electrically connected to the shielding layer 121. The inspector can use the open/short circuit inspection apparatus to inspect the on-resistance of the test pins 112c1,112d1 to confirm the conductivity between the shielding member 120 and the grounding area Z2 of the circuit board 110, so as to effectively solve the problem of the appearance damage of the circuit board 110 caused by the conventional destructive inspection method.

Referring to fig. 3, a schematic diagram of a circuit layer 112 of a circuit board 110 according to an embodiment of the disclosure is shown. As shown in fig. 3, in the present embodiment, the circuit layer 112 of the circuit board 110 includes a signal circuit 112a, a ground circuit 112b, and test circuits 112c and 112d. The signal line 112a is located in the trace zone Z1. The ground line 112b and the test lines 112c,112d are located in the ground zone Z2. The ground line 112b is electrically isolated from the test lines 112c,112d in the line layer 112. Specifically, the ground line 112b is separated from the test lines 112c,112d in the line layer 112 without direct contact.

In the present embodiment, the test lines 112c and 112d are surrounded by the ground line 112b, but the disclosure is not limited thereto.

As shown in fig. 2, the circuit board 110 further includes a pin zone Z3. The pin zone Z3 is located on the same side of the routing zone Z1 and the grounding zone Z2. The end of the signal line 112a has a signal pin 112a1 located in the pin zone Z3. The end of the grounding line 112b has a grounding pin 112b1 located in the pin zone Z3. The ends of the test lines 112c,112d have test pins 112c1,112d1, respectively, located in the pin zone Z3.

As shown in fig. 2 and 3, in the present embodiment, the circuit board 110 further includes contact pads 115,116 (shown in dashed lines in fig. 3). The contact pad 115 is located at the grounding region Z2 and electrically contacts the test circuit 112c and the shielding layer 121. The contact pad 116 is located at the grounding region Z2 and electrically contacts the test line 112d and the shielding layer 121. In other words, the contact pads 115 and 116 are in contact with the shielding layer 121 through the adhesion layer 113, the cover layer 114 and the conductive layer 123. Therefore, the inspector can use the open/short circuit inspection apparatus to inspect the on-resistance of the test pins 112c1,112d1 to confirm the conductivity between the shielding member 120 and the grounding area Z2 of the circuit board 110, so as to effectively solve the problem of the appearance damage of the circuit board 110 caused by the conventional destructive inspection method.

It should be noted that, although in the embodiment shown in fig. 3, the trace region Z1 is located between the grounding regions Z2 (i.e. the grounding regions Z2 are located at two sides of the trace region Z1), the disclosure is not limited thereto. In practical applications, the grounding region Z2 may also be located between the routing regions Z1 (i.e., the routing regions Z1 are located at two sides of the grounding region Z2).

Referring to fig. 4, a schematic diagram of a circuit layer 212 of a circuit board 110 according to another embodiment of the disclosure is shown. As shown in fig. 4, the present embodiment is modified with respect to the wiring layer 112 shown in fig. 3, and a modified wiring layer 212 is provided. In detail, the circuit layer 212 of the present embodiment eliminates the test circuit 112d and the contact pad 116 contacting the test circuit 112d in the circuit layer 112, and provides a modified grounding circuit 212b. In addition, the circuit board 110 further includes contact pads 117 (shown in phantom in fig. 4). The contact pad 117 is located in the grounding region Z2 and electrically contacts the grounding line 212b and the shielding layer 121 (please refer to fig. 1). In other words, the contact pad 117 passes through the adhesive layer 113, the cover layer 114 and the conductive layer 123 to contact the shielding layer 121. Therefore, the inspector can also use the open/short circuit inspection apparatus to inspect the on-resistance of the test pin 112c1 and the ground pin 212b1 of the ground line 212b to confirm the conductivity between the shielding member 120 and the ground area Z2 of the circuit board 110, so as to effectively solve the problem of the appearance breakage of the circuit board 110 caused by the conventional destructive inspection method.

As is apparent from the above description of the embodiments of the present disclosure, in the electronic device of the present disclosure, the shielding layer of the shielding member is electrically connected to the test pins disposed on the circuit board. Therefore, a detector can use the open circuit/short circuit detector to detect the conduction resistance of the test pin to confirm the conduction between the shielding piece and the grounding area of the circuit board, so that the problem of the appearance damage of the circuit board caused by the conventional destructive detection mode can be effectively solved.

While the present disclosure has been described with reference to the exemplary embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and it is therefore intended that the scope of the disclosure be limited only by the appended claims.

Claims

1. An electronic device, comprising:

a circuit board including a grounding region;

the shielding piece is positioned on one side of the circuit board and comprises a shielding layer and an insulating layer, wherein the shielding layer is electrically connected to the grounding area, and the insulating layer is positioned on one side of the shielding layer away from the circuit board; and

a test pin disposed on the circuit board and electrically connected to the shielding layer.

2. The electronic device of claim 1, wherein the circuit board further comprises a pin area, and the test pin is located in the pin area.

3. The electronic device of claim 1, wherein the shield further comprises a conductive layer, and wherein the conductive layer is located between the circuit board and the shield.

4. The electronic device of claim 1, wherein the circuit board further comprises a circuit layer, the circuit layer comprises a test circuit, and the test pin is located at an end of the test circuit.

5. The electronic device of claim 4, wherein the test circuit is located in the ground region.

6. The electronic device of claim 4, wherein the circuit board further comprises a contact pad, wherein the contact pad is located at the grounding region and electrically contacts the test circuit and the shielding layer.

7. The electronic device of claim 4, wherein the circuit layer further comprises a ground circuit, the ground circuit being electrically isolated from the test circuit in the circuit layer.

8. The electronic device of claim 7, wherein the circuit board further comprises a pin area, the ground circuit has a ground pin located in the pin area, and the ground pin is electrically connected to the shielding layer.

9. The electronic device of claim 8, wherein the circuit board further comprises a contact pad disposed at the grounding region and electrically contacting the grounding trace and the shielding layer.

10. The electronic device of claim 1, further comprising another test pin, wherein the other test pin is electrically connected to the shielding layer.

11. The electronic device of claim 10, wherein the circuit board further comprises a pin area, and the other test pin is located in the pin area.

12. The electronic device of claim 11, wherein the circuit board further comprises a circuit layer, the circuit layer comprises a test circuit, and the other test pin is located at an end of the test circuit.