CN116961670A - Method, device and application for generating ADC master clock based on constant temperature crystal oscillator - Google Patents
Method, device and application for generating ADC master clock based on constant temperature crystal oscillator Download PDFInfo
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Abstract
The invention relates to the technical field of analog-to-digital conversion, and discloses a method for generating an ADC main clock based on a constant-temperature crystal oscillator, which comprises the following steps: s3, the master control FPGA multiplies the frequency of the externally hung constant-temperature crystal oscillator; s4, after the frequency multiplication is executed, the frequency division module is used for dividing the frequency after the frequency multiplication, the frequency after the frequency division is output to the sigma-delta ADC through a main clock input pin, and the frequency after the frequency division is used as a main clock of the sigma-delta ADC. The clock multiplexing method saves the cost of the main clock of the ADC, improves the precision of the main clock of the sigma-delta ADC by one grade after using the domesticated clock, obviously improves the data stability and precision of the sigma-delta ADC, saves the economic cost for the digital transformation and operation of a national power grid when applied to the online detection of wide-area high-voltage transformers of high-voltage power stations and power plants, and improves the stability and reliability of the data.
Description
Technical Field
The invention relates to the technical field of analog-to-digital conversion, in particular to a method, a device and application for generating an ADC main clock based on a constant-temperature crystal oscillator.
Background
Along with the construction of smart power grids, more and more intelligent terminal devices are applied to high-voltage power plants or power stations, such as merging units or high-voltage transformer digital acquisition devices, and the like, and the devices mainly acquire, analyze, measure, control and the like analog signals input by the front end, most of the devices adopt a high-precision analog-to-digital conversion module (hereinafter referred to as an ADC module), a constant-temperature crystal oscillator, the ADC module is mainly used for performing analog-to-digital conversion on the input signals of the front end, and the constant-temperature crystal oscillator is mainly used for performing high-precision synchronous sampling and time keeping functions, and the functional block diagram of the existing product is shown in the following figure 1.
In order to quickly and real-timely collect signals at the front end and reduce the time delay of front end collection, a field programmable gate array (hereinafter referred to as FPGA) is generally adopted as a main control, meanwhile, in order to realize high-precision synchronous collection and time keeping functions, a constant-temperature crystal oscillator is arranged in the device, the constant-temperature crystal oscillator is tamed by combining an externally input second pulse (hereinafter referred to as PPS) signal, a high-precision clock frequency is generated, the tamed clock frequency is divided into a certain frequency, such as 4K or 12.K frequency, the frequency after frequency division is utilized to serve as a conversion trigger pin (CONVST) of an ADC, high-precision synchronous sampling can be realized, and when the external time-setting signal is lost, the time keeping function in a period of time can be realized by utilizing the high-stability characteristic of the constant-temperature crystal oscillator.
However, each ADC master clock is provided by an externally-hung clock crystal oscillator (generally, a temperature compensation crystal oscillator) and when a product has multiple ADCs, the multiple ADC master clock crystal oscillators will bring about the increase of product cost and complexity of design, and meanwhile, the externally-hung clock crystal oscillators have different error characteristics, so that the synchronization of the clocks is also error when the multiple ADCs work simultaneously.
Disclosure of Invention
The present invention is directed to a method, an apparatus and an application for generating an ADC master clock based on a constant temperature crystal oscillator, and a computer readable storage medium for solving the above-mentioned problems in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions: a method for generating an ADC master clock based on a thermostatic crystal oscillator, comprising a master FPGA and at least one sigma-delta ADC, comprising:
the input end of the master control FPGA is connected with an FPGA main clock, an externally hung constant-temperature crystal oscillator and a PPS input signal, the PPS input signal is a second pulse signal, and the master control FPGA comprises a frequency division module;
the sigma-delta ADC is not externally hung with a clock crystal oscillator, the sigma-delta ADC is in communication connection with the master control FPGA through an SPI interface, and a master clock input pin and a synchronous signal trigger pin of the sigma-delta ADC respectively receive a master clock signal and a synchronous signal trigger signal from the master control FPGA;
the method comprises the following steps:
s3, the master control FPGA multiplies the frequency of the externally hung constant-temperature crystal oscillator;
s4, after the frequency multiplication is executed, the frequency division module is used for dividing the frequency after the frequency multiplication, the frequency after the frequency division is output to the sigma-delta ADC through a main clock input pin, and the frequency after the frequency division is used as a main clock of the sigma-delta ADC.
Preferably, the step S3 further includes performing taming on the externally hung constant-temperature crystal oscillator in combination with the PPS input signal, and dividing the tamed frequency to obtain a frequency after high-precision frequency division.
Preferably, the step S3 further includes multiplying the clock frequency of the oven controlled crystal oscillator to 200MHZ, and using the rising edge signal of the PPS input signal output by the PPS monitoring unit module to tame the clock of the oven controlled crystal oscillator.
Preferably, before said step S3, step S2 is further included: the PPS input signal is continuously monitored by a PPS acquisition unit, and when the PPS signal arrives, the PPS acquisition unit outputs the rising edge signal of the PPS input signal.
Preferably, before said step S2, step S1 is further included: and initializing an FPGA main clock configuration, a GPIO configuration and a constant-temperature crystal oscillator of the main control FPGA.
Preferably, after the step S4, step S5 is further included: the main control FPGA controls the working mode and the sampling rate of the sigma-delta ADC through an SPI bus, and acquires digital signals through data output ports D0, D1 and D2 of the sigma-delta ADC;
after the step S5, the method further includes a step S6: and after the digital processing unit is used for receiving the digital signals, the digital signals are operated, and then the digital signals are sent to other terminals according to a protocol which is packed into a standard by a stipulation.
The invention also provides an analog-to-digital conversion device of the method for generating the ADC main clock based on the constant temperature crystal oscillator according to the description, the analog-to-digital conversion device at least comprises a main control FPGA and at least one sigma-delta ADC, the input end of the main control FPGA is connected with the FPGA main clock, the externally hung constant temperature crystal oscillator and a PPS input signal, the PPS input signal is a second pulse signal, and the main control FPGA comprises a frequency division module;
the sigma-delta ADC is not externally hung with a clock crystal oscillator, the sigma-delta ADC is in communication connection with the master control FPGA through an SPI interface, and a master clock input pin and a synchronous signal trigger pin of the sigma-delta ADC respectively receive a master clock signal and a synchronous signal trigger signal from the master control FPGA;
the master FPGA is further configured to: and multiplying the frequency of the externally hung constant-temperature crystal oscillator, after executing the frequency multiplication, using the frequency division module to divide the frequency after frequency multiplication, outputting the frequency after frequency division to the sigma-delta ADC through a main clock input pin, and taking the frequency after frequency division as a main clock of the sigma-delta ADC.
Preferably, the master FPGA is further configured to: continuously monitoring the PPS input signal by using a PPS acquisition unit, and outputting the rising edge signal of the PPS input signal by the PPS acquisition unit when the PPS signal arrives; the externally hung constant-temperature crystal oscillator is tamed by combining the PPS input signal, and the tamed frequency is divided to obtain a frequency after high-precision frequency division; doubling the clock frequency of the constant-temperature crystal oscillator to 200MHz, and using the rising edge signal of the PPS input signal output by the PPS monitoring unit module to tame the clock of the constant-temperature crystal oscillator; controlling the working mode and the sampling rate of the sigma-delta ADC through an SPI bus, and acquiring digital signals through data output ports D0, D1 and D2 of the sigma-delta ADC; and after the digital processing unit is used for receiving the digital signals, the digital signals are operated, and then the digital signals are sent to other terminals according to a protocol which is packed into a standard by a stipulation.
The invention also provides an application of the method for generating the ADC master clock based on the constant-temperature crystal oscillator in online detection of the wide-area high-voltage transformer of the high-voltage power station.
The present invention also provides a computer-readable storage medium having stored therein instructions for causing a computer to perform operations included in the method of generating an ADC master clock based on a thermostatic crystal oscillator according to the foregoing description.
The invention has the technical effects and advantages that:
the clock multiplexing method not only saves the cost of the main clock (temperature compensation crystal oscillator) of the ADC, but also improves the precision of the main clock of the sigma-delta ADC by one level after using the domesticated clock, so that the data stability and the precision of the sigma-delta ADC are obviously improved.
The technical scheme of the invention is applied to online detection of wide-area high-voltage transformers of high-voltage power stations and power plants, saves economic cost for digital transformation and operation of national power grids, and improves stability and reliability of data.
Drawings
Fig. 1 is a schematic diagram of an ADC module in the prior art.
FIG. 2 is a schematic diagram of a sigma-delta ADC module according to the present invention.
FIG. 3 is a schematic diagram of the functional blocks of the sigma-delta ADC module of the present invention.
FIG. 4 is a flow chart of a method of generating an ADC master clock based on a constant temperature crystal oscillator according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 2-4, the analog-to-digital conversion device comprises a master FPGA and at least one sigma-delta ADC, wherein the input end of the master FPGA is connected with an FPGA master clock, an externally hung constant-temperature crystal oscillator and a PPS input signal, the PPS input signal is a second pulse signal, the master FPGA comprises a frequency division module, the sigma-delta ADC is not externally hung with the clock crystal oscillator, the sigma-delta ADC is in communication connection with the master FPGA through an SPI interface, and the master clock input pin and the synchronizing signal trigger pin of the sigma-delta ADC receive the master clock signal and the synchronizing signal trigger signal from the master FPGA respectively. In order to solve the problems that after a product has a plurality of sigma-delta type ADCs, a plurality of sigma-delta type ADCs master clock oscillators bring about rising of product cost and complexity of design, a high-precision clock is tamed based on a constant temperature crystal oscillator, and a proper frequency is divided for a front-end sigma-delta type ADC module to be used, so that the clock oscillator hung outside the sigma-delta type ADCs is omitted, a method for generating the sigma-delta type ADC master clock based on the constant temperature crystal oscillator is provided, and the method comprises the following steps: s3, the master control FPGA multiplies the frequency of the externally hung constant-temperature crystal oscillator; s4, after the frequency multiplication is executed, the frequency division module is used for dividing the frequency after the frequency multiplication, the frequency after the frequency division is output to the sigma-delta ADC through a main clock input pin, and the frequency after the frequency division is used as a main clock of the sigma-delta ADC. Through the scheme, the sigma-delta ADC and the main control FPGA multiplex the externally hung constant-temperature crystal oscillator frequency, so that the externally hung clock crystal oscillator of the ADC is omitted, the economic cost is saved for the digital transformation and operation of a national power grid, and the stability and the reliability of data are improved.
Further, the step S3 further includes performing taming on the externally hung oven controlled oscillator in combination with the PPS input signal, and dividing the tamed frequency to obtain a frequency after frequency division with high accuracy, for example, the frequency obtained after frequency division is 8.192MHZ (the frequency commonly used in sigma-delta ADC). After the frequency division is carried out by using the domesticated clock, the precision of the main clock of the sigma-delta ADC is improved by one level, so that the data stability and the precision of the sigma-delta ADC are also obviously improved, the economic cost is saved for the digital transformation and operation of a national power grid, and the stability and the reliability of the data are improved.
Further, the step S3 further includes multiplying the clock frequency of the thermostatic crystal oscillator to 200MHZ, and using the rising edge signal of the PPS input signal output by the PPS monitoring unit module to tame the clock of the thermostatic crystal oscillator. Further improving the data stability and accuracy of the sigma-delta ADC.
Further, before the step S3, the method further includes a step S2: the PPS input signal is continuously monitored by a PPS acquisition unit, and when the PPS signal arrives, the PPS acquisition unit outputs the rising edge signal of the PPS input signal. Further improving the data stability and accuracy of the sigma-delta ADC.
Further, before the step S2, the method further includes a step S1: and initializing the FPGA main clock configuration, the GPIO configuration and the constant-temperature crystal oscillator of the main control FPGA, so that the stability and the precision of the sigma-delta ADC main clock are improved.
Further, after the step S4, the method further includes a step S5: the main control FPGA controls the working mode and the sampling rate of the sigma-delta ADC through an SPI bus, and acquires digital signals through data output ports D0, D1 and D2 of the sigma-delta ADC; after the step S5, the method further includes a step S6: and after the digital processing unit is used for receiving the digital signals, the digital signals are operated, and then the digital signals are sent to other terminals according to a protocol which is packed into a standard by a stipulation.
The invention also provides an analog-to-digital conversion device of the method for generating the ADC main clock based on the constant temperature crystal oscillator according to the description, as shown in figures 2 and 3, the analog-to-digital conversion device at least comprises a main control FPGA and at least one sigma-delta ADC, the main control FPGA mainly comprises 6 control units and consists of a system initialization unit, a PPS acquisition unit, a clock taming unit, a clock frequency division unit, an ADC acquisition unit and a data processing unit, the structure and the working schematic diagram are shown in figure 3, the input end of the main control FPGA is connected with the FPGA main clock, the externally hung constant temperature crystal oscillator and a PPS input signal, the PPS input signal is a pulse per second signal, and the main control FPGA comprises a frequency division module; the sigma-delta ADC is not externally hung with a clock crystal oscillator, the sigma-delta ADC is in communication connection with the master control FPGA through an SPI interface, and a master clock input pin and a synchronous signal trigger pin of the sigma-delta ADC respectively receive a master clock signal and a synchronous signal trigger signal from the master control FPGA; the master FPGA is further configured to: and multiplying the frequency of the externally hung constant-temperature crystal oscillator, after executing the frequency multiplication, using the frequency division module to divide the frequency after frequency multiplication, outputting the frequency after frequency division to the sigma-delta ADC through a main clock input pin, and taking the frequency after frequency division as a main clock of the sigma-delta ADC. The analog-digital conversion device of the invention realizes the multiplexing of the external constant-temperature crystal oscillator frequency of the sigma-delta ADC and the main control FPGA, thereby saving the external clock crystal oscillator of the ADC, saving economic cost for the digital transformation and operation of the national power grid, improving the stability and reliability of data, improving the precision of the main clock of the sigma-delta ADC by one grade after frequency division by using the domesticated clock, obviously improving the data stability and precision of the sigma-delta ADC, saving economic cost for the digital transformation and operation of the national power grid, and improving the stability and reliability of data.
Furthermore, the embodiment of the main control FPGA adopts 24 bit Sigema-Delta ADC AD 7779 of an ANALOG company, the chip supports an 8-channel 24-bit ADC, the main control adopts a field programmable gate array (hereinafter referred to as FPGA), the Xczu3eg of xlix is adopted between the main control and the ADC, an SPI communication interface is adopted between the main control and the ADC, an interface is configured for a sigma-Delta ADC register, D0-D3 is a data output port after the ADC is converted into a digital signal in an ANALOG manner, SYNC is a synchronous signal trigger signal of the ADC, after SYNC is electrified once, the sigma-Delta ADC can be sampled according to the frequency which is initially set, the MCLK is the main clock of the ADC, and SYNC and MCLK signals are output by the FPGA. The FPGA is externally connected with a second pulse input signal, the PPS can be utilized to tame the constant-temperature crystal oscillator, the main clock of the FPGA in the embodiment of the invention adopts 200MHz, and the clock of the constant-temperature crystal oscillator adopts 20 MHz. After the device or the system is powered on, a system initialization unit mainly completes initialization of the FPGA system, and the unit comprises configuration of an FPGA main clock, configuration of GPIO, initial configuration of a constant-temperature crystal oscillator and the like, and the device or the system is not limited to the initialization of the modules; after the system initialization is finished, the PPS acquisition unit continuously monitors PPS pulse input signals, and when the PPS signals arrive, the PPS rising edge signals are output and synchronously output to the clock taming unit, the clock frequency dividing unit and the ADC acquisition unit for use; the clock taming unit is used for firstly doubling the clock frequency of the constant-temperature crystal oscillator to 200MHz, taming the clock of the constant-temperature crystal oscillator by using a PPS rising edge signal output by the PPS monitoring unit module, and the clock frequency error after taming can be at the nanosecond level; the clock frequency dividing unit is used for dividing the frequency of the clock which is domesticated by the clock domesticating unit through a frequency dividing algorithm, and the frequency of the clock is divided into 8.192MHz by the domesticated frequency, and then the 8.192MHz frequency is transmitted to a sigma-delta ADC master clock pin, namely a pin through MCLK; the ADC acquisition unit mainly controls the working mode and the sampling rate of the ADC through an SPI bus, the sampling rate of the invention is set to be 4K, and then the data output by the ADC module is acquired through D0-D3 signals; the digital processing unit is mainly used for processing the digital signals sent by the ADC module, namely, carrying out operation on the digital signals of D0-D3, and then sending the digital signals to other terminals according to a protocol which is packed into a standard according to a rule.
Further, the master FPGA is further configured to: continuously monitoring the PPS input signal by using a PPS acquisition unit, and outputting the rising edge signal of the PPS input signal by the PPS acquisition unit when the PPS signal arrives; the externally hung constant-temperature crystal oscillator is tamed by combining the PPS input signal, and the tamed frequency is divided to obtain a frequency after high-precision frequency division; doubling the clock frequency of the constant-temperature crystal oscillator to 200MHz, and using the rising edge signal of the PPS input signal output by the PPS monitoring unit module to tame the clock of the constant-temperature crystal oscillator; controlling the working mode and the sampling rate of the sigma-delta ADC through an SPI bus, and acquiring digital signals through data output ports D0, D1 and D2 of the sigma-delta ADC; and after the digital processing unit is used for receiving the digital signals, the digital signals are operated, and then the digital signals are sent to other terminals according to a protocol which is packed into a standard by a stipulation. The data stability and the precision of the sigma-delta ADC are obviously improved by the scheme, the economic cost is saved for the digital transformation and operation of the national power grid, and the stability and the reliability of the data are improved.
The invention also applies to the on-line detection of a wide area high voltage transformer of a high voltage power station by a method for generating an ADC master clock based on a constant temperature crystal oscillator according to the description. In the online detection project of the wide-area high-voltage transformer of the high-voltage power station and the power plant, the invention not only saves the cost of the main clock (temperature compensation crystal oscillator) of the ADC, but also improves the accuracy of the main clock of the ADC by one grade after the domesticated clock, so that the data stability and the accuracy of the ADC are obviously improved, the economic cost is saved for the digital transformation and operation of the national power grid, and the stability and the reliability of the data are improved.
The present invention provides a computer-readable storage medium having stored therein instructions for causing a computer to perform operations included in the method of generating an ADC master clock based on a thermostatic crystal oscillator according to the foregoing description.
Finally, it should be noted that: the foregoing description of the preferred embodiments of the present invention is not intended to be limiting, but rather, it will be apparent to those skilled in the art that the foregoing description of the preferred embodiments of the present invention can be modified or equivalents can be substituted for some of the features thereof, and any modification, equivalent substitution, improvement or the like that is within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for generating an ADC master clock based on a thermostatic crystal oscillator, comprising a master FPGA and at least one sigma-delta ADC, comprising:
the input end of the master control FPGA is connected with an FPGA main clock, an externally hung constant-temperature crystal oscillator and a PPS input signal, the PPS input signal is a second pulse signal, and the master control FPGA comprises a frequency division module;
the sigma-delta ADC is not externally hung with a clock crystal oscillator, the sigma-delta ADC is in communication connection with the master control FPGA through an SPI interface, data are connected through D0-D3, and a master clock input pin and a synchronous signal trigger pin of the sigma-delta ADC respectively receive a master clock signal and a synchronous signal trigger signal from the master control FPGA;
the method comprises the following steps:
s3, the master control FPGA multiplies the frequency of the externally hung constant-temperature crystal oscillator;
s4, after the frequency multiplication is executed, the frequency division module is used for dividing the frequency after the frequency multiplication, the frequency after the frequency division is output to the sigma-delta ADC through a main clock pin MCLK, and the frequency after the frequency division is used as a main clock of the sigma-delta ADC.
2. The method of claim 1, wherein step S3 further comprises performing taming on the external thermostat oscillator in combination with the PPS input signal, and dividing the tamed frequency to obtain a frequency with high precision after frequency division.
3. The method of claim 1, wherein step S3 further comprises multiplying the clock frequency of the oven controlled crystal to 200MHZ, and using the rising edge signal of the PPS input signal outputted from the PPS monitoring unit module to tame the clock of the oven controlled crystal.
4. A method of generating an ADC master clock based on a thermostatic crystal oscillator according to claim 3, further comprising step S2, prior to said step S3: the PPS input signal is continuously monitored by a PPS acquisition unit, and when the PPS signal arrives, the PPS acquisition unit outputs the rising edge signal of the PPS input signal.
5. The method for generating an ADC master clock based on a thermostatic crystal oscillator according to claim 4, further comprising step S1, before said step S2: and initializing an FPGA main clock configuration, a GPIO configuration and a constant-temperature crystal oscillator of the main control FPGA.
6. The method for generating an ADC master clock based on a thermostatic crystal oscillator according to claim 1, further comprising step S5 after said step S4: the main control FPGA controls the working mode and the sampling rate of the sigma-delta ADC through an SPI bus, and acquires digital signals through data output ports D0, D1 and D2 of the sigma-delta ADC;
after the step S5, the method further includes a step S6: and after the digital processing unit is used for receiving the digital signals, the digital signals are operated, and then the digital signals are sent to other terminals according to a protocol which is packed into a standard by a stipulation.
7. An analog-to-digital conversion device of the method for generating an ADC main clock based on a thermostatic crystal oscillator according to any one of claims 1-6, the analog-to-digital conversion device at least comprising a master FPGA and at least one sigma-delta ADC, the input of the master FPGA being connected to the FPGA main clock, the thermostatic crystal oscillator being externally hung, and PPS input signals, the PPS input signals being pulse-per-second signals, the master FPGA comprising a frequency dividing module;
the sigma-delta ADC is not externally hung with a clock crystal oscillator, the sigma-delta ADC is in communication connection with the master control FPGA through an SPI interface, and a master clock input pin and a synchronous signal trigger pin of the sigma-delta ADC respectively receive a master clock signal and a synchronous signal trigger signal from the master control FPGA;
the master FPGA is further configured to: and multiplying the frequency of the externally hung constant-temperature crystal oscillator, after executing the frequency multiplication, using the frequency division module to divide the frequency after frequency multiplication, outputting the frequency after frequency division to the sigma-delta ADC through a main clock input pin, and taking the frequency after frequency division as a main clock of the sigma-delta ADC.
8. The analog-to-digital conversion apparatus of claim 7, wherein the master FPGA is further configured to:
continuously monitoring the PPS input signal by using a PPS acquisition unit, and outputting the rising edge signal of the PPS input signal by the PPS acquisition unit when the PPS signal arrives;
the externally hung constant-temperature crystal oscillator is tamed by combining the PPS input signal, and the tamed frequency is divided to obtain high-precision frequency required by sigma-delta;
doubling the clock frequency of the constant-temperature crystal oscillator to 200MHz, and using the rising edge signal of the PPS input signal output by the PPS monitoring unit module to tame the clock of the constant-temperature crystal oscillator;
controlling the working mode and the sampling rate of the sigma-delta ADC through an SPI bus, and acquiring digital signals through data output ports D0, D1 and D2 of the sigma-delta ADC;
and after the digital processing unit is used for receiving the digital signals, the digital signals are operated, and then the digital signals are sent to other terminals according to a protocol which is packed into a standard by a stipulation.
9. Use of a method of generating an ADC master clock based on a thermostatic crystal oscillator according to any one of claims 1-6 in on-line detection of wide area high voltage transformers of a high voltage power station.
10. A computer-readable storage medium having stored therein instructions for causing a computer to perform the operations included in the method of generating an ADC master clock based on a thermostatic crystal oscillator according to any one of claims 1 to 6.
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