CN114994104A

CN114994104A - CT detector module and data acquisition method

Info

Publication number: CN114994104A
Application number: CN202210593824.9A
Authority: CN
Inventors: 陈修儒; 倪健; 朱炯
Original assignee: Minfound Medical Systems Co Ltd
Current assignee: Minfound Medical Systems Co Ltd
Priority date: 2022-05-27
Filing date: 2022-05-27
Publication date: 2022-09-02

Abstract

The invention provides a CT detector module and a data acquisition method, wherein the CT detector module comprises an FPGA chip and an ADC chip, and a pin group of the FPGA chip comprises the following pins: the MCLK pin transmits a main clock signal to the ADC chip; the CONV pin sends an overturning signal to the ADC chip; the ADC chip sends a driving clock signal to the FPGA chip; data pin, ADC chip sends the Data package to the FPGA chip, and the Data package includes: the packet header is set by the FPGA chip and has initial information and highest-order information; data storing control information; when the FPGA chip detects that the information in the packet header is changed into the highest-order information, the driving clock signal received by the DCLK pin at the moment is recorded as the starting time, the starting time is used as the starting point, the holding time in the driving clock signal is used as the end point, and the data packet is received until the data packet is changed into the low level. After the technical scheme is adopted, the acquired data are stably output, and the image quality of the detector is improved.

Description

CT detector module and data acquisition method

Technical Field

The invention relates to the field of medical equipment, in particular to a CT detector module and a data acquisition method.

Background

With the use of CT nuclear medicine imaging equipment in various hospitals, the image-assisted examination of patients in hospitals is becoming more common.

At present, an ADC chip in a detector in CT nuclear medical imaging equipment controls an overturning signal to be triggered by adopting pulses, and the premise of stable sampling is that the sampling establishment time and the holding time of data are kept consistent. When the number of detectors is increased, the time for reaching the input pin of the FPGA chip is inconsistent although output is performed simultaneously due to inconsistent path delay from the ADC chip to the FPGA chip. In the case of a low sampling frequency, it is relatively easy to satisfy that the sample setup time and the hold time are kept the same, and thus data sampling can be performed stably. However, as the number of rows of detectors increases, the number of analog channels of a single ADC chip increases, and the amount of data converted per unit time and required to be output to the outside increases, so that the sampling frequency needs to be increased. With the increase of frequency, it is difficult to ensure that the above-mentioned requirement that the sampling setup time and the holding time are consistent, and the stability of data sampling cannot be ensured, and the finally obtained data generates artifacts.

Therefore, there is a need for a novel CT detector module and data acquisition method that can ensure stable sampling of data after frequency boosting

Disclosure of Invention

In order to overcome the technical defects, the invention aims to provide a CT detector module and a data acquisition method, so that acquired data are stably output, and the image quality of a detector is improved.

The invention discloses a CT detector module, which comprises an FPGA chip and at least one ADC chip electrically connected with the FPGA chip through a pin group of the FPGA chip, wherein the ADC chip receives analog output of a plurality of pixel arrays, and the pin group of the FPGA chip comprises the following pins:

the MCLK pin transmits a main clock signal to the ADC chip;

the CONV pin sends an overturning signal to the ADC chip so as to control the sampling frequency of the ADC chip;

the ADC chip sends a driving clock signal to the FPGA chip through the DCLK pin;

the Data pin, the ADC chip sends the Data package to the FPGA chip through the Data pin, and wherein the Data package includes:

the packet header is set by the FPGA chip and has initial information and highest-order information;

data storing control information;

when the FPGA chip detects that the information in the packet header is changed into the highest-order information, the driving clock signal received by the DCLK pin at the moment is recorded as the starting time, the starting time is used as the starting point, the holding time in the driving clock signal is used as the end point, and the data packet is received until the data packet is changed into the low level.

Preferably, the start information is 0, and the most significant bit information is 1;

and when the FPGA chip sends an overturning signal through the CONV pin, the ADC chip resets the internal sampling circuit.

Preferably, the channel bit number of each sampling channel is preset in the FPGA chip;

when the FPGA chip collects a data packet in a sampling period from an initial moment to a holding moment, accumulating the digit by 1, and outputting parallelization data and effective signals to a rear-stage module connected with the FPGA chip when the digit accumulation number reaches a channel digit;

and when the parallel data of each sampling channel of the CT detector with the CT detector module are acquired, waiting for the data packet to be converted from the tri-state to the low level and cut off.

Preferably, a unified clock circuit is further arranged in the FPGA chip and is respectively connected with each ADC chip through a DCLK pin;

the unified clock circuit receives the DCLK clock domain of each ADC chip, and unifies all deserialized data and corresponding data effective signals to the unified clock domain after the clock domain passes through.

The invention also discloses a data acquisition method of the CT detector module, which comprises the following steps:

configuring a CT detector module which comprises an FPGA chip and at least one ADC chip electrically connected with the FPGA chip through a pin group of the FPGA chip, wherein the ADC chip receives analog output of a plurality of pixel arrays;

configuring pins of an FPGA chip, wherein a pin group of the FPGA chip consists of the following pins:

the MCLK pin transmits a main clock signal to the ADC chip;

the Data pin, ADC chip sends the Data package to the FPGA chip through the Data pin, and wherein the Data package includes:

data storing control information;

when the FPGA chip sends an overturning signal through the CONV pin, the ADC chip resets the internal sampling circuit.

and when the parallel data of each sampling channel of the CT detector with the CT detector module are completely acquired, waiting for the data packet to be converted from the tri-state to the low level and cut off.

the unified clock circuit receives the DCLK clock domain of each ADC chip, and unifies all deserialized data and corresponding data effective signals to the unified clock domain after clock domain crossing.

After the technical scheme is adopted, compared with the prior art, the method has the following beneficial effects:

1. the DVLD base pin of the FPGA chip is cancelled, and more redundant resources on the FPGA chip are released;

2. the sampling rate is improved and the cost is reduced;

3. the CT detector modules are synchronous in data acquisition, and the data acquisition process is stable.

Drawings

FIG. 1 is a schematic diagram of a CT detector module according to a preferred embodiment of the present invention;

FIG. 2 is a diagram illustrating a data collection relationship between a flip signal and a data packet in accordance with a preferred embodiment of the present invention;

FIG. 3 is a block diagram of a unified clock circuit according to a preferred embodiment of the present invention.

Detailed Description

The advantages of the invention are further illustrated in the following description of specific embodiments in conjunction with the accompanying drawings.

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are merely for convenience of description and simplicity of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.

In the description of the present invention, unless otherwise specified and limited, it should be noted that the terms "mounted," "connected," and "connected" are to be interpreted broadly, and may be, for example, a mechanical connection or an electrical connection, a communication between two elements, a direct connection, or an indirect connection through an intermediate medium, and those skilled in the art will understand the specific meaning of the terms as they are used in the specific case.

In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in themselves. Thus, "module" and "component" may be used in a mixture.

Referring to fig. 1, in order to synchronize the data sampling time of the ADC chip in each CT detector module, in this embodiment, the CT detector module includes an FPGA chip and an ADC chip, the FPGA chip is provided with a plurality of pins, which are integrated into a pin group (which may be physically integrated or independent from each other in practical application), each FPGA chip may be connected to a plurality of ADC chips, each ADC chip is connected to the FPGA chip through one pin group, and the other side of the ADC chip is connected to analog outputs of a plurality of pixel arrays, which are converted into digital signals by the ADC chip. The pixel array is a ray acquisition module, and is finally sent to an FPGA chip and further processed by a post-stage module. In the invention, a pin group of the FPGA chip consists of the following pins:

the MCLK pin, the signal transmission direction is from the FPGA chip to the ADC chip, and the FPGA chip sends a main clock signal to the ADC chip, namely the current time information stored in the FPGA chip.

And the CONV pin is used for transmitting signals from the FPGA chip to the ADC chip, the FPGA chip sends an overturning signal to the ADC chip and controls the sampling frequency of the ADC chip, namely after the FPGA chip sends the overturning signal through the CONV pin, the ADC chip converts channels of all pixel arrays connected to the ADC chip into digital data and serially outputs the digital data to the FPGA chip.

And the DCLK pin is used for transmitting signals from the ADC chip to the FPGA chip, and transmitting a driving clock signal to the FPGA chip by the ADC chip so as to drive the ADC chip to output a clock signal when data are output.

A Data pin, the signal transmission direction is from the ADC chip to the FPGA chip, and the main Data, i.e. the Data packet, sent by the ADC chip to the FPGA chip specifically includes: in the embodiment, the data in the packet header is set by the FPGA chip conversely (i.e. the FPGA chip is preset to accept only the data packet stored with the specific type of data), so that the packet header includes the start information and the highest order information, which respectively represent the type change (analogous to a level signal) of the data packet. Referring to fig. 2, after the start information and the highest-order information are set, data acquisition of the FPGA chip does not depend on a flip signal, but on the contrary, the received highest-order information is used as a reference, that is, when the FGPA chip detects that information in the packet header changes from the start information to the highest-order information, the driving clock signal received by the DCLK pin is started to be the start time, and the data packet is received by using the start time as a start point and using the holding time in the driving clock signal as an end point (that is, only in the period from the determined start time to the holding time) until the signal of the data packet is converted from tri-state to low level.

Through the configuration, even if the time of the driving clock signal and the Data packet which are respectively output to the FPGA chip by the DCLK pin and the Data pin is different, the turning signal which is not sent by the FPGA chip is no longer used as the sampling starting point in the FPGA chip, and on the contrary, the highest-order information in the packet header is used as the sampling starting point (even if some time is wasted, the highest-order information can be accepted), so that the establishment time and the holding time of the sampling Data are always the same. In addition, it can be understood that the establishment of the starting time in the FPGA chip can be independent of the highest-order information, and can also be any number from the starting information to the highest-order information.

On the other hand, compared with the prior art, the FPGA chip does not need to set a DVLD pin (i.e. a Data valid signal originally output by a Data packet accompanying the Data pin), in this embodiment, whether the Data is valid or not can be determined by using the start information and the highest order information in the packet header at the same time, that is, the start information and the highest order information are the same as the preset information, and the Data packet should be valid. That is, in this manner, pins of the FPGA chip are released (the number of the release pins is the same as that of the ADC chips), and the released pins can be used to mount more ADC chips for the FPGA chip.

In a preferred embodiment, the start information is defined as 0, the most significant bit information is defined as 1, and the FPGA chip can determine that the Data of the current flip signal starts to be output when detecting a change from 0 to 1 on the signal line of the Data pin, and then continuously acquire Data by using the DCLK pin. In addition, after the FPGA chip sends the turnover signal through the CONV pin, the ADC chip resets the internal sampling circuit, namely the data sampling action of the ADC chip is triggered by the turnover signal, but the data sampling action of the FPGA chip is not triggered automatically after being sent according to the turnover signal, but is triggered after the highest position information in the packet header is set to be 1, and the clocks of any data sampling action are synchronous.

Furthermore, the number of channel bits of each sampling channel is preset in the FGPA chip, that is, the number of ADC chips connected to the FPGA chip is preset in the FPGA chip, when the FPGA chip collects data packets in a sampling period from the start time to the hold time, 1 is added to the bit set in the FPGA chip every time a group of data packets are sampled in one sampling period, when the bit is accumulated to the channel bit, it indicates that the data of all pixel arrays of one ADC chip connected to the FPGA chip have been received completely, and the FPGA chip outputs parallelized data and effective signals to the back-stage module. When the parallel data of each sampling channel of the CT detector with the CT detector module is completely acquired (i.e., all ADC chips have sent all data packets to the FPGA chip), the sampling of the flip signal is completed after the data packet signal is converted from the tri-state (i.e., still in the state of high-low level change) to the low level.

Referring to fig. 3, further, a unified clock circuit is further disposed in the FPGA chip, the unified clock circuit is connected to each ADC chip through the DCLK pin, the unified clock circuit receives the DCLK clock domain of each ADC chip, and unifies all deserialized data and corresponding data valid signals into the unified clock domain after clock domain crossing, so that the clock domains of all ADC chips are the same.

The invention also discloses a data acquisition method of the CT detector module, which comprises the following steps: configuring a CT detector module which comprises an FPGA chip and at least one ADC chip electrically connected with the FPGA chip through a pin group of the FPGA chip, wherein the ADC chip receives analog output of a plurality of pixel arrays; configuring pins of an FPGA chip, wherein a pin group of the FPGA chip consists of the following pins: the MCLK pin transmits a main clock signal to the ADC chip; the CONV pin sends an overturning signal to the ADC chip so as to control the sampling frequency of the ADC chip; the ADC chip sends a driving clock signal to the FPGA chip through the DCLK pin; the Data pin, the ADC chip sends the Data package to the FPGA chip through the Data pin, and wherein the Data package includes: the packet header is set by an FPGA chip and has initial information and highest-order information; data storing control information; when the FPGA chip detects that the information in the packet header is changed into the highest-order information, the driving clock signal received by the DCLK pin at the moment is recorded as the starting time, the starting time is used as the starting point, the holding time in the driving clock signal is used as the end point, and the data packet is received until the data packet is changed into the low level.

Preferably, the start information is 0, and the most significant bit information is 1; and when the FPGA chip sends an overturning signal through the CONV pin, the ADC chip resets the internal sampling circuit.

Preferably, the channel bit number of each sampling channel is preset in the FPGA chip; when the FPGA chip collects a data packet in a sampling period from an initial moment to a holding moment, accumulating the digit by 1, and outputting parallelization data and effective signals to a rear-stage module connected with the FPGA chip when the digit accumulation number reaches a channel digit; and when the parallel data of each sampling channel of the CT detector with the CT detector module are completely acquired, waiting for the data packet to be converted from the tri-state to the low level and cut off.

Preferably, a unified clock circuit is further arranged in the FPGA chip and is respectively connected with each ADC chip through a DCLK pin; the unified clock circuit receives the DCLK clock domain of each ADC chip, and unifies all deserialized data and corresponding data effective signals to the unified clock domain after clock domain crossing.

It should be noted that the embodiments of the present invention have been described in terms of preferred embodiments, and not by way of limitation, and that those skilled in the art can make modifications and variations of the embodiments described above without departing from the spirit of the invention.

Claims

1. A CT detector module comprises an FPGA chip and at least one ADC chip electrically connected with the FPGA chip through a pin group of the FPGA chip, the ADC chip receives analog output of a plurality of pixel arrays,

the pin group of the FPGA chip consists of the following pins:

the MCLK pin transmits a main clock signal to the ADC chip;

a Data pin through which the ADC chip sends a Data packet to the FPGA chip, wherein the Data packet comprises:

data storing control information;

when the FPGA chip detects that the information in the packet header is changed into the highest-order information, the driving clock signal received by the DCLK pin at the moment is recorded as the starting time, and the data packet is received by taking the starting time as the starting point and the holding time in the driving clock signal as the end point until the data packet is converted into the low level.

2. The CT detector module of claim 1,

the initial information is 0, and the highest order information is 1;

3. The CT detector module of claim 2,

the FPGA chip is internally preset with channel bits of each sampling channel;

when the FPGA chip collects a data packet in a sampling period from an initial moment to a holding moment, accumulating 1 bit number, and outputting parallelization data and effective signals to a rear-stage module connected with the FPGA chip when the bit number accumulation number reaches a channel bit number;

and after the acquisition of the parallelization data of each sampling channel of the CT detector with the CT detector module is finished, waiting for the data packet to be converted from the tri-state to the low level and cut off.

4. The CT detector module of claim 3,

a unified clock circuit is also arranged in the FPGA chip and is respectively connected with each ADC chip through the DCLK pin;

5. A data acquisition method of a CT detector module is characterized by comprising the following steps:

the MCLK pin transmits a main clock signal to the ADC chip;

data storing control information;

when the FPGA chip detects that the information in the packet header is changed into the highest-order information, the driving clock signal received by the DCLK pin at the moment is recorded as the starting time, the starting time is used as the starting point, the holding time in the driving clock signal is used as the end point, and the data packet is received until the data packet is converted into the low level.

6. The data acquisition method of claim 5,

the initial information is 0, and the highest order information is 1;

7. The data acquisition method as set forth in claim 6,

the FPGA chip is internally preset with channel bits of each sampling channel;

8. The data acquisition method as set forth in claim 7,