CN116936684B - Method for simultaneously growing polycrystalline silicon with different thicknesses on front and back surfaces of battery and back contact battery - Google Patents
Method for simultaneously growing polycrystalline silicon with different thicknesses on front and back surfaces of battery and back contact battery Download PDFInfo
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- CN116936684B CN116936684B CN202311183441.5A CN202311183441A CN116936684B CN 116936684 B CN116936684 B CN 116936684B CN 202311183441 A CN202311183441 A CN 202311183441A CN 116936684 B CN116936684 B CN 116936684B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 145
- 238000000034 method Methods 0.000 title claims abstract description 69
- 229920005591 polysilicon Polymers 0.000 claims abstract description 108
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 104
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 104
- 239000010703 silicon Substances 0.000 claims abstract description 104
- 235000012431 wafers Nutrition 0.000 claims abstract description 101
- 238000009792 diffusion process Methods 0.000 claims abstract description 56
- 238000004140 cleaning Methods 0.000 claims abstract description 32
- 230000005641 tunneling Effects 0.000 claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 24
- 238000006243 chemical reaction Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 107
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 97
- 235000012239 silicon dioxide Nutrition 0.000 claims description 49
- 239000000377 silicon dioxide Substances 0.000 claims description 37
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 32
- 230000004888 barrier function Effects 0.000 claims description 32
- 229910052698 phosphorus Inorganic materials 0.000 claims description 32
- 239000011574 phosphorus Substances 0.000 claims description 32
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 28
- 239000007789 gas Substances 0.000 claims description 28
- 238000001816 cooling Methods 0.000 claims description 13
- 239000002253 acid Substances 0.000 claims description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 12
- 239000010453 quartz Substances 0.000 claims description 12
- 239000000654 additive Substances 0.000 claims description 11
- 230000000996 additive effect Effects 0.000 claims description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 claims description 8
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 6
- 239000012495 reaction gas Substances 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 2
- 239000000243 solution Substances 0.000 description 23
- 239000012670 alkaline solution Substances 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 238000011049 filling Methods 0.000 description 7
- 239000005360 phosphosilicate glass Substances 0.000 description 7
- 239000003513 alkali Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000011259 mixed solution Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013065 commercial product Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The invention belongs to the technical field of back contact battery preparation, and particularly relates to a method for simultaneously growing polycrystalline silicon with different thicknesses on the front side and the back side of a battery and the back contact battery, wherein the method comprises the following steps: s1, providing a silicon wafer with a polished back surface and a textured front surface; s2, controlling silicon wafers to be arranged in pairs at intervals and the front surfaces to face each other, wherein the distance between the front surfaces of the paired silicon wafers is S1, and the distance between the back surfaces of the front paired silicon wafers and the back surfaces of the adjacent back paired silicon wafers is S2; simultaneously forming tunneling oxide layers and intrinsic polycrystalline silicon on the front surface and the back surface of the silicon wafer, forming first intrinsic polycrystalline silicon with the thickness of L1 on the front surface, and forming second intrinsic polycrystalline silicon with the thickness of L2 on the back surface, wherein [ S1/(2×S2) ]+0.1 is less than or equal to L1/L2 is less than or equal to [ S1/(2×S2) ]+0.3; s3, doping by adopting a diffusion annealing process; s4, cleaning. The invention can realize simultaneous growth of polysilicon with different thicknesses on both sides, and simultaneously improve conductivity and battery conversion efficiency.
Description
Technical Field
The invention belongs to the technical field of back contact battery preparation, and particularly relates to a method for simultaneously growing polycrystalline silicon with different thicknesses on the front side and the back side of a battery and the back contact battery.
Background
The tunneling oxide layer and the polysilicon structure are applied to the front surface of the back contact heterojunction solar cell, and polysilicon with smaller thickness is required to be used for improving the current of the cell; while for use on the back side, it is necessary to use polysilicon having a relatively large thickness to improve conductivity.
The existing tunneling polycrystalline growth process mainly uses LPCVD to grow an oxide layer and a polycrystalline silicon layer and then carries out high-temperature diffusion, for example, a tunneling silicon oxide layer and an N-type doped polycrystalline silicon layer are formed on the front surface and the back surface of a silicon wafer at the same time. After the tunneling silicon oxide layer is formed on the two sides, the process of forming the N-type doped polysilicon layer comprises the following steps: firstly, depositing an undoped intrinsic silicon layer on the surface of a tunneling silicon oxide layer on the front side and the back side by LPCVD (low pressure chemical vapor deposition), wherein the thickness of the intrinsic silicon layer is 30nm; and plating phosphorus doped polysilicon on the back surface of the silicon wafer in an in-situ doping mode by adopting a PECVD mode. After the film plating process is finished, the silicon wafer is placed into a high-temperature phosphorus diffusion furnace for phosphorus diffusion, and in the phosphorus diffusion step, the silicon wafer is placed at equal intervals so as to ensure that the same PSG glass layers (phosphosilicate glass layers) are formed on both sides, and the phosphorus diffusion process is carried out at the same time. The PSG glass layer produced in the above step is then removed. It can be seen that the thickening of the back side polysilicon is currently generally achieved by way of an additional coating on the back side, so that its thickness is different from that of the front side polysilicon.
However, the existing LPCVD polysilicon deposition process cannot realize simultaneous growth of front and back surface polycrystalline with different thickness, and the existing high-temperature diffusion process cannot realize simultaneous diffusion of front and back surface polycrystalline with different thickness and different doping concentration.
Disclosure of Invention
The invention aims to overcome the defect that the existing LPCVD polysilicon deposition process in the prior art cannot realize simultaneous growth of the front and back sides with different thickness polysilicon, and provides a method for simultaneously growing the front and back sides with different thickness polysilicon of a battery and a back contact battery, wherein the method can realize simultaneous growth of the double-sided polysilicon with different thickness, and simultaneously can improve the short circuit current and the filling factor of the battery while improving the conductivity, thereby improving the conversion efficiency of the battery; because the structure that the front surface and the back surface are both tunneling oxide layers and polysilicon is formed simultaneously, the equipment cost is obviously reduced.
In order to achieve the above object, in a first aspect, the present invention provides a method for simultaneously growing polysilicon with different thicknesses on the front and back surfaces of a battery, comprising the steps of:
step S1, providing a silicon wafer with polished back and textured front;
s2, controlling silicon wafers to be arranged in pairs at intervals, wherein the front surfaces of the silicon wafers in pairs are arranged face to face, the distance between the front surfaces of the silicon wafers in pairs is S1, and the distance between the back surfaces of the silicon wafers in the previous pair and the back surfaces of the adjacent silicon wafers in the next pair is S2, wherein S2 is larger than S1; then simultaneously forming tunneling oxide layers on the front surface and the back surface of the silicon wafer, and then simultaneously forming intrinsic polycrystalline silicon on the front surface and the back surface, wherein the first intrinsic polycrystalline silicon is formed on the front surface and has a thickness L1 on the textured front surface, the second intrinsic polycrystalline silicon with a thickness L2 is formed on the back surface, and the L1, L2, S1 and S2 satisfy the following conditions: [ S1/(2×S2) ] +0.1.ltoreq.L1/L2.ltoreq.S 1/(2×S2) ] +0.3;
s3, forming a corresponding doped polysilicon layer by using a diffusion annealing process to enable the first intrinsic polysilicon and the second intrinsic polysilicon;
and S4, cleaning.
Preferably, L1 is 15-70nm, preferably 15-50nm, and L2 is 100-300nm.
Preferably, S1 is 1-5mm, preferably 2-5mm, S2 is 10-15mm.
Preferably, S2 is greater than S1.
In some preferred embodiments of the present invention, the tunnel oxide layer has a thickness of 1.2-2.0nm.
In some preferred embodiments of the present invention, the simultaneous formation of the tunnel oxide layer and the intrinsic polysilicon in step S2 is performed in a tube type LPCVD apparatus, and each silicon wafer is mounted on a quartz boat having a plurality of clamping grooves.
In some preferred embodiments of the present invention, in step S2, the conditions for forming the tunnel oxide layer include: thermal oxidation is carried out at 550-650 ℃.
In some preferred embodiments of the present invention, the conditions for forming intrinsic polysilicon include: the growth temperature is 550-650 ℃ and the air pressure is 5-10000Pa.
In some preferred embodiments of the present invention, the method further comprises the step of simultaneously forming polysilicon of different doping concentrations on the front and back surfaces:
in the step S3, firstly, a silicon dioxide barrier layer is formed on the surface of the first intrinsic polycrystalline silicon obtained in the step S2, and then the diffusion annealing process is carried out; the sheet resistance of the first doped polysilicon obtained in the step S3 is 400-600Ω, and the sheet resistance of the second doped polysilicon obtained is 40-150Ω, preferably 50-150Ω;
and the silicon dioxide barrier layer is removed by cleaning in step S4.
More preferably, the thickness of the silicon dioxide barrier layer is 1/3 to 1 times, preferably 1/2 to 1 times the difference in thickness between the first and second intrinsic polysilicon.
More preferably, the silicon dioxide barrier layer is formed using a tube PECVD apparatus or a plate PECVD apparatus.
In some preferred embodiments of the present invention, the silicon dioxide barrier layer formation conditions include: the growth temperature is 300-550 ℃, and the reaction gas is SiH 4 And N 2 O, the reaction pressure is 500-5000Pa, and the power is 1000-3000W.
In some preferred embodiments of the present invention, the diffusion annealing process is high temperature phosphorus diffusion, and the Gao Wenlin diffusion adopts phosphorus oxychloride diffusion method, which comprises the following steps: firstly, phosphorus diffusion is carried out, the phosphorus diffusion temperature is 700-850 ℃, then high-temperature propulsion is carried out, and the high-temperature propulsion temperature is 850-950 ℃; and subsequently carrying out cooling annealing treatment, and cooling to 600-700 ℃.
More preferably, the conditions for phosphorus diffusion include: POCl is introduced 3 、O 2 、N 2 ，POCl 3 The gas flow is 50sccm-500sccm, O 2 The gas flow is 100sccm-1000sccm, N 2 The gas flow is 100sccm-1000sccm; the pressure of the furnace tube is 50mbar-300mbar, and the phosphorus diffusion time is controlled between 5min and 30min.
More preferably, the conditions of high temperature propulsion include: introducing O 2 And N 2 ，O 2 The gas flow is 1000sccm-2000sccm, N 2 The gas flow is 1000sccm-5000sccm; the pressure of the furnace tube is 100mbar-500mbar, and the high-temperature pushing time is controlled to be 30min-60min.
More preferably, the conditions of the cooling annealing include: introducing N 2 ，N 2 The gas flow is 1000sccm-3000sccm, and the cooling and annealing time is controlled to be 30min-60min.
In some preferred embodiments of the present invention, the cleaning solution used in the cleaning in step S4 is an HF acid solution, wherein the mass percentage of HF in the HF acid solution is 3% -8%.
Preferably, the treatment time of the silicon wafer in the HF acid solution in the cleaning is 2-8min, and the treatment temperature is 15-25 ℃.
In some preferred embodiments of the present invention, the process of providing a back-side polished, front-side textured silicon wafer in step S1 comprises:
s101, polishing the front surface and the back surface of a silicon wafer on two sides, and then cleaning;
s102, depositing a protective layer on the back surface of a double-sided polished silicon wafer;
s103, performing single-sided texturing and cleaning on the front surface of the silicon wafer obtained in the S102 to form a pyramid textured surface on the front surface.
Preferably, the protective layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.
More preferably, the texturing time is 8-40min, and the texturing temperature is 65-85 ℃.
More preferably, the texturing solution adopted by the texturing is mixed solution containing potassium hydroxide, a texturing additive and water, wherein the mass percentage of the potassium hydroxide in the texturing solution is 1% -5%, and the mass percentage of the texturing additive is 0.5% -1%.
In a second aspect, the invention provides a back contact battery, which comprises a silicon wafer, tunneling oxide layers arranged on the front surface and the back surface of the silicon wafer, first doped polysilicon arranged on the front surface of the silicon wafer, and second doped polysilicon arranged on the back surface of the silicon wafer, wherein the back contact battery is prepared by the method in the first aspect, and the thicknesses of the first doped polysilicon and the second doped polysilicon are different, or the thicknesses and the doping concentrations of the first doped polysilicon and the second doped polysilicon are different.
The beneficial effects are that:
according to the technical scheme, especially, the silicon wafers are controlled to be arranged face to face at different intervals, and L1, L2, S1 and S2 meeting specific relations are matched, then a tunneling oxide layer and intrinsic polycrystalline silicon are formed simultaneously, so that simultaneous growth of the polycrystalline silicon with different thicknesses on two sides can be realized, the conductivity of the obtained battery is improved, and meanwhile, the short-circuit current and the filling factor of the battery are improved, so that the conversion efficiency of the battery is improved; because the tunneling oxide layer and the polysilicon structure are formed on the front and back surfaces simultaneously, the equipment cost is obviously reduced. The silicon wafers have larger spacing, the larger the degree of freedom of the gas when the corresponding polysilicon is formed, the faster the reaction rate, and the thicker the polysilicon grown in the same time; the silicon wafers have smaller spacing, the corresponding polysilicon has small gas degree of freedom when being formed, gas is not easy to enter, the reaction rate is slower, and the polysilicon grown at the same time is thinner, thereby realizing the simultaneous growth of the polysilicon with different thicknesses on the two sides. The invention particularly requires L1, L2, S1 and S2 meeting specific relation, can reduce light absorption of front polycrystal and ensure conductivity of back polycrystal, and is beneficial to improving short circuit current and filling factor of the battery, thereby improving conversion efficiency of the battery. Under the same conditions, if the specific relationship is not satisfied, such as L1/L2 > [ S1/(2×S2) ] +0.3, the front poly is too thick or the back poly is too thin, the light absorption is serious due to the too thick front, the current is obviously reduced, and the back conductivity is poor due to the too thin back. If [ S1/(2×S2) ]+0.1 > L1/L2, passivation will be destroyed during wet cleaning due to too thin front side polycrystal or too thick back side polycrystal, and laser opening process during subsequent HBC battery manufacturing will be adversely affected due to too thick back side polycrystal.
In the scheme of the invention, the silicon dioxide blocking layer is preferably arranged, and the silicon dioxide blocking layer can be used for simultaneously diffusing different doping concentrations according to different polysilicon thicknesses of the front side and the back side, because the diffusion coefficient of common impurities (boron, phosphorus, arsenic and the like) in the oxide layer is far smaller than that in silicon, the oxide layer has the capability of blocking the diffusion of the impurities to the semiconductor, so that the silicon dioxide blocking layer is deposited on the surface of the polysilicon with the thinner front side before the diffusion annealing process in the preferred scheme, the diffusion speed of the phosphorus impurities is slowed down in the phosphorus diffusion, the doping concentration of the polysilicon with the front side is reduced, the back side is not blocked by the silicon dioxide blocking layer, and the doping concentration is higher, so that the different doping concentrations of the front side and the back side are formed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the structure of a quartz boat and silicon wafer in cooperation with each other according to embodiment 1 of the present invention;
FIG. 2 is a schematic diagram of the structure of a double-sided polished silicon wafer according to example 1 of the present invention;
FIG. 3 is a schematic structural diagram of a single-sided textured silicon wafer according to example 1 of the present invention;
fig. 4 is a schematic diagram of the structure of the tunneling oxide layer and the intrinsic polysilicon formed on the front and back surfaces of embodiment 1 of the present invention;
FIG. 5 is a schematic diagram of a structure of a silicon dioxide barrier layer formed on the surface of the first intrinsic polysilicon of FIG. 4;
FIG. 6 is a schematic diagram of the prior art quartz boat and wafer configuration of comparative example 1.
Description of the reference numerals
1. Quartz boat, 2, double-sided polished silicon wafer, 3, single-sided textured silicon wafer, 4, first tunneling oxide layer, 5, second tunneling oxide layer, 6, first intrinsic polysilicon, 7, second intrinsic polysilicon, 8, silicon dioxide barrier layer.
Detailed Description
In the present disclosure, the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The endpoints and any values of the ranges disclosed herein are not limited to the precise range or value, and are understood to encompass values approaching those ranges or values. For numerical ranges, one or more new numerical ranges may be found between the endpoints of each range, between the endpoint of each range and the individual point value, and between the individual point value, in combination with each other, and are to be considered as specifically disclosed herein. Wherein the terms "optional" and "optionally" mean either comprising or not comprising (or may not be present).
In a first aspect, the invention provides a method for simultaneously growing polycrystalline silicon with different thicknesses on the front and back surfaces of a battery, comprising the following steps:
step S1, providing a silicon wafer with polished back and textured front;
s2, controlling silicon wafers to be arranged in pairs at intervals, wherein the front surfaces of the silicon wafers in pairs are arranged face to face, the distance between the front surfaces of the silicon wafers in pairs is S1, and the distance between the back surfaces of the silicon wafers in the previous pair and the back surfaces of the adjacent silicon wafers in the next pair is S2, wherein S2 is larger than S1; then simultaneously forming tunneling oxide layers on the front surface and the back surface of the silicon wafer, and then simultaneously forming intrinsic polycrystalline silicon on the front surface and the back surface, wherein the first intrinsic polycrystalline silicon is formed on the front surface and has a thickness L1 on the textured front surface, the second intrinsic polycrystalline silicon with a thickness L2 is formed on the back surface, and the L1, L2, S1 and S2 satisfy the following conditions: [ S1/(2×S2) ] +0.1.ltoreq.L1/L2.ltoreq.S 1/(2×S2) ] +0.3;
s3, forming a corresponding doped polysilicon layer by using a diffusion annealing process to enable the first intrinsic polysilicon and the second intrinsic polysilicon;
and S4, cleaning.
Preferably, [ S1/(2X S2) ] +0.1.ltoreq.L1/L2.ltoreq.S 1/(2X S2) ] +0.2.
Preferably, L1 is 15-70nm, preferably 15-50nm, and L2 is 100-300nm. According to the preferred scheme, the L1 and L2 are proper in value, the light absorption of the front polycrystal can be reduced, the conductivity of the back polycrystal is ensured, and the short-circuit current and the filling factor of the battery are improved.
Preferably, S1 is 1-5mm, preferably 2-5mm, S2 is 10-15mm. According to the preferred scheme, the S1 and the S2 are proper in value, the fact that the front and back polycrystal is in proper thickness can be guaranteed, and improvement of short-circuit current and filling factors of the battery is facilitated.
In some preferred embodiments of the present invention, the tunnel oxide layer has a thickness of 1.2-2.0nm. According to the preferred scheme, the thickness of the tunneling oxide layer is proper, so that the passivation level can be ensured, and the tunneling of carriers is facilitated.
In the invention, the prior art can be used for preparing the silicon wafer with polished back and textured front by the prior method. For example, in some embodiments of the present invention, the process of providing a back side polished, front side textured silicon wafer in step S1 comprises:
s101, polishing the front surface and the back surface of a silicon wafer on two sides, and then cleaning;
s102, depositing a protective layer on the back surface of a double-sided polished silicon wafer;
s103, performing single-sided texturing and cleaning on the front surface of the silicon wafer obtained in the S102 to form a pyramid suede on the front surface, and reducing reflectivity. It will be appreciated that the protective layer deposited in S102 will be removed in the cleaning step of S103, using a cleaning liquid such as hydrofluoric acid.
S101, the polishing solution for double-sided polishing is alkaline solution, and the linear cutting damaged layer on the surface of the silicon wafer is removed by the alkaline solution; and then cleaning to remove the residual alkaline solution on the surface of the silicon wafer. The alkali in the alkaline solution can be, for example, potassium hydroxide, sodium hydroxide or a mixture of the two, wherein the mass concentration of the alkali in the alkaline solution can be, for example, 2% -10%.
Preferably, the conditions of the double-sided polishing may include, for example: the reaction temperature is 65-90 ℃, the reaction time is 1-15min, and the single-sided removal thickness is controlled to be 1-20 mu m.
The protective layer in S102 has the property of stronger alkali solution corrosion resistance, and can resist alkali corrosion in the velvet making liquid; the protective layer may include at least one of silicon nitride, silicon oxide, and silicon oxynitride, for example. The protective layer may be formed by a thin film formation method such as a sputtering method or a CVD method, and is preferably formed by a PECVD method.
In S103, more preferably, the texturing time is 8-40min, and the texturing temperature is 65-85 ℃.
More preferably, the texturing solution adopted by the texturing is a mixed solution containing potassium hydroxide, a texturing additive and water, wherein the mass percent of the potassium hydroxide in the texturing solution is 1-5%, the mass percent of the texturing additive is 0.5-1%, and the texturing additive can be any commercially available texturing additive in the field.
The silicon wafer in step S1 is preferably an N-type monocrystalline silicon wafer.
In some preferred embodiments of the present invention, the simultaneous formation of the tunnel oxide layer and the intrinsic polysilicon in step S2 is performed in a tube type LPCVD apparatus, and each silicon wafer is mounted on a quartz boat having a plurality of clamping grooves. According to the preferred scheme, the tubular LPCVD equipment is matched with the quartz boat, so that a compact tunneling oxide layer and intrinsic polycrystalline silicon can be deposited, passivation level is improved more easily, and the silicon is not easy to damage by a solution in a subsequent cleaning process.
In the step S2, the silicon wafers are controlled to be arranged in pairs at intervals, the front faces of the pairs of silicon wafers are arranged face to face and the spacing between the S1 and the S2 is met, and the silicon wafers can be clamped on the clamping grooves of the quartz boat. The clamping grooves on the quartz boat can be arranged at unequal intervals, and the unequal intervals are matched with the intervals of the S1 and the S2 so as to clamp the silicon wafers to meet the arrangement structure; the plurality of clamping grooves can also be arranged at equal intervals, and in this case, silicon wafers are clamped in part of the clamping grooves at different intervals S1 and S2 to meet the arrangement structure.
In some preferred embodiments of the present invention, in step S2, the conditions for forming the tunnel oxide layer include: thermal oxidation is carried out at 550-650 ℃. The time of the thermal oxidation may be determined according to the thickness of the tunnel oxide layer required, and may be, for example, 10-30min.
In some preferred embodiments of the present invention, the conditions for forming intrinsic polysilicon include: the growth temperature is 550-650 ℃ and the air pressure is 5-10000Pa. The time for forming the intrinsic polycrystalline silicon may be determined according to the thickness of the intrinsic polycrystalline silicon required, and may be, for example, 20 to 40 minutes.
The cleaning of step S4 of the present invention is used to remove the double-sided PSG layer (i.e., the phosphosilicate glass layer) generated in the diffusion annealing process.
In some preferred embodiments of the present invention, the cleaning solution used in the cleaning in step S4 is an HF acid solution, wherein the mass percentage of HF in the HF acid solution is 3% -8%.
Preferably, the treatment time of the silicon wafer in the HF acid solution in the cleaning is 2-8min, and the treatment temperature is 15-25 ℃.
In some preferred embodiments of the present invention, the method further comprises the step of simultaneously forming polysilicon of different doping concentrations on the front and back surfaces: in the step S3, firstly, a silicon dioxide barrier layer is formed on the surface of the first intrinsic polycrystalline silicon obtained in the step S2, and then the diffusion annealing process is carried out; the sheet resistance of the first doped polysilicon obtained in the step S3 is 400-600Ω, and the sheet resistance of the second doped polysilicon obtained is 40-150Ω, preferably 50-150Ω; and the silicon dioxide barrier layer is removed by cleaning in step S4. In the preferred scheme, a silicon dioxide blocking layer is deposited on the surface of the polysilicon with the thinner front surface before a diffusion annealing process, the diffusion speed of phosphorus impurities is slowed down in phosphorus diffusion, the doping concentration of the polysilicon at the front surface is reduced, the back surface is not blocked by the silicon dioxide blocking layer, the doping concentration is higher, the doped polysilicon with different front and back surface doping concentrations can be formed, and the doped polysilicon with different front and back surface sheet resistances is formed, wherein the sheet resistance is smaller when the doping concentration is higher.
More preferably, the thickness of the silicon dioxide barrier layer is 1/3 times to 1 times the thickness difference between the first intrinsic polysilicon and the second intrinsic polysilicon.
Further preferably, the thickness of the silicon dioxide barrier layer is 1/2 times to 1 times the thickness difference between the first intrinsic polysilicon and the second intrinsic polysilicon. According to the preferred scheme, the thickness of the silicon dioxide barrier layer is proper, the doping solubility required by front polycrystalline can be met while the passivation effect is considered, so that the front polycrystalline is not excessively doped or insufficiently doped, and the passivation level of the front polycrystalline is improved.
More preferably, the silicon dioxide barrier layer is formed using a tube PECVD apparatus or a plate PECVD apparatus, and even more preferably a tube PECVD apparatus.
In some preferred embodiments of the present invention, the silicon dioxide barrier layer formation conditions include: the growth temperature is 300-550 ℃, and the reaction gas is SiH 4 And N 2 O, the reaction pressure is 500-5000Pa, and the power is 1000-3000W.
The ratio of gases in the reaction gas and the growth time can be determined according to the amount of the silicon dioxide barrier layer to be formed, for example, siH in the reaction gas 4 And N 2 The molar ratio of O may be 0.2-0.5:1, the growth time can be 10-20min.
In some preferred embodiments of the present invention, the diffusion annealing process is high temperature phosphorus diffusion, and the Gao Wenlin diffusion adopts phosphorus oxychloride diffusion method, which comprises the following steps: firstly, phosphorus diffusion is carried out, the phosphorus diffusion temperature is 700-850 ℃, then high-temperature propulsion is carried out, and the high-temperature propulsion temperature is 850-950 ℃; and subsequently carrying out cooling annealing treatment, and cooling to 600-700 ℃.
More preferably, the conditions for phosphorus diffusion include: POCl is introduced 3 、O 2 、N 2 ，POCl 3 The gas flow is 50sccm-500sccm, O 2 The gas flow is 100sccm-1000sccm, N 2 The gas flow is 100sccm-1000sccm; the pressure of the furnace tube is 50mbar-300mbar, and the phosphorus diffusion time is controlled between 5min and 30min.
More preferably, the conditions of high temperature propulsion include: introducing O 2 And N 2 ，O 2 The gas flow is 1000sccm-2000sccm, N 2 The gas flow is 1000sccm-5000sccm; the pressure of the furnace tube is 100mbar-500mbar, and the high-temperature pushing time is controlled to be 30min-60min.
More preferably, the conditions of the cooling annealing include: introducing N 2 ，N 2 The gas flow is 1000sccm-3000sccm, and the cooling and annealing time is controlled to be 30min-60min.
In a second aspect, the invention provides a back contact cell comprising a silicon wafer, tunneling oxide layers disposed on both a front surface and a back surface of the silicon wafer, a first doped polysilicon disposed on the front surface of the silicon wafer, and a second doped polysilicon disposed on the back surface of the silicon wafer. The back contact battery is prepared by the method according to the first aspect, and the thicknesses of the first doped polysilicon and the second doped polysilicon are different, or the thicknesses and the doping concentrations of the first doped polysilicon and the second doped polysilicon are different.
It should be noted that the tunnel oxide layer and the second doped polysilicon layer disposed on the back surface serve as the first semiconductor layer. Those skilled in the art may further configure conventional structural layers, such as the second semiconductor layer and the metal electrode, according to requirements, and will not be described herein.
The back contact battery provided by the invention has excellent conductivity, high battery current and high battery conversion efficiency.
The following detailed description of the embodiments of the invention is exemplary and is merely illustrative of the invention and not to be construed as limiting the invention.
Example 1
A method for simultaneously growing polycrystalline silicon with different thicknesses and doping concentrations on the front and back surfaces of a battery comprises the following steps:
step S1, providing a silicon wafer with polished back and textured front, wherein the process is as follows:
s101, as shown in FIG. 2, performing double-sided polishing on the front side and the back side of an N-type monocrystalline silicon wafer, removing a linear cutting damage layer on the surface of the silicon wafer by using an alkaline solution to form a double-sided polished silicon wafer 2, wherein the alkaline solution is a potassium hydroxide solution with the mass concentration of 5%, the reaction temperature is 70 ℃, the reaction time is 5min, the single-sided removal thickness is controlled to be 10 mu m, and then performing standard RCA cleaning to remove the residual alkaline solution on the surface of the silicon wafer.
S102, depositing a silicon nitride protective layer on the back surface of the silicon wafer, wherein the silicon nitride protective layer has the property of strong alkali solution corrosion resistance, can resist alkali corrosion in a flocking liquid, and is formed by adopting a PECVD method.
And S103, as shown in FIG. 3, performing single-sided texturing and cleaning on the silicon nitride-protected silicon wafer to form a pyramid textured surface on the front surface, and reducing the reflectivity to form a single-sided textured silicon wafer 3. The texturing time is 20min, and the texturing temperature is 75 ℃. The texturing solution is an alkaline mixed solution, specifically a mixed solution of potassium hydroxide, a texturing additive and water, wherein the mass percentage of the potassium hydroxide is 2%, the mass percentage of the texturing additive is 0.5%, and the balance is water, and the texturing additive is a commercial product (purchased from Changzhou time-series energy source Co., ltd., brand name is TS series).
In step S2, as shown in fig. 4, the single-sided textured silicon wafer 3 is simultaneously grown with LPCVD to form a first tunneling oxide layer 4, a second tunneling oxide layer 5, a first intrinsic polysilicon 6 and a second intrinsic polysilicon 7, where the first intrinsic polysilicon 6 is deposited to a thickness L1 on the textured front surface and the second intrinsic polysilicon 7 is deposited to a thickness L2 on the polished back surface. The corresponding tunnel oxide layer and the corresponding polysilicon were grown in a tube LPCVD apparatus using a quartz boat 1 having different pitches on both sides of the silicon wafer, as shown in FIG. 1, the silicon wafer was set on the quartz boat 1 and arranged in pairs at intervals with the front faces of the pairs of silicon wafers facing each other, the spacing between the two textured front faces in the pairs of silicon wafers was S1, S1 was 2mm, the spacing between the adjacent two polished back faces was S2, S2 was 15mm, L1/L2 = [ S1/(2X S2) ] +0.2, the thickness L1 of the first intrinsic polysilicon was 40nm, and the thickness L2 of the second intrinsic polysilicon was 150nm. The formation process of the corresponding tunneling oxide layer comprises the following steps: thermally oxidizing at 600 ℃ for 30min to form a tunneling oxide layer with the thickness of 1.5nm, controlling the growth temperature of the corresponding intrinsic polycrystalline silicon to 600 ℃, controlling the air pressure to 50Pa, and controlling the growth time to 20-40min.
Step S3, as shown in FIG. 5, a silicon dioxide barrier layer 8 is grown on the surface of the first intrinsic polysilicon 6, the silicon dioxide barrier layer 8 is grown by a tubular PECVD device, and the growth conditions of the silicon dioxide barrier layer 8 are as follows: the growth temperature is controlled to be 450 ℃, and the reaction gas is SiH 4 And N 2 O and the mole ratio of the two is 0.3:1, the reaction pressure is 1000Pa, the power is 2000W, and the growth time is 10min. The thickness of the silicon dioxide blocking layer is the difference between the thickness L1 of the first intrinsic polysilicon and the thickness L2 of the second intrinsic polysilicon.
The silicon wafer with the grown silicon dioxide barrier layer 8 is subjected to high-temperature diffusion, so that the corresponding intrinsic polycrystalline silicon is subjected to phosphorus doping to form N-type doped polycrystalline silicon, and a phosphorus oxychloride diffusion method is specifically adopted, and the process comprises the following steps: firstly, phosphorus diffusion is carried out, POCl is introduced in the phosphorus diffusion process 3 、O 2 、N 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the phosphorus diffusion temperature is 750 ℃, the phosphorus diffusion time is 10min, and POCl is adopted during phosphorus diffusion 3 The gas flow rate is 100sccm, O 2 The gas flow rate is 200sccm, N 2 The gas flow is 100sccm, and the pressure of the furnace tube is 100mbar; then high-temperature propulsion is carried out, and O is introduced in the high-temperature propulsion process 2 And N 2 The method comprises the steps of carrying out a first treatment on the surface of the The high-temperature pushing temperature is 900 ℃, and the high-temperature pushing time is 40min. O during high temperature propulsion 2 The gas flow is 1000sccm; n (N) 2 The gas flow rate is 2000sccm; the furnace tube pressure was 200mbar. The sheet resistance of the obtained first doped polysilicon is 400 omega, and the sheet resistance of the second doped polysilicon is 60 omega.
Then cooling and annealing treatment is carried out, the temperature is reduced to 600 ℃, and N is introduced in the process 2 ，N 2 The gas flow is 1500sccm, and the cooling and annealing time is controlled at 40min.
And S4, re-cleaning the diffused silicon wafer, wherein a silicon dioxide barrier layer and phosphosilicate glass (namely PSG layer) formed by high-temperature diffusion reaction exist on the surface of the N-type polycrystalline silicon layer of the embodiment, the cleaning solution adopted in the re-cleaning is an HF acid solution, the HF acid solution comprises 5% by mass of HF, the deionized water comprises 95% by mass of HF, the treatment time of the silicon wafer in the HF acid solution is 5min, and the treatment temperature is 20 ℃.
Example 2
The procedure of example 1 was followed, except that l1=22.5 nm and s1=1.5 mm were adjusted so that [ S1/(2×s2) ]+0.1=l1/L2, where L2, S2 were unchanged. The process parameters are changed correspondingly to meet L1: the front side silicon dioxide barrier layer was varied to a thickness of 127.5nm instead of 110nm for example 1.
Example 3
The procedure of example 1 was followed, except that l1=70 nm and s1=5 nm were adjusted so that [ S1/(2×s2) ]+0.3=l1/L2, where L2, S2 were unchanged. The process parameters are changed correspondingly to meet L1: the thickness of the front side oxidation barrier layer was changed to 80nm instead of 110nm for example 1.
Example 4
The process of reference example 1 was performed, except that a silicon dioxide barrier layer was not formed.
The doping concentrations of the first doped polysilicon and the second doped polysilicon obtained in the embodiment are the same, and the square resistance is 400 omega.
Example 5
The process according to example 1 is carried out with the difference that the thickness of the silicon dioxide barrier layer is 50nm; which is less than 1/2 of the difference in thickness of the first intrinsic polysilicon and the second intrinsic polysilicon.
The sheet resistance of the first doped polysilicon obtained in this embodiment is 200Ω; the sheet resistance of the second doped polysilicon is 60deg.C.
Example 6
The process according to example 1 is carried out with the difference that the thickness of the silicon dioxide barrier layer is 130nm; which is greater than the difference in thickness between the first and second intrinsic polycrystalline silicon.
The sheet resistance of the first doped polysilicon obtained in this embodiment is 500Ω; the sheet resistance of the second doped polysilicon is 60deg.C.
Comparative example 1
The process of example 1 was performed with the difference that, in the tube type LPCVD apparatus employed in forming the corresponding tunnel oxide layer and intrinsic polycrystalline silicon, silicon wafers were alternately arranged at equal intervals (interval of 15 mm) in a quartz boat, and as shown in FIG. 6, the front surface of the silicon wafer was arranged face to face with the back surface of the adjacent silicon wafer.
The thickness of the first doped polysilicon obtained in this comparative example was 150nm, and the sheet resistance was 600Ω; the thickness of the second doped polysilicon is 150nm, and the sheet resistance is 60 omega.
Comparative example 2
The procedure of example 1 was followed, except that l1=20 nm was adjusted so that [ S1/(2×s2) ]+0.1 > L1/L2. The process parameters are changed correspondingly to meet the conditions: the thickness of the increased oxidation barrier layer was 130nm.
Comparative example 3
The procedure of example 1 was followed, except that l2=50 nm was adjusted so that [ S1/(2×s2) ]+0.3 < L1/L2, and the process parameters were changed accordingly to meet the conditions: the corresponding phosphorus diffusion time was changed to 66% of that of example 1, and the sheet resistance of the second intrinsic polysilicon layer was 150Ω.
Test case
The tunnel oxide layer and the doped polysilicon silicon wafer are formed on the front and back sides of the silicon wafer obtained in the above examples and comparative examples, and conventional layers are uniformly configured (i.e., an antireflection layer is further disposed on the front side, a second semiconductor layer including an intrinsic amorphous layer and a P-type doped microcrystalline silicon layer, a mask layer, a conductive film layer, and a metal electrode are further disposed on the back side, and the back structure is the same as that of the applicant's early patent CN 115207137B) to form a battery. The resultant batteries were then subjected to uniform performance tests, respectively, the test results of which are shown in table 1.
TABLE 1
Compared with the comparative example, the embodiment of the invention can realize simultaneous growth of polysilicon with different thicknesses on both sides, and can improve the short-circuit current, the filling factor and the battery conversion efficiency of the battery while improving the conductivity.
Furthermore, according to the embodiment 1 and the embodiment 3 of the present invention, the corresponding relationship of L1, L2, S1, S2 in the preferred specific range of the present invention is adopted, so that the front and back polysilicon forms a suitable thickness ratio, the influence of the excessive thickness of the back polysilicon on the short-circuit current is significantly reduced, and the loss caused by the corresponding higher energy laser opening is reduced as much as possible, thereby further improving the battery conversion efficiency.
Furthermore, according to embodiment 1 and embodiments 4-6 of the present invention, the silicon dioxide barrier layer and the thickness thereof are preferably provided, which is more beneficial to doping the back polysilicon and improving the filling factor of the battery.
The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the scope of the technical idea of the invention, a number of simple variants of the technical solution of the invention are possible, including combinations of the individual technical features in any other suitable way, which simple variants and combinations should likewise be regarded as being disclosed by the invention, all falling within the scope of protection of the invention.
Claims (10)
1. The method for simultaneously growing the polycrystalline silicon with different thicknesses on the front and back surfaces of the battery is characterized by comprising the following steps of:
(1) Providing a silicon wafer with polished back and textured front;
(2) The control silicon wafers are arranged in pairs at intervals, the front surfaces of the pair of silicon wafers face to face, the distance between the front surfaces of the pair of silicon wafers is S1, and the distance between the back surface of the front pair of silicon wafers and the back surface of the adjacent back pair of silicon wafers is S2, wherein S2 is larger than S1; then simultaneously forming tunneling oxide layers on the front surface and the back surface of the silicon wafer, and then simultaneously forming intrinsic polycrystalline silicon on the front surface and the back surface, wherein the first intrinsic polycrystalline silicon is formed on the front surface and has a thickness L1 on the textured front surface, the second intrinsic polycrystalline silicon with a thickness L2 is formed on the back surface, and the L1, L2, S1 and S2 satisfy the following conditions: [ S1/(2×S2) ] +0.1.ltoreq.L1/L2.ltoreq.S 1/(2×S2) ] +0.3;
(3) Forming a corresponding doped polysilicon layer by using a diffusion annealing process to enable the first intrinsic polysilicon and the second intrinsic polysilicon;
(4) And then cleaning.
2. The method according to claim 1, wherein L1 is 15-70nm, L2 is 100-300nm, S1 is 1-5mm, S2 is 10-15mm;
and/or the number of the groups of groups,
the thickness of the tunneling oxide layer is 1.2-2.0nm.
3. The method of claim 1, wherein the simultaneous formation of the tunnel oxide layer and the intrinsic polysilicon in step (2) is performed in a tube LPCVD apparatus, and each wafer is mounted on a quartz boat having a plurality of clamping grooves.
4. The method of claim 1, wherein in step (2), the conditions for forming the tunnel oxide layer comprise: thermally oxidizing at 550-650 ℃; the conditions for forming intrinsic polysilicon include: the growth temperature is 550-650 ℃ and the air pressure is 5-10000Pa.
5. The method of claim 1, further comprising the step of simultaneously forming polysilicon of different doping concentrations on the front and back sides:
in the step (3), firstly, a silicon dioxide barrier layer is formed on the surface of the first intrinsic polycrystalline silicon obtained in the step (2), and then the diffusion annealing process is carried out, so that the sheet resistance of the first doped polycrystalline silicon obtained in the step (3) is 400-600Ω, and the sheet resistance of the second doped polycrystalline silicon obtained in the step (3) is 40-150Ω;
and removing the silicon dioxide barrier layer by cleaning in step (4).
6. The method of claim 5, wherein the silicon dioxide barrier layer has a thickness that is 1/3 times to 1 times the difference in thickness between the first intrinsic polysilicon and the second intrinsic polysilicon.
7. The method of claim 5, wherein the silicon dioxide barrier layer is formed using a tube PECVD apparatus or a plate PECVD apparatus;
and/or the number of the groups of groups,
the formation conditions of the silicon dioxide barrier layer comprise: the growth temperature is 300-550 ℃, and the reaction gas is SiH 4 And N 2 O, the reaction pressure is 500-5000Pa, and the power is 1000-3000W.
8. The method of claim 5, wherein the diffusion annealing process is high temperature phosphorus diffusion, and wherein the Gao Wenlin diffusion adopts phosphorus oxychloride diffusion method, and the process comprises: firstly, phosphorus diffusion is carried out, the phosphorus diffusion temperature is 700-850 ℃, then high-temperature propulsion is carried out, and the high-temperature propulsion temperature is 850-950 ℃; subsequently, cooling and annealing treatment is carried out, and the temperature is reduced to 600-700 ℃;
wherein the conditions for phosphorus diffusion include: POCl is introduced 3 、O 2 、N 2 ，POCl 3 The gas flow is 50sccm-500sccm, O 2 The gas flow is 100sccm-1000sccm, N 2 The gas flow is 100sccm-1000sccm; the pressure of the furnace tube is 50mbar-300mbar, and the phosphorus diffusion time is controlled to be 5min-30min;
the conditions of the high-temperature propulsion include: introducing O 2 And N 2 ，O 2 The gas flow is 1000sccm-2000sccm, N 2 The gas flow is 1000sccm-5000sccm; the pressure of the furnace tube is 100mbar-500mbar, and the high-temperature pushing time is controlled to be 30min-60min;
the conditions of the cooling annealing include: introducing N 2 ，N 2 The gas flow is 1000sccm-3000sccm, and the cooling and annealing time is controlled to be 30min-60min.
9. The method according to claim 1, wherein the cleaning solution adopted in the step (4) is an HF acid solution, the mass percentage of HF in the HF acid solution is 3% -8%, the treatment time of the silicon wafer in the HF acid solution in the cleaning is 2-8min, and the treatment temperature is 15-25 ℃;
and/or
The process of providing the back-side polished and front-side textured silicon wafer in the step (1) comprises the following steps:
s101, polishing the front surface and the back surface of a silicon wafer on two sides, and then cleaning;
s102, depositing a protective layer on the back surface of a double-sided polished silicon wafer;
s103, single-sided texturing and cleaning are carried out on the front surface of the silicon wafer obtained in the step S102 to form a pyramid suede on the front surface, wherein the texturing time is 8-40min, the texturing temperature is 65-85 ℃, the texturing liquid adopted in the texturing is mixed liquid containing potassium hydroxide, a texturing additive and water, the mass percentage of the potassium hydroxide in the texturing liquid is 1-5%, and the mass percentage of the texturing additive is 0.5-1%.
10. A back contact cell comprising a silicon wafer, tunneling oxide layers arranged on the front surface and the back surface of the silicon wafer, first doped polysilicon arranged on the front surface of the silicon wafer, and second doped polysilicon arranged on the back surface of the silicon wafer, wherein the back contact cell is prepared by the method according to any one of claims 1-9, and the thicknesses of the first doped polysilicon and the second doped polysilicon are different, or the thicknesses and the doping concentrations of the first doped polysilicon and the second doped polysilicon are different.
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