CN116935794A

CN116935794A - Driving chip, partition multi-frequency display method of display device and display device

Info

Publication number: CN116935794A
Application number: CN202310943980.8A
Authority: CN
Inventors: 安泰生
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd
Priority date: 2023-07-28
Filing date: 2023-07-28
Publication date: 2023-10-24

Abstract

The application discloses a driving chip, a partition multi-frequency display method of a display device and the display device. The driving chip at least comprises an image registering module and an image output module, wherein the image registering module is coupled with the image output module, and the driving chip comprises: the image registering module is configured to store a plurality of image data output by the front-end processor; the image output module is configured to read a part of the plurality of image data from the image register module according to refresh frequencies of the plurality of display areas carried in the instruction sent by the front-end processor, and generate corresponding data signals. According to the embodiment of the application, parts in the plurality of image data can be read according to the refresh frequencies of different display areas to generate corresponding data signals, so that the power consumption of the driving chip is reduced.

Description

Driving chip, partition multi-frequency display method of display device and display device

Technical Field

The application belongs to the technical field of display panels, and particularly relates to a driving chip, a partition multi-frequency display method of a display device and the display device.

Background

Organic light emitting diodes (Organic Light Emitting Display, OLEDs) and flat display devices based on the technologies of light emitting diodes (Light Emitting Diode, LEDs) are widely used in various consumer electronic products such as mobile phones, televisions, notebook computers, and desktop computers, and become the mainstream of display devices, because of their advantages such as high image quality, power saving, thin body, and wide application range.

However, the service performance of the current OLED display product needs to be improved.

Disclosure of Invention

The embodiment of the application provides a driving chip, a partition multi-frequency display method of a display device and the display device, which can improve the service performance of OLED display products.

In a first aspect, an embodiment of the present application provides a driving chip, where the driving chip at least includes an image register module and an image output module, and the image register module is coupled to the image output module, where:

the image registering module is configured to store a plurality of image data output by the front-end processor;

the image output module is configured to read a part of the plurality of image data from the image register module according to refresh frequencies of the plurality of display areas carried in the instruction sent by the front-end processor, and generate corresponding data signals.

In some embodiments, the plurality of display regions includes a first display region and a second display region, the first display region having a refresh frequency that is higher than a refresh frequency of the second display region, the reading a portion of the plurality of image data from the image registration module includes:

and reading the image data corresponding to the first display area from the image registering module.

In some embodiments, the driver chip further comprises a gate dynamic control module coupled to the image output module, wherein:

The image output module is further configured to generate a control signal based on the refresh frequency of the plurality of display areas and the read image data;

the grid dynamic control module is configured to respond to the control signals to generate scanning driving control signals with corresponding time sequences so that the grid driving circuit sequentially outputs a plurality of scanning signals based on the scanning driving control signals, wherein the frequencies of conducting pulses in at least two scanning signals are different;

in some embodiments, the plurality of display regions includes a first display region and a second display region, the refresh frequency corresponding to the first display region is higher than the refresh frequency corresponding to the second display region, and the frequency of the on pulse in the scan signal corresponding to the first display region is greater than the frequency of the on pulse in the scan signal corresponding to the second display region.

In some embodiments, the driver chip further comprises a source dynamic control module coupled to the image output module, wherein:

the image output module is further configured to generate a data drive control signal based on the refresh frequency of the plurality of display regions;

the source dynamic control module is configured to maintain a voltage of the data signal except for the corresponding data signal unchanged in response to the data driving control signal.

In some embodiments, the driving chip further includes:

the data output modules are respectively connected with the plurality of signal fan-out lines and comprise a first data signal port and at least one second data signal port; the first data signal port is used for providing a data signal corresponding to the read image data, and the second data signal port is used for providing a data signal corresponding to the unread image data;

and the source dynamic control module is used for controlling the signal voltage of the first data signal port to be unchanged under the condition that the grid driving circuit does not output a scanning signal, or switching the connection between the first data signal port and the signal fan-out line into the connection between the second data signal port and the signal fan-out line.

In some embodiments, the driving chip further includes a gate dynamic control module and a source dynamic control module in the above embodiments.

In some embodiments, the driving chip further includes:

the data output modules are respectively connected with the plurality of signal fan-out lines and comprise a first data signal port and at least one second data signal port; the first data signal port is used for providing a data signal corresponding to image data, and the second data signal port is used for providing a data signal with a fixed potential;

In a second aspect, an embodiment of the present application provides a partitioned multi-frequency display method of a display device, where the display device at least includes a display panel, the display panel has a plurality of display areas according to the first aspect, and the partitioned multi-frequency display method at least includes:

acquiring a plurality of image data and refresh frequencies of a plurality of display areas;

and reading parts in the plurality of image data according to the refresh frequency of each display area, and generating corresponding data signals.

In some embodiments, after acquiring the plurality of image data and the refresh frequency of the plurality of display regions, further comprising:

generating a scanning driving control signal according to the refreshing frequency of each display area;

sequentially outputting a plurality of scan signals in response to a scan driving control signal; wherein the frequencies of the conducting pulses in at least two scanning signals are different;

in some embodiments, the plurality of display regions includes a first display region and a second display region, the refresh frequency corresponding to the first display region is higher than the refresh frequency corresponding to the second display region, and the frequency of the on pulse in the scan signal corresponding to the first display region is greater than the frequency of the on pulse in the scan signal corresponding to the second display region;

generating a data driving control signal according to the refresh frequency of each display area;

in response to the data driving control signal, the voltage of the data signals other than the corresponding data signals is maintained unchanged.

In a third aspect, an embodiment of the present application provides a display device, including at least:

a display panel having a plurality of display areas of the first aspect;

a storage medium configured to store computer program instructions;

a front-end processor configured to output the plurality of image data of the first aspect and execute computer program instructions; the method comprises the steps of,

the driving chip of the first aspect is configured to perform the partitioned multi-frequency display method of the display device of the second aspect in response to computer program instructions to achieve partitioned multi-frequency display of the display panel.

Compared with the prior art, the driving chip, the partition multi-frequency display method of the display device and the display device provided by the embodiment of the application have the advantages that the image output module and the image registering module are arranged, the image registering module can store a plurality of image data output by the front-end processor, the refreshing frequencies of the display areas are obtained from the instruction sent by the front-end processor through the image output module, and the image output module can read part of image data from the plurality of image data stored in the image registering module according to the refreshing frequencies of the display areas and generate data signals corresponding to the part of image data. Because the image output module can read part of image data in the plurality of image data according to the refresh frequency of different display areas, when the refresh frequency of the part of display areas is lower, the image output module can not read the corresponding image data when the part of display areas are positioned in the holding frame, and also can not generate the data signal corresponding to the part of image data. Since the driving chip in a single image frame only needs to generate corresponding data signals for part of the image data in the plurality of image data, the power consumption of the driving chip can be reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

FIG. 1 is a schematic diagram of a driving chip according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a driving chip according to another embodiment of the present application;

FIG. 3 is a schematic diagram of a driving chip according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a driving chip according to another embodiment of the present application;

FIG. 5 is a schematic diagram of a display device according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present application;

FIG. 7 is a flow chart of a method for partitioning multiple frequency display according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a multi-band display device according to an embodiment of the present application;

in the accompanying drawings:

1. a display area; 2. a non-display area; 10. a driving chip; 20. an image output module; 30. a grid dynamic control module; 40. a source dynamic control module; 50. an image registering module; 60. a front-end processor; 70. a data output module; 80. a digital-to-analog conversion module; fan, signal Fan out line; 11. a light emitting sub-pixel; GIP, gate driving circuit; OE, scan drive control signal line.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the particular embodiments described herein are meant to be illustrative of the application only and not limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The embodiments will be described in detail below with reference to the accompanying drawings.

In order to solve the technical problems, the embodiment of the application provides a driving chip, a partition multi-frequency display method of a display device and the display device. The following first describes a driving chip provided by an embodiment of the present application.

Fig. 1 is a schematic block diagram of a driving chip 10 according to an embodiment of the present application. The driving chip 10 includes at least an image registering module 50 and an image outputting module 20.

The image registering module 50 is coupled to the image output module 20.

The image registration module 50 is capable of storing a plurality of image data output from the front-end processor. That is, during the image display process, the front-end processor 60 may transmit a plurality of image data to be displayed to the driving chip 10 and store in the image registering module 50 of the driving chip 10.

The front-end processor 60 may also output refresh frequencies of different display areas into the driver chip 10 when outputting image data. For example, front-end processor 60 may be capable of partitioning the display area by two, three, or more partitions with partitioned multi-frequency display functions. The refresh frequencies of each partition are independent of each other and may be the same or different. And the dividing boundary of the display area can be flexibly adjusted. For example, in the case of dividing two partitions, the display area may be divided up and down, and the dividing line of the two areas may be any one of the pixel rows. In the case of performing the division of three partitions, two dividing lines of the three regions may be any two rows of pixels.

The instruction sent by the front-end processor carries the refresh frequency of the multiple display areas, and the image output module 20 can read part of image data in the multiple image data from the image register module 50 according to the read refresh frequency of each display area, and generate a corresponding data signal according to the read part of image data.

The image registration module 50 may be a GRAM (graphics RAM), an image register. The input of the image registration module 50 may be connected to a front-end processor 60, and the front-end processor 60 may be capable of transmitting the image data of the image to be displayed to the image registration module 50 for storage. The output end of the image registering module 50 may be connected to the image output module 20, and the image output module 20 may read the image data of the image frames corresponding to the respective image frames from the image registering module 50.

The image data module may selectively read a part of the image data among the plurality of image data according to the refresh frequency of different display areas when the image data is read from the image registering module 50, where the part of the image data may be the image data corresponding to a single display area or the image data corresponding to a plurality of display areas.

Taking the example of the display area being divided into three areas of different refresh frequencies, the front-end processor 60 provides refresh frequencies corresponding to the three display areas, respectively. The image data module can respectively determine whether the three display areas in the current image frame need to be refreshed according to the refresh frequencies respectively corresponding to the three display areas. After determining the partial display area needing to be refreshed, the partial image data corresponding to the partial display area needing to be refreshed can be read from the whole frame of image data stored in the image registering module 50, so that the reading amount of the image data is reduced, and the service life of the image registering module 50 is prolonged.

In an exemplary embodiment, taking the refresh frequencies of three areas as 60Hz, 30Hz and 1Hz respectively as an example, when the frame period of a single image frame is sixty seconds, for the display area with the refresh frequency of 60Hz, in each image frame, the image data corresponding to the display area needs to be read from the whole frame of image data stored in the image registering module 50; for a display area with the refresh frequency of 30Hz, selecting one image frame from every two image frames, reading image data corresponding to the display area in the image frame, and not reading the image data in the other image frame; for a display area with a refresh frequency of 1Hz, one image frame may be selected from every sixty image frames, in which image frame the image data corresponding to the display area is read, and in the remaining fifty-nine image frames the image data is not read.

The image output module 20 may acquire refresh frequencies corresponding to different display areas, respectively, and read part of the image data from the plurality of image data output from the front-end processor to the driving chip 10.

The image output module 20 may generate a corresponding data signal according to the read partial image data. For example, the image data includes a display screen of a single image frame, and the image output module 20 may generate data signals respectively corresponding to the light emitting sub-pixels of each pixel row according to the image data.

In this embodiment, the image output module 20 and the image registering module 50 are configured to be capable of storing a plurality of image data output by the front-end processor 60 through the image registering module 50, and acquiring refresh frequencies of a plurality of display areas from an instruction sent from the front-end processor 60 through the image output module 20, and the image output module 20 may read a part of the image data from the plurality of image data stored in the image registering module 50 according to the refresh frequencies of the plurality of display areas, and generate a data signal corresponding to the part of the image data. Since the image output module 20 can read part of the image data in the plurality of image data according to the refresh frequency of different display areas, when the refresh frequency of a part of the display areas is low, the image output module may not read the corresponding image data when the part of the display areas is located in the holding frame, and also may not generate the data signal corresponding to the part of the image data. Since the driving chip 10 in a single image frame only needs to generate the corresponding data signal for a part of the image data among the plurality of image data, the power consumption of the driving chip 10 can be reduced.

In some embodiments, the plurality of display regions may include a first display region and a second display region, where a refresh frequency corresponding to the first display region is higher than a refresh frequency corresponding to the second display region. The image output module 20 may read a portion of the plurality of image data from the image registration module 50, which is the image output module 20 reads the image data corresponding to the first display area from the image registration module 50.

Since the refresh frequency of the first display area is higher than that of the second display area, the number of data writing frames of the first display area is greater than that of the second display area in the same time interval. Taking a single image frame as an example, the first display area is in the data writing frame and the second display area is in the holding frame, the image output module 20 may read the image data corresponding to the first display area from the image registering module 50, but not read the image data corresponding to the second display area.

Referring to fig. 2, in some embodiments, the driving chip 10 may further include a gate dynamic control module 30, and the gate dynamic control module 30 is coupled to the image output module 20.

After the image output module 20 obtains the refresh frequencies respectively corresponding to the different display areas and reads part of the image data in the plurality of image data, a control signal may be generated based on the refresh frequencies of the plurality of display areas and the read image data.

The gate dynamic control module 30 may receive the control signal generated by the image output module 20 and generate the scan driving control signal having a corresponding timing in response to the control signal. The gate driving circuit can sequentially output a plurality of scan signals based on the scan driving control signal. Wherein the frequencies of the conducting pulses in at least two scanning signals are different.

Taking a single image frame as an example, after determining the refresh frequencies corresponding to the different display areas, the image output module 20 may determine whether each display area in the image frame needs to be refreshed according to the refresh frequency of each display area, and generate a corresponding control signal.

The gate dynamic control module 30 may generate a scan driving control signal having a corresponding timing when receiving the control signal, and transmit the scan driving control signal to the gate driving circuit. The gate driving circuit can sequentially output a plurality of scanning signals according to the scanning driving signal, and adjust the on pulse in each scanning signal.

As an alternative embodiment, taking a single image frame as an example, the image output module 20 may generate the control signal after determining the display area under the image frame that needs to be refreshed and reading a portion of the image data. The gate dynamic control module 30 may generate a scan driving control signal based on the control signal. When the gate driving circuit provides the scanning signals for the pixel rows respectively, the scanning signals containing the conducting pulses can be output for the display areas needing to be refreshed according to the scanning driving control signals, and the gate driving circuit does not output the scanning signals or does not contain the conducting pulses in the output scanning signals for the display areas which do not need to be refreshed in the image frame.

In an exemplary embodiment, taking a single image frame with a period of sixty-one second as an example, the different display areas include two display areas, and the refresh frequency may be 60Hz and 30Hz, respectively. For a display area with a refresh frequency of 60Hz, the refresh of the image frame is required in the image frame. For a display area with a refresh frequency of 30Hz, it is necessary to determine whether the refresh of the image frame is required in the image frame according to the adjacent image frames. For example, a refresh rate of 30Hz indicates that 30 data write frames and 30 hold frames are included in one second. The data writing frames and the holding frames may be alternately arranged at intervals or may be arranged at random. For example, in 60 consecutive frames, the data writing frames and the holding frames may be alternately arranged at intervals, and the holding frames may be arranged between any two data writing frames, and the data writing frames may be arranged between any two holding frames. In this arrangement, whether or not the refresh of the image frame is required in a single image frame can be determined from adjacent image frames for a display area with a refresh frequency of 30Hz. For example, if the display area in the previous image frame is refreshed, the image frame is not refreshed any more. In contrast, when the refresh of the image frame is not performed in the previous image frame, the refresh of the image frame is performed in the image frame.

In another implementation of the refresh rate, for example, when the 60 consecutive frames include 30 consecutive data writing frames and 30 consecutive holding frames for a display area with a refresh rate of 30Hz, the determination of whether the refresh of the image frame is required in a single image frame may be performed according to the consecutive number of data writing frames before and after the image frame or the consecutive number of holding frames.

The gate dynamic control module 30 may be connected to a plurality of gate driving circuits arranged in cascade, and the gate dynamic control module 30 may be capable of receiving the control signal generated by the image output module 20 in a single image frame.

The gate dynamic control module 30 may generate a scan driving control signal having a corresponding timing based on the control signal, and the scan driving control signal may be formed by combining high and low level signals. One of the high and low level signals is an active signal and the other is an inactive signal. The plurality of gate driving circuits may sequentially output a plurality of scan signals, and determine whether the output scan signals include a turn-on pulse based on the scan driving control signal. For example, when the plurality of gate driving circuits output the scan signals line by line, if the scan driving control signal is an effective signal, the gate driving circuit outputs the scan signals for the corresponding pixel lines; if the scan driving control signal is an inactive signal, the gate driving circuit does not output a scan signal for the corresponding pixel row or the output scan signal does not include a turn-on pulse.

After determining a partial display area in a single image frame, which needs to be refreshed, a partial pixel row corresponding to the partial display area may be determined. In a single image frame, the plurality of gate driving circuits may supply the scan signals to the portion of the pixel rows without supplying the scan signals to the remaining pixel rows or without including the on pulse in the scan signals supplied to the remaining pixel rows. That is, the plurality of gate driving circuits may supply only a part of the pixel rows with effective scan signals in a single image frame according to the scan driving control signal.

In some embodiments, the plurality of display regions may include a first display region and a second display region, where the refresh frequency corresponding to the first display region is higher than the refresh frequency corresponding to the second display region, and the frequency of the on pulse in the scan signal corresponding to the first display region is greater than the frequency of the on pulse in the scan signal corresponding to the second display region.

The refresh frequency of the first display area is higher than that of the second display area, and the number of on pulses in the scanning signals received by the first display area is larger than that of the second display area in the same time interval. That is, the frequency of the on pulse in the scan signal corresponding to the first display region is greater than the frequency of the on pulse in the scan signal corresponding to the second display region.

Taking a time interval of 1 second as an example, for any pixel row in a display area with a refresh frequency of 60Hz, the frequency of the on pulse in the scan signal received in 1 second is 60Hz; and for any pixel row in the display area where the refresh frequency is 30Hz, the frequency of the on pulse in the scan signal received within 1 second is 30Hz.

Referring to fig. 3, in some embodiments, the driving chip 10 may further include a source dynamic control module 40, and the source dynamic control module 40 is coupled to the image output module 20.

After the image output module 20 obtains the refresh frequencies respectively corresponding to the different display areas, the data driving control signal may be generated based on the refresh frequencies of the plurality of display areas. When the image output module 20 reads a part of image data among the plurality of image data from the image registering module 50 and generates a corresponding data signal, the source dynamic control module 40 may respond to the data driving control signal and maintain the signal voltage of other data signals than the data signal generated by the image output module 20 unchanged.

When the gate driving circuit corresponding to the partial display region supplies the scan signal to the pixel row corresponding to the partial display region, the image output module 20 normally supplies the data signal through the data signal line. The source dynamic control module 40 can maintain the signal voltage of the data signal unchanged when the gate driving circuit does not output the scan signal. For example, if a display area of the display panel includes light-emitting sub-pixels of 11 th to 20 th pixel rows, and the light-emitting sub-pixels of the partial pixel rows do not refresh an image frame in the image frame, the gate driving circuit supplies scanning signals for 1 st to 10 th pixel rows line by line in a single image frame, and does not output the scanning signals for 11 th to 20 th pixel rows. The source dynamic control module 40 may start from the 11 th pixel row, maintain the signal voltage of the data signal unchanged, and until the gate driving circuit provides the scanning signal for the 21 st pixel row, the image output module 20 may not provide the corresponding data signal for each light emitting sub-pixel of the 21 st pixel row according to the image content of the 21 st pixel row in the image data.

It should be noted that the plurality of gate driving circuits may be connected in cascade, and the scanning signal output by the gate driving circuit may be transmitted to the light emitting sub-pixels in the same row through the scanning signal line and transmitted to the next gate driving circuit. In the 11 th pixel row to the 20 th pixel row, the gate driving circuit does not output a scanning signal, that is, the scanning signal generated by the gate driving circuit is not output to the scanning signal line, so that the light emitting sub-pixels in the same row cannot receive the effective signal of the scanning signal. The next gate drive circuit can still receive the valid signal of the scan signal so that the plurality of gate drive circuits can continue generating valid signals of the scan signal row by row. In the above embodiment, in the 21 st pixel row, the scan driving control signal received by the gate driving circuit is the valid signal, and at this time, the gate driving circuit can transmit the valid signal of the scan signal to the light emitting sub-pixels of the same row through the scan signal line, so that the 21 st pixel row can receive the scan signal again.

Taking a single image frame as an example, the gate dynamic control module 30 and the source dynamic control module 40 can determine a part of display areas and a corresponding part of pixel rows, which need to refresh an image picture, in the image frame according to refresh frequencies of different display areas. The partial pixel row can normally receive a scan signal and a data signal. The other pixel rows cannot receive the valid signal of the scan signal, and the signal voltage of the data signal provided by the source dynamic control module 40 will also remain unchanged. That is, for a portion of the pixel rows that receive the scan signal and the data signal, the image frame is a data write frame. And for other pixel rows for which no valid signal of the scan signal is received, the image frame is a hold frame. By adjusting the pixel rows in the data writing frame and the pixel rows in the holding frame in each image frame, the refresh frequency adjustment of the individual pixel rows can be achieved. That is, the refresh frequencies of any two pixel rows can be independently adjusted. When the displayed image content has the requirement of partitioned multi-screen display, the refresh frequency of different display areas can be flexibly adjusted, so that each display area can display the image content by adopting the proper refresh frequency.

Note that since the light emitting sub-pixels of the same pixel row receive the same scanning signal, the light emitting sub-pixels of the same pixel row have the same refresh frequency. That is, when dividing the display area, the division may be performed by pixel row.

Taking a single data signal line as an example, when the gate driving circuit outputs the scan signal line by line, the driving chip 10 needs to continuously adjust the signal voltage on the data signal line, so that the light emitting sub-pixels in the same column can sequentially receive the corresponding data signal when the scan signal is output line by line. When the driving chip 10 adjusts the signal voltage of the data signal row by row, the voltage jump of the data signal will generate a certain power consumption. The power consumption generated by the transitions of the data signal is usually the main component of the display power consumption of the driving chip 10. The source dynamic control module 40 can maintain the signal voltage of the data signal unchanged when the gate driving circuit does not output the scan signal, for example, in the embodiment described above, the signal voltage of the data signal output by the driving chip 10 through each data signal line can be maintained unchanged from the 11 th pixel row to the 20 th pixel row, so as to save the power loss generated by the data signal jump, reduce the power consumption generated by the source driving circuit in the driving chip 10, and realize the reduction of the display power consumption.

In some embodiments, the driving chip 10 may further include a plurality of data output modules 70. As shown in fig. 4, fig. 4 shows a schematic diagram of the connection of a single data output module 70 within the driver chip 10.

The image output module 20 is connected to the data output module 70 through the digital-to-analog conversion module 80, and outputs a corresponding data signal to the data output module 70. The digital-to-analog conversion module 80 may convert the data signal output from the image output module 20 from a digital signal to an analog signal.

The plurality of data output modules 70 are respectively connected to the corresponding signal fanout lines Fan. The single data output module 70 may include one first data signal port and at least one second data signal port. The first data signal port is capable of providing a data signal corresponding to a portion of the image data read by the image output module 20. That is, the driving chip 10 can adjust the data voltage output from the first data signal port according to the partial image data read by the image output module 20 to provide the corresponding data signal for each light emitting sub-pixel. The second data signal port is capable of providing a data signal of a portion of the image data that is not read by the image output module 20.

As shown in fig. 4, the first data signal port of the data output module 70 may perform signal amplification through the amplifier op1 to improve the driving capability of the data signal. Likewise, the second data signal port may perform signal amplification through the amplifier op2 to enhance the driving capability of the data signal.

The source dynamic control module 40 can maintain the signal voltage of the data signal unchanged when the gate driving circuit does not output the scan signal. The manner of maintaining the signal voltage unchanged may include the following two ways:

in a first manner, the source dynamic control module 40 may control the signal voltage of the first data signal port to remain unchanged. For example, when the scan signal is not provided from the 11 th pixel row to the 20 th pixel row, the first data signal port may provide a corresponding data signal for the 10 th pixel row, and the source dynamic control module 40 may control the signal voltage output by the first data signal port to remain as the data signal corresponding to the 10 th pixel row until the gate driving circuit provides the scan signal for the 21 st pixel row, and the driving chip 10 adjusts the signal voltage output by the first data signal port to be the data signal corresponding to the 21 st pixel row.

In a second manner, the source dynamic control module 40 may change the data signal port connected to the signal fanout line Fan from the first data signal port to the second signal port. At this time, the data signal provided by the signal Fan-out line Fan is the fixed voltage signal output by the second signal port. For example, when the scan signal is not supplied from the 11 th pixel row to the 20 th pixel row, the source dynamic control module 40 may communicate the second data signal port with the signal Fan line Fan to supply the data signal with the fixed voltage for the 11 th pixel row to the 20 th pixel row. The driving chip 10 disconnects the second data signal port from the signal fanout line Fan and reconnects the first data signal port to the signal fanout line Fan until the gate driving circuit supplies the scan signal to the 21 st pixel row, so as to supply the data signal corresponding to the 21 st pixel row through the first data signal port.

It is understood that the number of the signal fanout lines Fan may be consistent with the number of the data signal lines in the display device when the multi-gate module is not provided in the display device. When the multi-path gating module is arranged in the display device, the number of the signal Fan-out lines Fan is different from the number of the data signal lines in the display device, and a single signal Fan-out line Fan can be connected with a plurality of data signal lines through the multi-path gating module and provides data signals for the plurality of data signal lines in a time division multiplexing mode.

In some embodiments, the driving chip 10 may further include the gate dynamic control module 30 and the source dynamic control module 40 in the above embodiments.

By providing the gate dynamic control module 30 and the source dynamic control module 40, the scan driving control signal under each image frame can be generated according to the refresh frequency of different display regions. For a portion of the display area in the single image frame that needs to be refreshed, the scan driving control signal may drive the gate dynamic control module 30 to provide a scan signal for a pixel row corresponding to the portion of the display area, and not output a scan signal for other pixel rows. Accordingly, for the pixel rows that do not receive the scan signal, the source dynamic control module 40 may maintain the signal voltage of the supplied data signal unchanged, so as to reduce the power consumption generated by the data signal jump, and realize the reduction of the display power consumption of the driving chip 10.

The embodiment of the application also provides a display device, as shown in fig. 5, which comprises a display area 1 and a non-display area 2. The display area 1 includes a plurality of light emitting sub-pixels 11 arranged in an array, and the non-display area 2 includes a driving chip 10, a plurality of gate driving circuits GIP, and a scan driving control signal line OE. The gate dynamic control module 30 of the driving chip 10 may be connected to the plurality of gate driving circuits GIP through the scan driving control signal line OE.

Each of the plurality of gate driving circuits GIP is electrically connected to the corresponding light emitting sub-pixel 11 of the same row. In a single image frame, the plurality of gate driving circuits GIP can output effective signals of the scan signals line by line so that each pixel line can receive the data signals line by line.

The scan driving control signal line OE may extend in the non-display region and be connected to the plurality of gate driving circuits GIP, respectively.

The gate dynamic control module 30 may output a scan driving control signal through a scan driving control signal line OE in a single image frame. The scan driving control signal may be a high-low level signal. Taking the high level signal as an active signal as an example, the plurality of gate driving circuits GIP can each receive the scan driving control signal. When the gate driving circuit GIP outputs the scan signal line by line, if the scan driving control signal received by the gate driving circuit GIP is an active signal, for example, a high level signal, the gate driving circuit GIP normally outputs the active signal of the scan signal to the scan signal line and supplies the active signal to the light emitting sub-pixels 11 of the same line through the scan signal line. The row of light emitting sub-pixels 11 receives a scanning signal in the image frame, which is the data writing frame of the row of light emitting sub-pixels 11.

If the scan driving control signal received by the gate driving circuit GIP is an inactive signal, the gate driving circuit GIP does not output an active signal of the scan signal to the scan signal line, and the row of light emitting sub-pixels 11 does not receive the scan signal in the image frame, which is a holding frame of the row of light emitting sub-pixels 11.

In the present embodiment, by providing the scan drive control signal line OE to be connected to the plurality of gate drive circuits GIP, selective output of the scan signal can be achieved by the scan drive control signal. By adjusting the effective level interval and the non-effective level interval of the scan driving control signal, the gate driving circuit GIP can output the scan signal only in the effective level interval of the scan driving control signal and not in the non-effective level interval of the scan driving control signal in a single image frame, thereby realizing flexible switching of the data writing frame and the holding frame of each pixel line in a single image frame. By setting the ratio of the data writing frame to the holding frame for each pixel row in a certain number of image frames, individual adjustment of the refresh frequency of each pixel row can be achieved. So that the display device can partition according to the actual image content and flexibly adjust the refresh frequency of each partition.

Referring to fig. 5, in some embodiments, the gate driving circuits GIP may be cascaded in turn, and an output terminal of each gate driving circuit GIP is connected to a corresponding scan signal line. The gate driving circuit GIP may include a dynamic control module DCM, a first end of the dynamic control module DCM is connected to an output end of the gate driving circuit GIP, and a second end of the dynamic control module DCM is connected to a scan signal line. The control end of the dynamic control module DCM is connected with a scanning drive control signal line OE.

When the scan driving control signal received by the dynamic control module DCM is an effective signal, the first end and the second end may be connected, so that the scan signal generated by the gate driving circuit GIP may be output to the scan signal line through the output end, and further be provided to the light emitting sub-pixels 11 in the same row.

When the scan driving control signal received by the dynamic control module DCM is an inactive signal, the first terminal and the second terminal may be disconnected, and the gate driving circuit GIP does not output the scan signal.

The gate driving circuits GIP may be sequentially cascaded, and when the previous gate driving circuit GIP generates the valid signal of the scan signal, the valid signal of the scan signal may be transmitted to the next gate driving circuit GIP to drive the next gate driving circuit GIP to generate the valid signal of the scan signal. It should be noted that, the dynamic control module DCM does not affect the cascade connection of the upper and lower gate driving circuits GIP, i.e., when the dynamic control module DCM is turned on or off, the latter gate driving circuit GIP can receive the valid signal of the scan signal generated by the former gate driving circuit GIP.

The embodiment of the application also provides a partitioned multi-frequency display method of the display device, and the display device at least comprises a display panel, wherein the display panel is provided with a plurality of display areas in the embodiment. FIG. 7 is a flow chart illustrating a partitioned multi-frequency display according to an embodiment of the present application. The zoned multi-frequency display method comprises the following steps:

s110, acquiring refresh frequencies of a plurality of image data and a plurality of display areas;

s120, according to the refresh frequency of each display area, reading part of the plurality of image data and generating corresponding data signals.

The method for displaying the display device in the partitioned multi-frequency mode provided by the embodiment of the application can be applied to the display device in the embodiment. The display device may be a PC, a television, a smart terminal or a tablet computer, etc. The specific form of the display device is not limited in this embodiment.

In this embodiment, by acquiring the refresh frequencies of the plurality of image data and the plurality of display regions, it is possible to read a part of the image data in the plurality of image data according to the refresh frequency of each display region, and when the refresh frequency of a part of the display region is low, the display device may not read the corresponding image data when the part of the display region is located in the hold frame, thereby reducing power consumption of the display device.

In S110, the driving chip of the display device may acquire image data of an image to be displayed and refresh frequencies of a plurality of display areas from the front-end processor.

The front-end processor can divide the whole display area of the display panel according to the image content actually displayed, and respectively set the same or different refresh frequencies for the divided display areas. When the front-end processor stores the image data in the image registering module of the driving chip, the positional relationship of each display area and the refresh frequency of each display area may also be provided to the driving chip.

In S120, the driving chip of the display device may read a portion of image data from the plurality of image data stored in the image register module according to the read refresh frequency of each display area, and generate a data signal corresponding to the portion of image data.

When the driving chip reads part of image data from the plurality of image data according to the refresh frequency of each display area and only generates a data signal corresponding to the part of image data, the driving chip only needs to generate a corresponding data signal for the part of image data in the plurality of image data, so that the power consumption of the driving chip can be reduced.

As an alternative embodiment, after S110, the method may further include:

s210, generating a scanning driving control signal according to the refresh frequency of each display area;

s220, responding to the scanning driving control signals and sequentially outputting a plurality of scanning signals; wherein the frequencies of the conducting pulses in at least two scanning signals are different;

in this embodiment, by acquiring the remaining refresh frequencies of different displays, a corresponding scan driving control signal may be generated, and the frequencies of the on pulses of the scan signals output by different scan signal lines may be adjusted according to the scan driving control signal, so that each display area receives the on pulse corresponding to the refresh frequency.

In S210, after the display device obtains refresh frequencies respectively corresponding to different display regions, a scan driving control signal may be generated based on the refresh frequencies of the plurality of display regions.

Taking a single image frame as an example, after determining the refresh frequencies corresponding to different display areas, the display device may determine, according to the refresh frequency of each display area, whether each display area in the image frame needs to be refreshed, and generate a corresponding scan driving control signal.

In S220, when the gate dynamic control module of the display device receives the scan driving control signal, the gate dynamic control module may provide a scan signal for a portion of the display area that needs to be refreshed in the image frame, and another portion of the display area that does not need to be refreshed in the image frame does not output the scan signal or does not include a turn-on pulse in the output scan signal.

It will be appreciated that, in the same time interval, if the refresh frequencies of the two display areas are different, the number of on pulses included in the scan signals received by the two display areas in the same time interval is also different. The different numbers of the on pulses at the same time indicate different frequencies of the on pulses in the scan signals corresponding to the two display areas respectively.

The number of on pulses in the scan signal received by the first display area is greater than the number of on pulses in the scan signal received by the second display area. That is, the frequency of the on pulse in the scan signal corresponding to the first display region is greater than the frequency of the on pulse in the scan signal corresponding to the second display region.

The gate dynamic control module may include a plurality of gate driving circuits arranged in cascade, and in a single image frame, the gate dynamic control module may be capable of receiving the scan driving control signals generated by the image output module.

The scan driving control signal may be formed by combining high and low level signals. One of the high and low level signals is an active signal and the other is an inactive signal. When the plurality of gate driving circuits output scanning signals row by row, if the scanning driving control signals are effective signals, the gate driving circuits output scanning signals for corresponding pixel rows; if the scan driving control signal is an inactive signal, the gate driving circuit does not output a scan signal for the corresponding pixel row.

After determining a part of display area needing to be refreshed in an image frame, the grid dynamic control module can determine a part of pixel rows corresponding to the part of display area. In a single image frame, the gate dynamic control module may provide scan signals for the portion of the pixel rows without providing scan signals for the remaining pixel rows or without including on pulses in the scan signals provided for the remaining pixel rows. That is, the gate dynamic control module may provide an effective scan signal for only a portion of the pixel rows in a single image frame according to the scan driving control signal.

As an alternative embodiment, after S110, the method may further include:

s310, generating a data driving control signal according to the refresh frequency of each display area;

s320, in response to the data driving control signal, maintaining the voltage of the data signals except for the corresponding data signal unchanged.

In this embodiment, the display device may also maintain the signal voltage unchanged for the data signal of the portion of the display area that does not need to perform image refresh by generating the data driving control signal according to the refresh frequency of each display area, so as to reduce the power consumption generated by the data signal jump, and realize the reduction of the display power consumption of the display device.

In S310, after the image output module 20 acquires the refresh frequencies respectively corresponding to the different display areas, the data driving control signal may be generated based on the refresh frequencies of the plurality of display areas.

In S320, when the image output module 20 reads part of the image data among the plurality of image data from the image registering module 50 and generates the corresponding data signal, the source dynamic control module 40 may respond to the data driving control signal and maintain the signal voltage of the other data signals except the data signal generated by the image output module 20 unchanged.

As an alternative embodiment, the driving chip of the display device is electrically connected to a front-end processor, which may provide the refresh frequency of each display area to the driving chip when transmitting image data.

The driving chip can determine partial display areas to be refreshed in a single image frame according to the obtained refresh frequencies of different display areas.

Taking a whole screen display area as an example, dividing the whole screen display area into two display areas, wherein the refresh frequency is respectively 60Hz and 1Hz, and when the period of a single image frame is sixty-one second, refreshing an image picture of the display area with the refresh frequency of 60Hz under each image frame; for a display area with a refresh frequency of 1Hz, it is necessary to update the image frame only under one of the 60 consecutive image frames. Thus, of 60 consecutive image frames, only one image frame has two display areas each being a display area to be refreshed, and the other 59 image frames have only a display area with a refresh frequency of 60Hz being a partial display area to be refreshed.

After determining the partial display area to be refreshed in a single image frame, the partial image data corresponding to the partial display area to be refreshed can be read from the whole frame of image data stored in the image register module.

Taking 60Hz and 1Hz as examples in the above embodiment, of 60 consecutive image frames, only one image frame reads the whole frame of image data stored in the image registration module, and of the remaining 59 image frames, all the image frames read the partial image data corresponding to the display area of 60Hz from the whole frame of image data.

As an alternative embodiment, after determining the refresh frequency of the different display areas, the corresponding first pixel row may be determined according to the portion of the display area to be refreshed in the single image frame.

Taking the example that the display panel is divided into three display areas, according to the refresh frequency of the three display areas, in determining a certain image frame, two display areas are partial display areas to be refreshed, and then the pixel rows contained in the two display areas are the first pixel rows. For example, the display panel includes 1000 pixel rows, and three display areas are respectively 1 st pixel row to 100 th pixel row, 101 st pixel row to 500 th pixel row, and 501 st pixel row to 1000 th pixel row. According to the refresh frequency of the three display areas, in a certain image frame, the first display area and the third display area are the display areas to be refreshed, and then the first pixel row corresponding to the partial display area is from the 1 st pixel row to the 100 th pixel row and from the 501 st pixel row to the 1000 th pixel row.

After determining the first pixel row in the single image frame, a scan drive control signal may be generated according to the position of the first pixel row, the scan drive control signal being capable of driving the gate drive circuit to provide a scan signal for the first pixel row.

The scan driving control signal may be composed of high and low level signals, and in an example of the high level signal as an effective signal, the scan driving control signal may correspond to a timing at which each gate driving circuit outputs the scan signal in a time period of a single image frame. In the example of the pixel rows 1 to 100 and 501 to 1000 in the above embodiment, the scan driving control signal may be divided into 1000 time intervals in the time length of a single image frame, and the scan driving control signal is a high-level effective signal in the time intervals corresponding to the pixel rows 1 to 100 and 501 to 1000 respectively. The scan driving control signal is a low-level inactive signal in a time period corresponding to the 101 st pixel row to the 500 th pixel row.

When the grid driving circuit outputs scanning signals row by row, if the scanning driving control signals received by the grid driving circuit outputting the scanning signals are effective signals, the grid driving circuit normally outputs the effective signals of the scanning signals; if the scanning driving control signal received by the grid driving circuit is an inactive signal, the grid driving circuit does not output the scanning signal. Therefore, in the above embodiment, in a single image frame, the 1 st pixel row to the 100 th pixel row and the 501 st pixel row to the 1000 th pixel row can receive the scan signal, and the 101 st pixel row to the 500 th pixel row cannot receive the valid signal of the scan signal.

The driving chip of the display device may generate data signals corresponding to the light emitting sub-pixels of each first pixel row according to the image data when the gate driving circuit provides the scanning signals for each first pixel row, and provide the data signals to each first pixel row, so as to realize refreshing of the image picture of each first pixel row in a single image frame. That is, in the image frame, the light-emitting sub-pixels in each first pixel row receive a new data signal and emit light according to the new data signal; the light emitting sub-pixels of the remaining pixel rows continue to emit light using the data signals in the previous image frame.

As an alternative embodiment, after determining a portion of the display area to be refreshed in a single image frame according to the refresh frequency of different display areas and determining a first pixel row included in the portion of the display area, the second pixel row may be determined according to the first pixel row. The second pixel row is the pixel row in the image frame that does not receive the scan signal and the data signal.

In a single image frame, after the first pixel row is determined, the other pixel rows are the second pixel rows. For example, when the display panel includes 1000 pixel rows, if the 1 st pixel row to the 100 th pixel row and the 501 st pixel row to the 1000 th pixel row are the first pixel row, the 101 st pixel row to the 500 th pixel row are the second pixel row.

The driving chip can adjust the provided data signals into the data signals with unchanged signal voltage when the data signals are provided for each second pixel row, so as to reduce the power consumption generated by data signal jumping.

When the driving chip supplies the data signals to the second pixel rows, the mode of maintaining the signal voltage of the data signals unchanged may be to adjust the data signals corresponding to the second pixel rows to the data signals of the nearest first pixel rows, or to adjust the data signals corresponding to the second pixel rows to the fixed potential signals.

The driving chip adjusts the data signals corresponding to the second pixel rows to the data signals of the nearest first pixel row, which means that the driving chip generates the data signals according to the image content corresponding to the second pixel row, but not the image content corresponding to the nearest first pixel row before the second pixel row when the driving chip provides the data signals for the second pixel row.

Taking a single data signal line as an example, when the 1 st pixel row to the 10 th pixel row are the first pixel row, the 11 th pixel row to the 20 th pixel row are the second pixel row, and the driving chip can generate corresponding data voltages according to the image content corresponding to the 1 st pixel row to the 10 th pixel row when the driving chip provides data signals for the 1 st pixel row to the 10 th pixel row. In the 11 th pixel row, whether the data signal changes or not does not affect the light emitting brightness of the light emitting sub-pixels in the 11 th pixel row because the 11 th pixel row does not receive the scanning signal, so as to reduce the transition frequency of the data signal and reduce the display power consumption of the driving chip, the driving chip can keep the signal voltage of the data signal to be the signal voltage of the data signal of the 10 th pixel row when the data signal is provided for the 11 th pixel row. Similarly, when the driving chip provides the data signals for the 12 th pixel row to the 20 th pixel row, the signal voltage of the data signals can be kept unchanged, so that the signal voltage of the data signals is kept unchanged all the time in the time interval corresponding to the 11 th pixel row to the 20 th pixel row, the jump times of the data signals in a single image frame are greatly reduced, and the data signal driving power consumption of the driving chip is reduced.

In this embodiment, after determining the first pixel row corresponding to the single image frame, the remaining pixel rows are the second pixel rows. When the driving chip supplies the data signals to the second pixel rows, the driving chip can supply the data signals with the same voltage to the plurality of continuous second pixel rows so as to reduce the jump times of the data signals and reduce the driving power consumption.

In another embodiment, the driving chip may directly adjust the data signals corresponding to the second pixel rows to be fixed potential signals, and in this case, the signal voltages of the data signals in the consecutive second pixel rows are kept unchanged, so that the data signal driving power consumption of the driving chip can be reduced.

It should be noted that, for a portion of pixel rows in a single image frame that do not need to be refreshed, whether the data signals corresponding to the portion of pixel rows are kept to be adjusted to be fixed potential signals or the data signals with the same voltage are provided for the continuous pixel rows in the portion of pixel rows, compared with the embodiment that reads image data and generates corresponding data signals but does not provide the corresponding data signals to the pixel rows in the related art, the transition times of the data signals can be reduced, so as to reduce the driving power consumption.

The embodiment of the application also provides a display device which at least comprises a display panel, a storage medium, a front-end processor and a driving chip.

The display panel includes a plurality of display areas in the above-described embodiments, the storage medium stores computer program instructions, and the front-end processor is capable of outputting a plurality of image data in the above-described embodiments and executing the computer program instructions.

The driving chip may be the driving chip in the above-described embodiment. The driving chip may perform the partitioned multi-frequency display method of the display device in the above embodiment in response to the computer program instructions to implement the partitioned multi-frequency display of the display panel.

Fig. 8 is a schematic diagram of a hardware structure of a partitioned multi-frequency display device according to an embodiment of the present application.

The partitioned multi-frequency display device may include a processor 801 and a memory 802 storing computer program instructions.

In particular, the processor 801 may include a Central Processing Unit (CPU), or an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or may be configured as one or more integrated circuits that implement embodiments of the present application.

Memory 802 may include mass storage for data or instructions. By way of example, and not limitation, memory 802 may include a Hard Disk Drive (HDD), floppy Disk Drive, flash memory, optical Disk, magneto-optical Disk, magnetic tape, or universal serial bus (Universal Serial Bus, USB) Drive, or a combination of two or more of the above. Memory 802 may include removable or non-removable (or fixed) media, where appropriate. The memory 802 may be internal or external to the partitioned multi-frequency display device, where appropriate. In a particular embodiment, the memory 802 is a non-volatile solid-state memory.

In particular embodiments, memory 802 may include Read Only Memory (ROM), random Access Memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software comprising computer-executable instructions and when the software is executed (e.g., by one or more processors) it is operable to perform the operations described with reference to methods in accordance with aspects of the present disclosure.

The processor 801 implements any of the partitioned multi-frequency display methods of the above embodiments by reading and executing computer program instructions stored in the memory 802.

In one example, the partitioned multi-frequency display device may also include a communication interface 803 and a bus 810. As shown in fig. 8, the processor 801, the memory 802, and the communication interface 803 are connected to each other via a bus 810 and perform communication with each other.

Communication interface 803 is primarily used to implement communication between modules, devices, units, and/or apparatuses in an embodiment of the present application.

Bus 810 includes hardware, software, or both, that couple the components of the partitioned multi-frequency display device to one another. By way of example, and not limitation, the buses may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an infiniband interconnect, a Low Pin Count (LPC) bus, a memory bus, a micro channel architecture (MCa) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus, or a combination of two or more of the above. Bus 810 may include one or more buses, where appropriate. Although embodiments of the application have been described and illustrated with respect to a particular bus, the application contemplates any suitable bus or interconnect.

In addition, in combination with the partitioned multi-frequency display method in the above embodiment, the embodiment of the application may be implemented by providing a computer storage medium. The computer storage medium has stored thereon computer program instructions; the computer program instructions, when executed by a processor, implement any of the partitioned multi-frequency display methods of the above embodiments.

It should be understood that the application is not limited to the particular arrangements and instrumentality described above and shown in the drawings. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after appreciating the spirit of the present application.

The functional blocks shown in the above block diagrams may be implemented in hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, a plug-in, a function card, or the like. When implemented in software, the elements of the application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine readable medium or transmitted over transmission media or communication links by a data signal carried in a carrier wave. A "machine-readable medium" may include any medium that can store or transfer information. Examples of machine-readable media include electronic circuitry, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and the like. The code segments may be downloaded via computer networks such as the internet, intranets, etc.

It should also be noted that the exemplary embodiments mentioned in this disclosure describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, or may be performed in a different order from the order in the embodiments, or several steps may be performed simultaneously.

Aspects of the present disclosure are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to being, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware which performs the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In the foregoing, only the specific embodiments of the present application are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present application is not limited thereto, and any equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the present application, and they should be included in the scope of the present application.

Claims

1. The driving chip is characterized by at least comprising an image registering module and an image output module, wherein the image registering module is coupled with the image output module, and the driving chip comprises:

the image output module is configured to read a part of the plurality of image data from the image register module according to refresh frequencies of a plurality of display areas carried in an instruction sent by the front-end processor, and generate corresponding data signals.

2. The driver chip of claim 1, wherein the plurality of display regions includes a first display region and a second display region, the refresh frequency corresponding to the first display region is higher than the refresh frequency corresponding to the second display region, the reading the portion of the plurality of image data from the image registration module includes:

3. The driver chip of claim 1, further comprising a gate dynamic control module coupled to the image output module, wherein:

the image output module is further configured to generate a control signal based on the refresh frequency of the plurality of display areas and the image data being read;

the grid dynamic control module is configured to respond to the control signals to generate scanning driving control signals with corresponding time sequences, so that the grid driving circuit sequentially outputs a plurality of scanning signals based on the scanning driving control signals, wherein the frequencies of conducting pulses in at least two scanning signals are different;

Preferably, the plurality of display areas include a first display area and a second display area, the refresh frequency corresponding to the first display area is higher than the refresh frequency corresponding to the second display area, and the frequency of the on pulse in the scan signal corresponding to the first display area is higher than the frequency of the on pulse in the scan signal corresponding to the second display area.

4. The driver chip of claim 1, further comprising a source dynamic control module coupled to the image output module, wherein:

the source dynamic control module is configured to maintain a voltage of a data signal other than the corresponding data signal unchanged in response to the data driving control signal.

5. The driver chip of claim 4, further comprising:

the data output modules are respectively connected with the plurality of signal fan-out lines and comprise a first data signal port and at least one second data signal port; the first data signal port is used for providing a data signal corresponding to the read image data, and the second data signal port is used for providing a data signal corresponding to the image data which is not read;

The source dynamic control module is used for controlling the signal voltage of the first data signal port to be unchanged under the condition that the grid driving circuit does not output a scanning signal, or switching the connection between the first data signal port and the signal fan-out line into the connection between the second data signal port and the signal fan-out line.

6. The driver chip of claim 1, further comprising a gate dynamic control module of claim 3 and a source dynamic control module of claim 4.

7. The driver chip of claim 4, further comprising:

8. A method of partitioned multi-frequency display of a display device, wherein the display device comprises at least a display panel having a plurality of display areas according to any one of claims 1-7, the method comprising at least:

and reading parts of the plurality of image data according to the refresh frequency of each display area, and generating corresponding data signals.

9. The method according to claim 8, wherein after the acquiring the plurality of image data and the refresh frequency of the plurality of display areas, further comprising:

sequentially outputting a plurality of scan signals in response to the scan driving control signal; wherein, the frequency of the conducting pulse in at least two scanning signals is different;

preferably, the plurality of display areas include a first display area and a second display area, the refresh frequency corresponding to the first display area is higher than the refresh frequency corresponding to the second display area, and the frequency of the on pulse in the scan signal corresponding to the first display area is higher than the frequency of the on pulse in the scan signal corresponding to the second display area;

Preferably, after the acquiring the refresh frequencies of the plurality of image data and the plurality of display areas, the method further includes:

in response to the data driving control signal, a voltage of the data signal other than the corresponding data signal is maintained unchanged.

10. A display device, the display device comprising at least:

a display panel having a plurality of display areas as claimed in any one of claims 1 to 7;

a storage medium configured to store computer program instructions;

a front-end processor configured to output a plurality of image data as claimed in any one of claims 1-7 and execute the computer program instructions; the method comprises the steps of,

the driver chip of any one of claims 1-7, configured to perform the partitioned multi-frequency display method of the display device of any one of claims 8-9 in response to the computer program instructions to achieve a partitioned multi-frequency display of the display panel.