KR102673949B1 - Gate driver, display device, display deviceand driving method for the same - Google Patents

Abstract

Embodiments of the present invention include a shift register that sequentially outputs shift signals, and a shift signal that receives the shift signals and sequentially supplies gate signals to a plurality of gate lines arranged in the first and second regions of the display panel. A gate driver including a switch unit that sequentially supplies a gate signal to the first area and the second area in a first period, and sequentially supplies a gate signal to the first area of the first area and the second area in a second period, A display device including the same and a manufacturing method thereof can be provided.

Description

Gate driver, display device and driving method thereof {GATE DRIVER, DISPLAY DEVICE, DISPLAY DEVICEAND DRIVING METHOD FOR THE SAME}

This specification relates to a gate driver, a display device, and a driving method thereof, and more specifically, to a gate driver, a display device, and a driving method thereof that can reduce power consumption and display various images.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, such as liquid crystal display devices (LCDs) and quantum dot light emitting displays (QLEDs). Various types of display devices such as OLED (Organic Light Emitting Display Device) are being used.

The display device displays an image by sequentially displaying a plurality of frames for a preset time. In addition, the display device can display photos, games, and videos. The greater the number of frames displayed during a preset time, that is, the shorter the time of one frame, the more naturally the games and videos displayed on the display device. You can.

When a display device operates at a single driving frequency, there is a problem in that unnecessary power consumption increases. Accordingly, the inventors of this specification have invented a gate driver, a display device, and a driving method thereof that can reduce power consumption by adjusting the driving frequency.

If the number of frames of an image displayed on a display device during a preset time increases, that is, the shorter the time of one frame, the display device has a problem of increasing power consumption. Also, when a still image such as a photo is displayed, the image displayed on the display device can be displayed naturally even if the number of frames displayed during the preset time is small. Therefore, there is no need to unnecessarily increase the number of frames when displaying a still image.

Additionally, when the display device is applied to a mobile device such as a smartphone or tablet PC, in order to reduce power consumption, after a certain period of time has elapsed after using the mobile device, the display device switches to a low-power display mode in which only simple information is displayed using low gradations. It can operate as . Low-power display mode also does not require increasing the number of frames displayed during a preset time.

Accordingly, the inventors of the present specification have invented a gate driver with a new structure, a display device, and a driving method thereof that can minimize power consumption by adjusting the number of frames of images displayed on the display device.

The problem according to an embodiment of the present specification is to provide a gate driver, a display device, and a method of driving the same that can reduce power consumption.

The problem according to an embodiment of the present specification is to provide a gate driver, a display device, and a driving method thereof that set a different driving frequency in response to a displayed image.

The problems to be solved according to an embodiment of the present specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment of the present specification is divided into at least a first area and a second area, and includes a display panel that displays images corresponding to different driving frequencies in the first area and the second area, respectively. In order to display images corresponding to different driving frequencies in the first and second areas on the display panel, the data driver and gate driver generate data signals and gate signals in response to the driving frequencies corresponding to the first and second areas. It is supplied to the first and second areas, and the data driver and gate driver are controlled by the timing controller.

The gate driver according to an embodiment of the present specification receives a shift register and shift signals that sequentially output shift signals, and sequentially supplies gate signals to a plurality of gate lines arranged in the first and second regions of the display panel. It includes a switch unit that does. The switch unit sequentially supplies gate signals to the first area and the second area in the first period, and sequentially supplies the gate signal to the first of the first and second areas in the second period.

A method of driving a display device according to an embodiment of the present specification displays an image corresponding to a first driving frequency in a first area of the display panel and performs a second driving frequency different from the first driving frequency in the second area of the display panel. Displays images according to frequency.

By providing a gate driver, a display device, and a driving method thereof according to an embodiment of the present specification, there is an effect of reducing power consumption.

Additionally, by using the gate driver, display device, and driving method described above, there is an effect that image quality does not deteriorate even when various images are displayed.

The effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a structural diagram showing the structure of a display device according to embodiments of the present invention.
Figure 2 is a circuit diagram showing a pixel according to embodiments of the present invention.
Figure 3 is a conceptual diagram showing an image displayed by dividing a screen in a display device according to embodiments of the present invention.
Figure 4 is a timing diagram showing a gate signal output in response to a driving frequency in a display device according to embodiments of the present invention.
Figure 5 is a graph comparing the power consumption of the display device when the driving frequency is 120Hz and when the driving frequency is 60Hz.
Figure 6 is a structural diagram showing a gate driver according to embodiments of the present invention.
7 and 8 are timing diagrams showing the operation of a gate driver according to embodiments of the present invention.
Figure 9 is a conceptual diagram showing a driving frequency selection signal corresponding to a different driving frequency for each area of the display device according to embodiments of the present invention.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and the present embodiments only serve to ensure that the disclosure of the present specification is complete and that common knowledge in the technical field to which the present specification pertains is provided. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as ‘after’, ‘after’, ‘after’, ‘before’, etc., ‘immediately’ or ‘directly’ Non-consecutive cases may also be included unless ' is used.

In the case of a description of the signal flow relationship, for example, 'a signal is transmitted from node A to node B', unless 'immediately' or 'directly' is used, it is transmitted from node A via another node. This may include cases where a signal is transmitted to the B node.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

Each feature of the various embodiments of the present specification can be combined or combined with each other, partially or entirely, and various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

1 is a structural diagram showing the structure of a display device according to embodiments of the present invention.

Referring to FIG. 1 , the display device 100 may include a display panel 110, a data driver 120, a gate driver 130, and a timing controller 140.

The display panel 110 may include a plurality of data lines (DL1 to DLm) extending in the first direction (A) and a plurality of gate lines (GL1 to GLn) extending in the second direction (B). Here, the first direction (A) and the second direction (B) are shown as perpendicular to each other, but are not limited thereto.

Additionally, the display panel 110 may include a plurality of pixels 101. The pixel 101 is connected to a data line and a gate line, and can operate by receiving a data signal transmitted through the connected data line in response to a gate signal transmitted through the connected gate line.

The display panel 110 is divided into at least a first area (110a) and a second area (110b), and the first area (110a) and the second area (110b) display images corresponding to different driving frequencies, respectively. You can. Among the first area (110a) and the second area (110b), the area with a high driving frequency is an area where the screen change is fast because the period of one frame is short, and the area with a low driving frequency is an area where the screen change is slow because the period of one frame is long. You can. Faster screen transitions increase power consumption, while in the case of videos or games, images can be displayed naturally.

The data driver 120 is connected to a plurality of data lines DL1 to DLm and can supply data signals to a plurality of pixels through the plurality of data lines DL1 to DLm. The data driver 120 may include a plurality of source drivers. Each of the plurality of source drivers may be implemented as an integrated circuit. The data signal transmitted by the data driver 120 may be applied to the pixel.

The gate driver 130 is connected to a plurality of gate lines GL1 to GLn and may supply gate signals to the plurality of gate lines GL1 to GLn. A pixel that receives a gate signal through a gate line can receive a data signal.

The gate driver 130 is shown as being disposed outside the display panel 110, but is not limited thereto, and the gate driver 130 may include a gate signal generator disposed on the display panel 110. . Additionally, the gate driver 130 may be implemented with a plurality of integrated circuits.

In addition, the gate driver 130 is shown as being disposed on one side of the display panel 110, but is not limited thereto. It is disposed on both sides of the display panel 110, and the gate driver disposed on the left is odd-numbered. The gate driver connected to the gate line and disposed on the right side of the display panel 110 may be connected to the even-numbered gate line.

The timing controller 140 can control the data driver 120 and the gate driver 130. The timing controller 140 may supply a data control signal to the data driver 120 and a gate control signal to the gate driver 130. The data control signal or gate control signal may include a clock, vertical synchronization signal, horizontal synchronization signal, and start pulse. However, the signal output from the timing controller 140 is not limited to this.

Additionally, the timing controller 140 may supply an image signal to the data driver 120. The data driver 120 can generate a data signal through the video signal and data control signal received from the timing controller 140 and supply the data signal to a plurality of data lines.

Figure 2 is a circuit diagram showing an example of a pixel according to embodiments of the present invention.

Referring to FIG. 2 , the pixel 101 may include a first transistor (M1), a second transistor (M2), a third transistor (M3), a storage capacitor (Cst), and an organic light emitting diode (OLED).

The first electrode of the first transistor M1 may be connected to the first node N1 through which the first power EVDD is transmitted, and the second electrode may be connected to the second node N2. The gate electrode of the first transistor (M1) may be connected to the third node (N3). The first transistor M1 may cause a driving current to flow to the second electrode by the first power source EVDD supplied to the first node N1 in response to the voltage delivered to the gate electrode.

The first electrode of the second transistor M2 may be connected to the reference voltage line VL2 that transmits the reference voltage Vref, and the second electrode may be connected to the third node N3. Additionally, the gate electrode of the second transistor M2 may be connected to the first gate line GL1 that supplies the first gate signal. The second transistor M2 may receive the first gate signal and supply the reference voltage transmitted to the reference voltage line VL2 to the gate electrode of the first transistor M1. The first gate signal may be supplied from the gate driver 130 shown in FIG. 1.

The first electrode of the third transistor M3 may be connected to the data line DL, and the second electrode may be connected to the second node N2. Additionally, the gate electrode of the third transistor M3 may be connected to the second gate line GL2. The third transistor M3 may receive the second gate signal and apply a data voltage corresponding to the data signal transmitted to the data line DL to the second electrode of the first transistor M1. The second gate signal may be supplied from the gate driver 130 shown in FIG. 1. Additionally, the data signal may be supplied from the data driver 120 shown in FIG. 1.

The first electrode of the storage capacitor Cst may be connected to the third node N3, and the second electrode may be connected to the second node N2. That is, the storage capacitor Cst is disposed between the gate electrode of the first transistor M1 and the second electrode of the first transistor M1. The voltage difference between the two electrodes can be maintained.

The anode electrode of the organic light emitting diode (OLED) may be connected to the second node (N2), and the cathode electrode may be connected to the second power source (EVSS). The voltage level of the second power source (EVSS) may be lower than the voltage level of the first power source (EVDD). Organic light-emitting diodes (OLEDs) can emit light in response to current flowing from the anode electrode to the cathode electrode. An organic light-emitting diode (OLED) may include a light-emitting layer that emits light by current flowing between an anode electrode and a cathode electrode. The light emitting layer may include an organic layer.

In the pixel 101 configured as described above, the first transistor M1 and the second transistor M2 may be N MOS type transistors, and the third transistor M3 may be a P MOS type transistor. However, it is not limited to this. Additionally, the first and second electrodes of the first to third transtors (M1 to M3) may be a drain electrode and a source electrode, respectively. However, it is not limited to this.

Additionally, the driving current supplied from the first transistor M1 may flow in accordance with Equation 1 below.

Here, Id represents the amount of driving current supplied by the first transistor (M1), Vgs represents the voltage difference between the voltage of the gate electrode and the source electrode of the first transistor (M1), and Vth represents the amount of driving current supplied by the first transistor (M1). ) means the threshold voltage. Also, k means mobility.

As shown in Equation 1 above, the driving current corresponds to the voltage difference between the gate electrode and the source electrode of the first transistor (M1), so when the second electrode is the source electrode, the source electrode corresponds to the data signal. When the data voltage (Vdata) is transmitted and the reference voltage (Vref) is transmitted to the gate electrode, the driving current may flow in response to the data signal.

Additionally, the pixel 101 may include a fourth transistor (M4). The first electrode of the fourth transistor M4 may be connected to the first power line VL1 that supplies the first power EVDD, and the second electrode may be connected to the first node N1. Additionally, the gate electrode of the fourth transistor M4 may be connected to the emission control signal line (EML) that transmits the emission control signal. The emission control signal line (EML) is connected to the gate driver 130 shown in FIG. 1 and can receive an emission control signal from the gate driver 130. When the fourth transistor M4 is turned on by the light emission control signal, the voltage of the first power source EVDD can be applied to the first node N1. The fourth transistor M4 may be an N MOS type transistor. However, it is not limited to this.

Figure 3 is a conceptual diagram showing how the display device according to the present invention operates divided by region.

Referring to FIG. 3, in the display device 100, one display panel 110 is divided into a first area 110a, a second area 110b, a third area 110c, and a fourth area 110d. You can. Here, it is disclosed that one display panel 110 is divided into four areas, but this is an example and is not limited thereto.

When the display device 100 is a smartphone, the first area 110a indicates the current time, communication status, and battery information. The second area 110b and the third area 110c represent Internet web pages. The second area 110b can display the address bar and the name of the web page on the web page, and the third area 110c can display A search window and search results can be displayed. Additionally, the fourth area 110d may display games or videos. That is, various screens can be provided on one display panel 110.

At this time, if the first to fourth areas 110d are all driven by the same driving frequency, the first areas 110a to fourth areas 110d all have the same one frame period and the image is displayed on the display panel 110. ) can be displayed. At this time, if the driving frequency is set based on the image displayed in the fourth area (110d), unnecessary screen switching occurs in the first to third areas (110c), resulting in an increase in power consumption of the display device 100. Problems may arise.

In order to solve the above problem, the driving frequency of the first area 110a is set to 1 Hz because screen switching rarely occurs, and the screen switching occurs more frequently in the second area 110b than in the first area 110a. The driving frequency can be set to 30Hz, and since screen switching occurs more frequently in the third area (110c) than in the second area (110b), the driving frequency can be set to 60Hz. Additionally, because screen changes occur most frequently in the fourth area 110d, the driving frequency can be set to 120Hz. Here, the driving frequency used in the embodiments of the present invention is not limited to the frequency set in each region.

If the driving frequency is set differently in the first to fourth areas (110a to 110d) as above, consumption is consumed in areas where screen switching does not occur frequently, such as the first area (110a) and the second area (110b). Power can be saved. In addition, the third area 110c and the fourth area 110d, where screen changes occur more frequently, have a high driving frequency, so screen changes can be displayed naturally.

Additionally, the sizes of the first to fourth regions 110a to 110d are not fixed and may vary. Additionally, the display device 100 may display at least one of the first to fourth areas 110a to 110d on the entire display panel 110.

FIG. 4 is a timing diagram showing a gate signal output in response to a driving frequency in a display device according to embodiments of the present invention, and FIG. 5 is a graph comparing power consumption when the driving frequency is 120 Hz and 60 Hz. .

Referring to Figure 4, (a) represents the gate signal when the driving frequency is 120Hz, and (b) represents the gate signal when the driving frequency is 60Hz.

In (a) and (b), the first gate signal (gs1) is a signal that turns on/off the second transistor (M2) of the pixel 101 shown in FIG. 2, and the second gate signal (gs2) is a signal that turns on/off the second transistor (M2) of the pixel 101 shown in FIG. This is a signal that turns on/off the third transistor (M3) of the pixel 101 shown in Figure 2.

In Figure 2, the first transistor (M1) and the second transistor (M2) are shown as N MOS transistors, and the third transistor (M3) is shown as a P MOS transistor, so the first gate signal is transmitted as a high signal and the second transistor is transmitted as a high signal. The gate signal may be transmitted in a low state.

And, as shown in (a) and (b), the period of the first gate signal (gs1) driven at 120Hz is shorter than the second gate signal (gs2) driven at 60Hz, so the first gate signal (gs1) is It can be seen that twice as much is generated as the second gate signal (gs2). That is, when the first gate signal gs1 is transmitted, the number of data signals written to the pixel 101 may be twice as large as when the second gate signal gs2 is transmitted.

Although not shown here, when driven at 30Hz, the first gate signal may be generated once while being generated 4 times, and when driven at 1Hz, it may be generated once while the first gate signal is generated 12 times.

And, as shown in FIG. 5, when comparing the power consumption of the display device 100 when the driving frequency is 120Hz (a) and when the driving frequency is 60Hz (b), (a) and (b) are shown. Likewise, the power consumed by the display device 100 may include the power consumed by logic circuits such as the organic light emitting diode (OLED), the data driver 120, and the gate driver 130. The dotted line (L1) divides the power consumed by the organic light-emitting diode (OLED) and the power consumed by the logic circuit. The organic light-emitting diode (a) has a driving frequency of 120Hz and (b) has a driving frequency of 60Hz. The size of power consumption generated by (OLED) is the same, but the size of power consumption consumed by logic circuit (Logic) may be less in (b) than (a). Accordingly, it can be seen that the display device 100 consumes more power when the driving frequency is 120 Hz (a) than when the driving frequency is 60 Hz (b).

Figure 6 is a structural diagram showing a portion of a gate driver according to embodiments of the present invention.

Referring to FIG. 6, the gate driver 130 may include a shift register 610 and a switch unit 620. Here, the shift register 610 is shown as including eight registers, but this is for convenience of explanation and is not limited thereto.

The shift register 610 can output a plurality of shift signals (sr1 to sr8) that are output sequentially. The shift register 610 may include a plurality of registers 611 to 618.

The plurality of registers 611 to 618 may receive a first clock (CLK1) or a second clock (CLK2) through the first clock line 601 or the second clock line 602, respectively. Here, the plurality of registers 611 to 618 are shown as being supplied with the first clock (CLK1) or the second clock (CLK2), but this is not limited to this, and each register of the plurality of registers 611 to 618 Can receive the first clock (CLK1) and the second clock (CLK2). The first clock (CLK1) and the second clock (CLK2) may be transmitted from the timing controller 140. Additionally, the start pulse (SP) may be transmitted from the timing controller 140. However, it is not limited to this.

The first register 611 can receive a start pulse (SP). Additionally, the first register 611 can receive the first clock (CLK) transmitted through the first clock line 601. The first register 611 may output the first shift signal (sr1) in response to the received start pulse (SP) and first clock (CLK1). When the first shift signal sr1 is transmitted to the first gate line GL1, it may become the first gate signal gs1.

The second register 612 can receive the first shift signal sr1 output from the first register 611 and the second clock CLK2 transmitted through the second clock line 602. The second register 612 may output the second shift signal sr2 in response to the received first shift signal sr1 and the second clock CKL2. Since the second register 612 receives the first shift signal sr1 and outputs the second shift signal sr2, the second shift signal sr2 may be a delayed signal of the first shift signal sr1.

The third register 613 includes the second shift signal (sr2) output from the second register 612 and the first clock (CKL1) transmitted through the first clock line 601 and the second clock line 602. The second clock (CKL2) can be transmitted. The third register 613 may output the third shift signal sr3 in response to the received second shift signal sr2 and the first and second clocks CKL1 and CKL2. Since the third register 613 receives the second shift signal sr2 and outputs the third shift signal sr3, the third shift signal sr3 may be a delayed signal of the second shift signal sr2.

The fourth register 614 includes the third shift signal (sr3) output from the third register 613 and the first clock (CLK1) transmitted through the first clock line 601 and the second clock line 602. The second clock (CLK2) can be received. The fourth register 614 may output the fourth shift signal sr4 in response to the received third shift signal and the first clock (CKL1) and second clock (CKL2). Since the fourth register 614 receives the third shift signal sr3 and outputs the fourth shift signal sr4, the fourth shift signal sr4 may be a delayed signal of the third shift signal sr3.

In the same manner as above, the fifth to eighth registers 615 to 618 can output the fifth to eighth shift signals (sr5 to sr8).

For the above reason, the shift register 610 including the first to eighth registers 611 to 618 can sequentially output the first to eighth shift signals sr1 to sr8.

The switch unit 620 transfers a plurality of sequentially received shift signals (sr1 to sr8) to a plurality of gate lines (GL1 to GL8) through a switching operation, so that the plurality of gate signals (gs1 to gs8) are connected to the gate line (GL1). to GL8) can be delivered sequentially. In addition, the switch unit 620 sequentially receives a plurality of shift signals (sr1 to sr8) and prevents them from being transmitted to the plurality of gate lines (GL1 to GL8) through a switching operation, so that the plurality of gate signals (gs1 to gs8) are transmitted. It can be prevented from being transmitted to the gate lines (GL1 to GL8).

The switch unit 620 includes first to eighth switches (SW1 to SW8), where the first switch (SW1) connects the output terminal of the first register 611 and the first gate line, and the second switch ( SW2) connects the output terminal of the second register 612 and the second gate line (GL2), and the third switch (SW3) connects the output terminal of the third register 613 and the third gate line (GL3), The fourth switch SW4 may connect the output terminal of the fourth register 614 and the fourth gate line GL4. In addition, the fifth switch (SW5) connects the output terminal of the fifth register 615 and the fifth gate line (GL5), and the sixth switch (SW6) connects the output terminal of the sixth register 616 and the sixth gate line ( GL6), the seventh switch (SW7) connects the output terminal of the seventh register 617 and the seventh gate line (GL7), and the eighth switch (SW8) connects the output terminal of the eighth register 618 and the seventh gate line (GL7). 8 gate lines (GL8) can be connected.

In addition, the first to eighth switches (SW1 to SW8) may be turned on/off simultaneously in response to the frequency selection signal (MULTI) transmitted through the multi-frequency selection signal line 603.

7 and 8 are timing diagrams showing the operation of a gate driver according to embodiments of the present invention. The first period (T1) is a period in which the gate signal is applied to the first to eighth gate lines (GL1 to GL8) arranged in the first area (110a) and the second area (110b), and the second period ( T2) is explained as a period indicating that a gate signal is applied to the first to eighth gate lines GL1 to GL8 arranged in the first area 110a and the second area 110b.

Referring to FIG. 7, it is assumed that the driving frequency of the first area 110a is set higher than the driving frequency of the second area 110b. In the first period (T1), the multi-control signal (MULTI) is maintained in a high state, so that the first to eighth switches (SW1 to SW8) shown in FIG. 6 can be maintained in a turned-on state.

In the first period T1, the first to eighth gate lines GL1 to GL8 disposed in the first area 110a and the second area 110b receive the first to second shift signals from the shift register 610. By sequentially receiving 4 shift signals (sr1 to sr4), the first to eighth gate signals (gs1 to gs8) can be sequentially output.

In addition, in the first second period (T2a) of the second period (T2), the multi-control signal (MULTI) maintains a high state, and in the second second period (T2b), the multiple multi-control signal (MULTI) maintains a low state. do.

The first to eighth switches SW1 to SW8 can be maintained in the turn-on state in the first second period T2a by the multi-control signal MULTI. And, in the second second period (T2b), the first to eighth switches (SW1 to SW8) may maintain the turn-off state.

In the first second period (T2a), the first to fourth shift signals (sr1 to sr4) are transmitted from the shift register 610, and in the second second period (T2b), the fifth to fourth shift signals are transmitted from the shift register 610. The eighth shift signal (sr5 to sr8) may be transmitted.

In the second period (T2), the first to eighth switches (SW1 to SW8) may receive the first to eighth shift signals (sr1 to sr8), but in the first second period (T2a), the first to eighth switches (SW1 to SW8) may receive the first to eighth shift signals (sr1 to sr8). The switches SW1 to SW8 maintain the turn-on state and the first to eighth switches (SW1 to SW8) maintain the turn-off state in the second second period (T2b), so that the first to eighth switches Among the first to eighth shift signals (sr1 to sr8) received by the 8 switches (SW1 to SW8), the 5th to 8th shift signals (sr4 to sr8) are the 5th to 8th gate lines ( Since they are not transmitted to GL5 to GL8), the fifth to eighth gate signals (gs5 to gs8) may not be output. Here, the fifth to eighth gate signals (gs5 to gs8) are indicated with dotted lines to indicate that the fifth to eighth gate signals (gs5 to gs8) are not output.

Here, the multi-control signal MULTI is shown changing from a high state to a low state between the fourth gate signal gs4 and the fifth gate signal gs5 in the second period T2, but is limited thereto. This does not mean that the width of the multi-control signal MULTI is variable, so that the number of gate lines outputting the gate signal in the second period T2 can be controlled by the width of the multi-control signal MULTI.

The first area 110a can sequentially output a greater number of gate signals than the second area 110b within the same period, so the first area 110a corresponds to a higher driving frequency than the second area 110b. A video can be displayed.

Referring to FIG. 8, it is assumed that the driving frequency of the first area 110a is set lower than the driving frequency of the second area 110b. In the first first period (T1a) of the first period (T1), the multiple multi control signal (MULTI) remains low, and in the second first period (T1b) of the first period (T1), the multiple multi control signal (MULTI) remains low. can remain high.

Therefore, in the first first period (T1a), the first to eighth switches (SW1 to SW8) shown in FIG. 6 maintain the turn-off state, and in the second first period (T1b), the first to eighth switches (SW1 to SW8) shown in FIG. 6 remain in the turn-off state. The eighth switch (SW1 to SW8) can maintain the turn-on state.

In the first first period (T1a), the first to fourth shift signals (sr1 to sr4) are transmitted from the shift register 610, and in the second first period (T1b), the fifth to fourth shift signals are transmitted from the shift register 610. The eighth shift signal (sr5 to sr8) may be transmitted.

In the first period (T1), the first to eighth switches (SW1 to SW8) may receive the first to eighth shift signals (sr1 to sr8), but in the first period (T1a), the first to eighth switches (SW1 to SW8) may receive the first to eighth shift signals (sr1 to sr8). The switches SW1 to SW8 maintain the turn-off state and the first to eighth switches (SW1 to SW8) maintain the turn-on state in the second first period (T1b), so that the first to eighth switches Among the first to eighth shift signals (sr1 to sr8) received by the 8 switches (SW1 to SW8), the first to fourth shift signals (sr1 to sr4) are the first to fourth gate lines ( Since they are not transmitted to GL1 to GL4), the first to fourth gate signals (gs1 to gs4) may not be output. Here, the first to fourth gate signals (gs1 to gs4) are indicated with dotted lines to indicate that the first to fourth gate signals (gs1 to gs4) are not output.

And, in the second period (T2), the multi-control signal (MULTI) maintains the high state, so that the first to eighth switches (SW1 to SW8) shown in FIG. 6 can maintain the turn-on state.

In the second period T2, the first to eighth gate lines GL1 to GL8 disposed in the first area 110a and the second area 110b receive the first to second shift signals from the shift register 610. By sequentially receiving 4 shift signals (sr1 to sr4), the first to eighth gate signals (gs1 to gs8) can be sequentially output.

Here, the multi-control signal MULTI is shown changing from a low state to a high state between the fourth gate signal gs4 and the fifth gate signal gs5 in the first period T1, but is limited to this. This does not mean that the width of the multi-control signal MULTI is variable, so that the number of gate lines outputting the gate signal in the first period T1 can be controlled by the width of the multi-control signal MULTI.

The first area 110a can sequentially output fewer gate signals than the second area 110b within the same period, so the first area 110a corresponds to a lower driving frequency than the second area 110b. A video can be displayed.

9 is a flowchart showing a method of driving a display device according to embodiments of the present invention.

Referring to FIG. 9 , the display device 100 shown in FIG. 1 may include a display panel 110 divided into at least a first area 110a and a second area 110b. And, the method of driving the display device can display an image corresponding to the first driving frequency in the first area 110a of the display panel 110 (S900).

In addition, the method of driving the display device can display an image in the second area 110b of the display panel 110 in response to a second driving frequency that is different from the first driving frequency (S910).

The display device 100 shown in FIG. 1 includes a gate driver 130 that outputs a gate signal, and the gate driver 130 includes a shift register 610 that sequentially outputs a shift signal and a display device that receives the shift signal. Gate signals are sequentially supplied to a plurality of gate lines GL1 to GLn arranged in the first area 110a and the second area 110b of the panel 110, and in the first period, the first area 110a and A switch unit 620 sequentially supplies gate signals to each of the second areas 110b, and sequentially supplies gate signals to either the first area 110a or the second area 110b during the second period. ) may include. In addition, the gate driver 130 includes a shift register 610 that sequentially outputs shift signals and a plurality of devices arranged in the first area 110a and the second area 110b of the display panel 110 to receive the shift signals. A gate signal is sequentially supplied to the gate lines GL1 to GLn, and during the first period, the gate signal is sequentially supplied to either the first area 110a or the second area 110b, and the gate signal is sequentially supplied to either the first area 110a or the second area 110b during the first period. may include a switch unit 620 that sequentially supplies gate signals to the first area 110a and the second area 110b, respectively.

If the first driving frequency is higher than the second driving frequency, the first area 110a can receive the gate signal in the first period and the second period, respectively, and the second area 110b can receive the gate signal in the first period and the second period. The gate signal can be received in any one of the second periods.

In the first period, the multi-control signal (MULTI) controlling the switch unit 620 is transmitted in a high state, so that the switch unit 620 is turned on, and in the second period, the multiple multi-control signal (MULTI) is in a low state. The switch unit 620 may be turned off. Since the switch unit 620 is turned on in the first period, the shift signal sequentially output from the shift register 610 is transmitted to the gate line, so that the gate signal can be sequentially transmitted to the plurality of gate lines GL1 to GLn. there is. On the other hand, since the switch unit 620 is turned off in the second period, the shift signal sequentially output from the shift register is not transmitted to the gate line, so the gate signal is not transmitted to the plurality of gate lines (GL1 to GLn). You can.

In addition, if the first driving frequency is lower than the second driving frequency, the first area 110a can receive the gate signal in any one of the first period and the second period, and the second area (110a) can receive the gate signal in either the first period or the second period. 110b) can receive gate signals in the first period and the second period, respectively.

In the first period, the multi-control signal (MULTI) controlling the switch unit 620 is transmitted in a low state, so that the switch unit 620 is turned off, and in the second period, the multiple multi-control signal (MULTI) is transmitted in a high state. The switch unit 620 may be turned on. Since the switch unit 620 is turned off in the first period, the shift signal sequentially output from the shift register 610 is not transmitted to the gate line, preventing the gate signal from being transmitted to the plurality of gate lines (GL1 to GLn). It can be. On the other hand, since the switch unit 620 is turned on in the second period, the shift signal sequentially output from the shift register 610 is transmitted to the gate line, and the gate signal is sequentially transmitted to the plurality of gate lines (GL1 to GLn). It can be.

Accordingly, depending on the driving method of the display device, the first area 110a and the second area 110b of the display device 100 can display images corresponding to different driving frequencies. The driving method of the display device allows the sizes of the first area 110a and the second area 110b to be varied by adjusting the width of the multi-control signal MULTI. Additionally, the number of areas of the display device 100 can be controlled using the multi-control signal (MULTI). The multi-control signal (MULTI) may be output from the timing controller 140 shown in FIG. 1.

Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present specification. . Accordingly, the embodiments disclosed in this specification are not intended to limit the technical idea of the present specification, but rather to explain it, and the scope of the technical idea of the present specification is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of this specification should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of this specification.

100: display device
110: display panel
120: data driver
130: gate driver
140: Timing controller

Claims (16)

A display panel divided into at least a first area and a second area, and displaying images corresponding to different driving frequencies in the first area and the second area, respectively;
a data driver that supplies an image signal corresponding to the image to the display panel;
A gate driver that supplies a gate signal to the display panel; and
Including a timing controller that controls the data driver and the gate driver,
The gate driver is
A shift register including n registers that sequentially output n shift signals; and
A switch unit connecting the output terminals of the n registers and the n gate lines and including n switches simultaneously controlled by a multi-control signal with a variable width,
In the first period, n gate signals corresponding to the n shift signals are sequentially supplied to the first area and the second area, and in the second period, the width of the multiplex control signal is varied to shift the n number of shifts. A display device that blocks m (a natural number smaller than n) shift signals among signals and sequentially supplies nm gate signals corresponding to nm shift signals to the first region among the first and second regions.
According to paragraph 1,
If the driving frequency of the first area is set higher than the driving frequency of the second area,
In a first period, the first area and the second area sequentially output the n gate signals,
In a second period, the nm gate signals are sequentially transmitted to the first region and the gate signals are not transmitted to the second region.
delete delete delete According to paragraph 1,
The shift register includes a first circuit unit that outputs a first shift signal among the n shift signals,
A display device comprising a second circuit unit that outputs a second shift signal among the n shift signals when receiving the first shift signal from the first circuit unit.
delete delete A shift register including n registers that sequentially output n shift signals; and
A switch unit connecting the output terminals of the n registers and the n gate lines and including n switches simultaneously controlled by a multi-control signal with a variable width,
In the first period, n gate signals corresponding to the n shift signals are sequentially supplied to the first area and the second area, and in the second period, the width of the multi-control signal is varied to select among the n shift signals. A gate driver that blocks m (a natural number smaller than n) shift signals and sequentially supplies nm gate signals corresponding to nm shift signals to the first region among the first and second regions.
According to clause 9,
A gate driver in which gate lines arranged in the first area among the n gate lines are supplied with a gate signal before gate lines arranged in the second area.
According to clause 9,
A gate driver in which gate lines arranged in the first area among the n gate lines receive a gate signal later than gate lines arranged in the second area.
Displaying an image corresponding to a first driving frequency in a first area of the display panel by sequentially supplying n gate signals corresponding to n shift signals in a first period; and
By varying the width of the multi-control signal that simultaneously controls n switches connecting n registers and n gate lines in the second period, m (a natural number smaller than n) shift signals are blocked among the n shift signals. and supplying nm gate signals corresponding to nm shift signals to display an image corresponding to a second driving frequency that is different from the first driving frequency in a second area of the display panel. Driving method.
According to clause 12,
The first driving frequency is higher than the second driving frequency,
A method of driving a display device in which a gate signal is sequentially supplied from the first area to the second area of the display panel.
According to clause 12,
The first driving frequency is higher than the second driving frequency,
A method of driving a display device in which a gate signal is sequentially supplied from the second area to the first area of the display panel.
According to clause 12,
In response to the first driving frequency, the first area of the display panel sequentially receives the n gate signals in the first period and the second period,
In response to the second driving frequency, the second area of the display panel sequentially transmits the nm gate signals in response to any one of the first period and the second period in response to the second driving frequency. How to drive the receiving display device.
delete