CN116930823A - High-voltage adjacent test method and system for wire tester - Google Patents

High-voltage adjacent test method and system for wire tester Download PDF

Info

Publication number
CN116930823A
CN116930823A CN202311197006.8A CN202311197006A CN116930823A CN 116930823 A CN116930823 A CN 116930823A CN 202311197006 A CN202311197006 A CN 202311197006A CN 116930823 A CN116930823 A CN 116930823A
Authority
CN
China
Prior art keywords
voltage
pins
adjacent
connector
qualified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311197006.8A
Other languages
Chinese (zh)
Inventor
刘亚国
孙伯乐
高志齐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changzhou Tonghui Electronics Co ltd
Original Assignee
Changzhou Tonghui Electronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changzhou Tonghui Electronics Co ltd filed Critical Changzhou Tonghui Electronics Co ltd
Priority to CN202311197006.8A priority Critical patent/CN116930823A/en
Publication of CN116930823A publication Critical patent/CN116930823A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66Testing of connections, e.g. of plugs or non-disconnectable joints

Abstract

The application belongs to the technical field of electronic testing, and particularly relates to a high-voltage adjacent testing method and a testing system for a wire tester, wherein the high-voltage adjacent testing method comprises the following steps of: acquiring parameters of a connector; detecting whether the high-voltage parameter of the connector is qualified or not; the high-voltage parameter detection of the connector can be completed only by two times of detection, and the test efficiency is improved.

Description

High-voltage adjacent test method and system for wire tester
Technical Field
The application belongs to the technical field of electronic testing, and particularly relates to a high-voltage adjacent testing method and a testing system for a wire tester.
Background
The connector is characterized by two features: the number of the feet is more, and tens of feet are hundreds of feet; the high-voltage failure only occurs between two adjacent pins; conventional high pressure testing methods are shown in the following table:
the connector needs to be tested for many times during high-voltage testing, and the efficiency is low.
Therefore, based on the above technical problems, a new high-voltage adjacent test method and test system for a wire tester need to be designed.
Disclosure of Invention
The application aims to provide a high-voltage adjacent test method and a test system for a wire tester.
In order to solve the technical problems, the application provides a high-voltage adjacent testing method for a wire tester, which comprises the following steps:
acquiring parameters of a connector;
and detecting whether the high-voltage parameters of the connector are qualified.
Further, the parameters of the acquisition connector include:
the number of rows of pin arrangements on the connector is obtained.
Further, the number of pins per row is obtained.
Further, the method for detecting whether the high-voltage parameter of the connector is qualified comprises the following steps:
and sequentially labeling each pin in each row, connecting high voltage to the odd-numbered pins, and connecting low voltage to the even-numbered pins, so that high voltage and low voltage are formed between the adjacent odd-numbered pins and even-numbered pins.
Furthermore, the high voltage is connected to the pins with odd numbers, and the pins with even numbers are connected to the low end and then are electrified, and if the high voltage is output, the high voltage parameters between two adjacent pins in each row are qualified.
Further, each whole row is sequentially numbered, high voltage is connected to all pins in the odd rows, and low voltage is connected to all pins in the even rows, so that high voltage and low voltage are formed between the adjacent whole rows of pins.
Furthermore, all pins in the odd-numbered rows are connected with high voltage, all pins in the even-numbered rows are connected with the low end and then are electrified, and if the high voltage is output, the high voltage parameters between two adjacent rows of pins are qualified.
Further, when the high-voltage parameter between two adjacent pins in each row is qualified, and the high-voltage parameter between two adjacent rows of pins is qualified, the connector is judged to be qualified in high-voltage parameter.
In another aspect, the present application also provides a high-voltage adjacent test system for a wire tester, comprising:
the parameter module is used for acquiring parameters of the connector;
and the judging module is used for detecting whether the high-voltage parameters of the connector are qualified or not.
Further, the high-voltage adjacent test system is suitable for detecting whether the high-voltage parameters of the connector are qualified or not by adopting the high-voltage adjacent test method for the wire tester.
The application has the beneficial effects that the parameters of the connector are obtained; detecting whether the high-voltage parameter of the connector is qualified or not; the high-voltage parameter detection of the connector can be completed only by two times of detection, and the test efficiency is improved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and drawings.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a high voltage adjacent test method for a wire tester of the present application;
FIG. 2 is a schematic diagram of a 16 pin connector pin label of the present application;
fig. 3 is a schematic diagram of any number of pin connectors of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Embodiment 1 as shown in fig. 1 to 3, embodiment 1 provides a high-voltage adjacent test method for a wire tester, including: acquiring parameters of a connector; detecting whether the high-voltage parameter of the connector is qualified or not; the high-voltage parameter detection of the connector can be completed only by two times of detection, and the test efficiency is improved.
In this embodiment, the parameters of the acquisition connector include: obtaining the number of rows of pin arrangement on the connector; the pins of each row are convenient to set subsequently, and accurate testing is convenient.
In this embodiment, the number of pins of each row is obtained; facilitating the setting of each pin.
In this embodiment, the method for detecting whether the high voltage parameter of the connector is acceptable includes: sequentially marking each pin in each row, connecting high voltage to the odd-numbered pins, connecting low voltage to the even-numbered pins, and forming high and low voltage between the adjacent odd-numbered pins and even-numbered pins; the high voltage can be connected to the pins with even numbers, and the low voltage can be connected to the pins with odd numbers, so that the high voltage parameter test can be conveniently performed between two adjacent pins in the same row.
In this embodiment, the high voltage is connected to the pins with odd numbers, and the pins with even numbers are connected to the low end and then are electrified, if the high voltage is output, the high voltage parameters between two adjacent pins in each row are qualified.
In this embodiment, each whole row is sequentially numbered, all pins in the odd rows are connected to high voltage, and all pins in the even rows are connected to low voltage, so that high voltage and low voltage are formed between the adjacent whole rows of pins; and high voltage can be accessed to all pins of even rows, and low voltage can be accessed to all pins of odd rows, so that high voltage parameter test can be conveniently performed between two adjacent pins of the same row.
In this embodiment, all pins in the odd-numbered rows are connected to high voltage, and all pins in the even-numbered rows are connected to low voltage and then are electrified, if the high voltage is output, the high voltage parameters between two adjacent rows of pins are qualified.
In this embodiment, when the high voltage parameter between two adjacent pins in each row is qualified, and the high voltage parameter between two adjacent rows of pins is qualified, the connector is judged to be qualified.
In this embodiment, a 16 pin connector is tested for high voltage parameters if needed. One pair of other test methods requires testing 16 times and the dichotomy requires testing 4 times. The high-voltage adjacent test method for the wire tester can reduce the test times to 2 times, and can meet the test requirement of high-voltage parameters.
In the present embodiment, a 16-pin connector is taken as an example for illustration, and the characteristics of the connector are as follows: the high voltage defect can only occur between two adjacent pins, namely, only the high voltage parameters of the adjacent pins are measured. There are 2 cases of adjacent positions of the connector: first kind: laterally adjacent locations such as foot 1 and foot 2; second kind: longitudinally adjacent locations such as foot 1 and foot 9; therefore, the high-voltage adjacent test method for the wire tester is also used for testing according to the two adjacent position conditions one by one.
Step 1: and the test of the transverse adjacent pins only needs to ensure that the high-low voltage relation between any transverse adjacent pins. As shown in tables 1 and 2 below, the odd pins are high voltage and the even pins are low voltage. (+ "indicates high voltage, and" - "indicates low side);
table 1: first row pin configuration table for testing transverse adjacent pins
Table 2: second row pin configuration table for testing transverse adjacent pins
The instrument then outputs a high voltage, and if the test results are acceptable, it is indicated that the high voltage parameter between any laterally adjacent pins is acceptable.
Step 2: and testing the longitudinal adjacent pins, and only ensuring that any longitudinal adjacent pins have a high-low voltage relationship. As shown in tables 3 and 4 below, all pins in the odd rows are high-voltage and all pins in the even rows are low-voltage. (+ "indicates high voltage, and" - "indicates low side);
table 3: first row pin configuration table for testing longitudinal adjacent pins
Table 4: second row pin configuration table for testing longitudinal adjacent pins
The instrument then outputs a high voltage, and if the test results are acceptable, it is indicated that the high voltage parameter between any of the longitudinally adjacent pins is acceptable.
Through the above 2 tests, the adjacent pins in the transverse direction and the adjacent pins in the longitudinal direction are respectively tested, and if the test results of the 2 tests are all qualified, the high-voltage parameters between the adjacent pins in any direction of the connector are qualified. In addition, the characteristics of the connector are added, and the high-voltage fault only exists in the adjacent pins, so that the high-voltage parameter between any two pins of the connector can be obtained to be qualified, namely the high-voltage parameter of the connector is qualified. The high-voltage adjacent test method only needs 2 times (1 time in the transverse direction and 1 time in the longitudinal direction), so that the test efficiency is improved. The more advantageous this algorithm is as the number of pins increases, as shown in table 5:
table 5: chart of test times
In this embodiment, the connector is exemplified by M pins in the transverse direction and n rows in the longitudinal direction, and the total number of pins m=m×n; first, the high voltage parameters of the laterally adjacent pins are tested. The pin configuration is carried out according to the method that the odd pins are connected with high voltage and the even pins are connected with low voltage, so that the high voltage and the low voltage between any two adjacent pins are ensured. As shown in table 6 below:
table 6: test lateral adjacent pin configuration table
And secondly, testing the high-voltage parameters of the longitudinally adjacent pins. And (3) carrying out pin configuration according to the method that all pins in the odd-numbered rows are connected with high voltage and all pins in the even-numbered rows are connected with low voltage, so as to ensure that high voltage and low voltage are arranged between any two adjacent pins in the longitudinal direction. As shown in table 7 below:
table 7: test longitudinal adjacent pin configuration table
Finally, after the testing of the adjacent pins in the transverse direction and the longitudinal direction is completed, the high-voltage testing of the connector is completed. No matter how complex the connector is, only 2 tests are required to complete the high voltage test.
Embodiment 2 on the basis of embodiment 1, this embodiment 2 further provides a high-voltage adjacent test system for a wire tester, including: the parameter module is used for acquiring parameters of the connector; and the judging module is used for detecting whether the high-voltage parameters of the connector are qualified or not.
In this embodiment, the high-voltage adjacent test system is adapted to detect whether the high-voltage parameters of the connector are acceptable by adopting the high-voltage adjacent test method for the wire tester.
In summary, the parameters of the connector are obtained; detecting whether the high-voltage parameter of the connector is qualified or not; the high-voltage parameter detection of the connector can be completed only by two times of detection, and the test efficiency is improved.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
With the above-described preferred embodiments according to the present application as an illustration, the above-described descriptions can be used by persons skilled in the relevant art to make various changes and modifications without departing from the scope of the technical idea of the present application. The technical scope of the present application is not limited to the description, but must be determined according to the scope of claims.

Claims (10)

1. A high voltage adjacent test method for a wire tester, comprising:
acquiring parameters of a connector;
and detecting whether the high-voltage parameters of the connector are qualified.
2. The method for high-voltage neighbor testing for a wire tester according to claim 1,
the parameters of the acquisition connector include:
the number of rows of pin arrangements on the connector is obtained.
3. A high-voltage adjacent test method for a wire tester according to claim 2, wherein,
the number of pins per row is obtained.
4. A high-voltage adjacent test method for a wire tester according to claim 3,
the method for detecting whether the high-voltage parameter of the connector is qualified comprises the following steps:
and sequentially labeling each pin in each row, connecting high voltage to the odd-numbered pins, and connecting low voltage to the even-numbered pins, so that high voltage and low voltage are formed between the adjacent odd-numbered pins and even-numbered pins.
5. The method for high-voltage neighbor testing for a wire tester according to claim 4,
and (3) connecting high voltage to the pins with odd numbers, connecting the pins with even numbers to the low end, and electrifying, wherein if the high voltage is output, the high voltage parameters between two adjacent pins in each row are qualified.
6. The method for high-voltage neighbor testing for a wire tester according to claim 5,
each whole row is sequentially numbered, high voltage is connected to all pins in the odd rows, and low voltage is connected to all pins in the even rows, so that high voltage and low voltage are formed between the adjacent whole rows.
7. The method for high-voltage neighbor testing for a wire tester according to claim 6,
and all pins in the odd-numbered rows are connected with high voltage, all pins in the even-numbered rows are connected with the low end and then are electrified, and if the high voltage is output, the high voltage parameters between two adjacent rows of pins are qualified.
8. The method for high-voltage neighbor testing for a wire tester according to claim 7,
and when the high-voltage parameters between two adjacent pins in each row are qualified and the high-voltage parameters between two adjacent rows of pins are qualified, judging that the high-voltage parameters of the connector are qualified.
9. A high voltage adjacent test system for a wire tester, comprising:
the parameter module is used for acquiring parameters of the connector;
and the judging module is used for detecting whether the high-voltage parameters of the connector are qualified or not.
10. A high-voltage adjacent test system for a wire tester according to claim 9,
the high-voltage adjacent test system is suitable for detecting whether the high-voltage parameters of the connector are qualified by adopting the high-voltage adjacent test method for the wire tester according to any one of claims 1 to 8.
CN202311197006.8A 2023-09-18 2023-09-18 High-voltage adjacent test method and system for wire tester Pending CN116930823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311197006.8A CN116930823A (en) 2023-09-18 2023-09-18 High-voltage adjacent test method and system for wire tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311197006.8A CN116930823A (en) 2023-09-18 2023-09-18 High-voltage adjacent test method and system for wire tester

Publications (1)

Publication Number Publication Date
CN116930823A true CN116930823A (en) 2023-10-24

Family

ID=88389999

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311197006.8A Pending CN116930823A (en) 2023-09-18 2023-09-18 High-voltage adjacent test method and system for wire tester

Country Status (1)

Country Link
CN (1) CN116930823A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102944823A (en) * 2012-11-30 2013-02-27 中国北车集团大连机车车辆有限公司 High-voltage holding test method of wiring harness connector
CN103592578A (en) * 2012-08-16 2014-02-19 神讯电脑(昆山)有限公司 High-voltage insulation tester of cable
CN106154127A (en) * 2016-06-27 2016-11-23 成都蓉盛达系统工程技术有限公司 The wire harness pressure method for rapidly testing of insulation
CN109031064A (en) * 2018-07-24 2018-12-18 常州同惠电子股份有限公司 High pressure two for wire test instrument divides test method
CN109031065A (en) * 2018-07-24 2018-12-18 常州同惠电子股份有限公司 Other a pair of test methods of high pressure for wire test instrument
CN115128406A (en) * 2022-05-23 2022-09-30 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) Voltage withstand test device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103592578A (en) * 2012-08-16 2014-02-19 神讯电脑(昆山)有限公司 High-voltage insulation tester of cable
CN102944823A (en) * 2012-11-30 2013-02-27 中国北车集团大连机车车辆有限公司 High-voltage holding test method of wiring harness connector
CN106154127A (en) * 2016-06-27 2016-11-23 成都蓉盛达系统工程技术有限公司 The wire harness pressure method for rapidly testing of insulation
CN109031064A (en) * 2018-07-24 2018-12-18 常州同惠电子股份有限公司 High pressure two for wire test instrument divides test method
CN109031065A (en) * 2018-07-24 2018-12-18 常州同惠电子股份有限公司 Other a pair of test methods of high pressure for wire test instrument
CN115128406A (en) * 2022-05-23 2022-09-30 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) Voltage withstand test device

Similar Documents

Publication Publication Date Title
CN111554344B (en) Storage unit testing method and device, storage medium and electronic equipment
US6324665B1 (en) Event based fault diagnosis
Huang et al. Scan chain diagnosis based on unsupervised machine learning
CN112217668B (en) Self-adaptive network fault diagnosis method based on comparison model
US9400311B1 (en) Method and system of collective failure diagnosis for multiple electronic circuits
CN108984575B (en) Three-dimensional system integrated circuit wafer test probe station data structure storage method
CN116930823A (en) High-voltage adjacent test method and system for wire tester
DE112004000601T5 (en) Event-based test procedure to eliminate clock-related errors in integrated circuits
Huang Dynamic learning based scan chain diagnosis
CN114862740A (en) Defect detection method, device, electronic equipment and computer readable storage medium
DE102004043050B4 (en) Method, semiconductor device and test system for loop-back measurement of the interface timing of semiconductor devices
CN110264842A (en) A kind of tutoring system and method for the p-wire measuring principle that sharpens understanding
US6751765B1 (en) Method and system for determining repeatable yield detractors of integrated circuits
CN113296043B (en) Online analysis method, device and equipment for voltage transformer errors and storage medium
CN110361601B (en) Method for rapidly testing electric indexes of pins of LCD (liquid crystal display) device
CN109342872A (en) A kind of cable conducting high speed detection algorithm
KR100901522B1 (en) Scan chain diagnosis method and apparatus using symbolic simulation
JP5213114B2 (en) Continuity inspection method and continuity inspection device
JP4745820B2 (en) Circuit board inspection apparatus and circuit board inspection method
CN212723249U (en) Fault detection device
JP3254633B2 (en) EEP-ROM simultaneous test method
US6400134B1 (en) Automated bad socket masking in real-time for test handlers
US11092645B2 (en) Chain testing and diagnosis using two-dimensional scan architecture
CN113536506B (en) Method, system, equipment and medium for testing self-healing capacity of power distribution network
JP2000304820A (en) Device and method for fault diagnosing as well as semiconductor integrated circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination