CN116915247A - Broadband low-phase-noise low-spurious-frequency source - Google Patents

Broadband low-phase-noise low-spurious-frequency source Download PDF

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Publication number
CN116915247A
CN116915247A CN202310831801.1A CN202310831801A CN116915247A CN 116915247 A CN116915247 A CN 116915247A CN 202310831801 A CN202310831801 A CN 202310831801A CN 116915247 A CN116915247 A CN 116915247A
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China
Prior art keywords
signal
circuit
phase
frequency
outputs
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CN202310831801.1A
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Chinese (zh)
Inventor
魏良桂
关鑫
邢君
柴俊
杨威
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723 Research Institute of CSIC
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723 Research Institute of CSIC
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Priority to CN202310831801.1A priority Critical patent/CN116915247A/en
Publication of CN116915247A publication Critical patent/CN116915247A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention provides a broadband low-phase-noise low-spurious frequency source. The device comprises a reference clock circuit, a phase-locked circuit, a frequency dividing circuit and a radio frequency output circuit which are sequentially connected, wherein the reference clock circuit locks an internal 100MHz constant-temperature crystal oscillator by using an external reference signal and outputs a 100MHz clock signal; the phase-locked circuit comprises a power divider, a frequency multiplier, a DDS, a feedback circuit, a phase discriminator, a loop filter and a VCO, and outputs a broadband low-spurious low-phase-noise 10-20 GHz signal; the frequency division circuit divides the frequency of the output signal of the phase-locked circuit, and expands the bandwidth of the signal; the radio frequency output circuit attenuates, modulates, amplifies, switch filters the output wideband signal and ultimately outputs the signal. The invention has the characteristics of wide band, low phase noise, low spurious, controllable output power, controllable modulation mode and the like.

Description

Broadband low-phase-noise low-spurious-frequency source
Technical Field
The invention belongs to the technical field of microwaves, and particularly relates to a broadband low-phase-noise low-spurious-frequency source.
Background
Microwave frequency sources are core components in radio systems, and are widely used in the fields of communication, radar, electronic countermeasure, etc., and the performance of the microwave frequency sources will be directly affected by the performance of the receiver. From the development theory to the development, the frequency synthesis technology can be divided into the following four types: direct Analog Synthesis (DAS), indirect synthesis (PLL), direct Digital Synthesis (DDS), mixed frequency synthesis. The direct analog frequency synthesis technology has the main advantages of fast frequency switching, low phase noise, high cost and large volume; the phase-locked loop frequency synthesis has the advantages of low cost, convenient switching frequency and the like, but the frequency conversion time is longer; the direct digital synthesis technology has the greatest advantages of high resolution and high frequency conversion speed, but has the fatal weaknesses of low output frequency, high phase noise and the like. In addition, by combining the two or three frequency synthesis techniques described above using a hybrid frequency synthesis technique, a signal satisfying higher requirements can be obtained.
In the mixed frequency synthesis design, the phase noise of a phase-locked loop circuit or a frequency doubling circuit worsens by 20Log (N) along with the increase of the frequency division frequency N of a frequency doubling or feedback circuit, the high-frequency band phase noise of a broadband frequency source worsens more, and a low-phase-noise broadband output signal is difficult to obtain. Meanwhile, the DDS output spurious in the mixed frequency synthesis design is higher, the bandwidth can be expanded by directly mixing with the point frequency signal, but larger spurious signals are brought at the same time, and the low spurious design is not facilitated.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a broadband low-phase-noise low-spurious-frequency source. The device comprises a reference clock circuit, a phase-locked circuit, a frequency dividing circuit and a radio frequency output circuit which are sequentially connected, wherein the reference clock circuit locks an internal 100MHz constant-temperature crystal oscillator by using an external reference signal and outputs a 100MHz clock signal; the phase-locked circuit comprises a power divider, a frequency multiplier, a DDS, a feedback circuit, a phase discriminator, a loop filter and a VCO, and outputs a broadband low-spurious low-phase-noise 10-20 GHz signal; the frequency division circuit divides the frequency of the output signal of the phase-locked circuit, and expands the bandwidth of the signal; the radio frequency output circuit attenuates, modulates, amplifies, switch filters the output wideband signal and ultimately outputs the signal. The invention has the characteristics of wide band, low phase noise, low spurious, controllable output power, controllable modulation mode and the like.
A broadband low phase noise low spurious frequency source comprising: the reference clock circuit, the phase-locked circuit, the frequency dividing circuit and the radio frequency output circuit are sequentially connected;
the reference clock circuit locks an internal 100MHz constant-temperature crystal oscillator by utilizing an external reference signal through an integer phase-locked loop and outputs a 100MHz clock signal to the phase-locked circuit;
the phase-locked circuit comprises a power divider, a frequency multiplier, a DDS, a feedback circuit, a phase discriminator, a loop filter and a VCO, wherein the power divider is a 100MHz one-to-two power divider, and outputs a 100MHz signal power outputted by the reference clock circuit into two paths, one path is outputted to the frequency multiplier, and the other path is outputted to the feedback circuit; the frequency multiplier performs frequency multiplication processing on the signal output by the power divider and outputs the signal to the DDS, and the DDS outputs a 200MHz bandwidth signal to the phase discriminator; the feedback circuit consists of a harmonic generator, a first switch filter bank, a first variable frequency divider and a mixer circuit, wherein the harmonic generator processes signals output by the power divider, outputs harmonic signals with different frequencies to the first switch filter bank, filters the harmonic signals with different frequencies by the first switch filter bank, and outputs 2GHz, 2.2GHz or 2.4GHz signals to a local oscillation input port of the mixer circuit according to different external input control levels; the VCO outputs a signal to the first variable divider, and the first variable divider divides the frequency of the signal according to an external input control level and outputs the signal to a radio frequency input port of the mixer circuit; the mixing circuit respectively performs down-conversion and synthesis on the output signal of the switch filter group I and the output signal of the variable frequency divider I, and outputs an intermediate frequency signal to the phase discriminator; the phase discriminator performs phase discrimination processing on the intermediate frequency signal output by the feedback circuit and the 200MHz bandwidth signal output by the DDS, and then outputs a phase discrimination voltage signal through the loop filter to control the VCO to output 10-20 GHz signals;
the frequency dividing circuit comprises a variable frequency divider II, and is used for carrying out frequency dividing processing on the 10-20 GHz signals output by the phase locking circuit according to an external control level, expanding the signal bandwidth and outputting 10 MHz-20 GHz signals;
the radio frequency output circuit outputs the broadband signal of 10 MHz-20 GHz after attenuation, modulation, amplification and switch filtering.
Further, the reference clock circuit integrates a 100MHz constant temperature crystal oscillator with low phase noise inside, the stability and accuracy of outputting a 100MHz reference signal are determined by an external reference signal, and the phase noise depends on the internal 100MHz constant temperature crystal oscillator; when no reference signal is input from the outside, the internal 100MHz constant temperature crystal oscillator works normally, and a reference signal with the phase noise less than or equal to-150 dBc/Hz@1KHz is provided for the frequency source.
Further, the phase noise of the signal filtered from the harmonic generator output signal of the switch filter bank is 20Log (N) worse than the phase noise of the 100MHz reference signal.
Further, the mixer circuit outputs a variable divider-output signal f RF Dividing into two paths, wherein one path directly performs down-conversion, the other path performs 90 DEG phase shift and then down-conversion, and outputs a signal f from a switch filter bank LO The equal phase power is divided into two paths for down conversion.
Further, the radio frequency output circuit comprises a numerical control attenuator, a modulation switch, an amplifier, a numerical control attenuator, a modulation switch, an amplifier and a switch filter bank II which are sequentially connected.
The beneficial effects of the invention are as follows:
(1) Because a 100MHz constant temperature crystal oscillator with low phase noise is integrated inside, an external reference signal is used for locking the internal 100MHz constant temperature crystal oscillator through an integer phase-locked loop, the stability and accuracy of the output 100MHz reference signal are determined by the external reference signal, the phase noise depends on the internal 100MHz constant temperature crystal oscillator, when no external reference signal is input, the internal 100MHz constant temperature crystal oscillator works normally, the invention can be provided with reference signals with the phase noise of less than or equal to-150 dBc/Hz@1KHz, so that the invention has high reliability, and when the phase noise of the external reference signal is worse than that of the internal constant temperature crystal oscillator, the invention provides reference signals with higher phase noise;
(2) The output signals of the harmonic generator are filtered by the switch filter bank, so that the phase noise of the output end of the phase-locked circuit is improved, and the frequency division signals of the feedback circuit are down-converted to the intermediate frequency through the frequency mixing circuit and enter the phase discriminator to replace more frequency division, so that the frequency division multiple is reduced, and the phase noise of the output end of the phase-locked circuit can be further improved;
(3) The radio frequency output circuit outputs a final signal after attenuation, modulation, amplification and switch filtering of the 10 MHz-20 GHz broadband signal, so that the output power is controllable, the modulation mode is controllable, and harmonic waves and spurious signals are reduced.
(4) Because the variable frequency divider I output signal is divided into two paths and one path is subjected to 90-degree phase shift, and the switching filter group I output signal is divided into equal power, stray components can be mutually offset in synthesis, and stray is further reduced.
(5) The invention has the beneficial effects of wide band, low phase noise, low spurious, controllable output power, controllable modulation mode and the like.
Drawings
FIG. 1 is a schematic diagram of a broadband low phase noise low spurious frequency source configuration of the present invention;
FIG. 2 is a schematic diagram of a phase lock circuit;
FIG. 3 is a schematic diagram of an RF output circuit.
Detailed Description
The invention will be further illustrated with reference to the following figures and examples, which include but are not limited to the following examples.
As shown in fig. 1, the present invention provides a broadband low-phase noise low-spurious frequency source, comprising: the reference clock circuit, the phase-locked circuit, the frequency dividing circuit and the radio frequency output circuit are sequentially connected.
1. Reference clock circuit
The reference clock circuit internally integrates a 100MHz constant temperature crystal oscillator with low phase noise, the internal 100MHz constant temperature crystal oscillator is locked by an external reference signal through an integer phase-locked loop, the stability and accuracy of the output 100MHz reference signal are determined by the external reference signal, and the phase noise depends on the internal 100MHz constant temperature crystal oscillator. When no reference signal is input from the outside, the internal 100MHz constant temperature crystal oscillator works normally, and the phase noise is less than or equal to-150 dBc/Hz@1KHz reference signal can be provided for the frequency source, so that the invention has high reliability, and when the phase noise of the external reference signal is worse than that of the internal constant temperature crystal oscillator, the reference signal with higher phase noise is provided.
2. Phase-locked circuit
As shown in fig. 2, the phase lock circuit includes a power divider, a frequency multiplier, a DDS, a feedback circuit, a phase detector, a loop filter, and a VCO, wherein the feedback circuit includes a harmonic generator, a switch filter bank one, a variable divider one, and a mixer circuit.
The power divider is a 100MHz one-to-two power divider, and outputs 100MHz signals output by the reference clock circuit into two paths, one path of signals is output to the frequency multiplier, and the other path of signals is output to the harmonic generator.
The frequency multiplier receives the 100MHz signal output by the power divider, multiplies the 100MHz signal, outputs the multiplied signal to the DDS, and outputs the 200MHz bandwidth signal to the phase discriminator.
The harmonic generator processes the 100MHz clock signal, outputs harmonic signals with different frequencies to the first switch filter bank, filters the harmonic signals with different frequencies, and outputs 2GHz/2.2GHz/2.4GHz signals to the local oscillation input port of the mixing circuit according to different external input control levels. The phase noise of the switching filter bank is 20Log (N) worse than that of the 100MHz reference signal by about 26dB, 27dB or 28dB, about-124 dBc/Hz@1KHz, -123dBc/Hz@1KHz, -122dBc/Hz@1KHz, and still better than that of the phase-locked circuit output end.
The VCO outputs a signal to the first variable divider, which divides the signal according to an external input control level and outputs the signal to the radio frequency input port of the mixer circuit.
The mixer circuits respectively convert the VCO frequency-converted signals f (output by the variable frequency divider) received by the radio frequency input ports RF And a signal f (output by switch filter bank) received by local oscillation input port LO Down-converting, synthesizing the two paths of signals, and outputting intermediate frequency signals to a phase discriminator. To reduce spurious outputs, the mixer circuit may also divide the output signal f of the variable divider one RF The power is divided into two paths, one path is directly subjected to down-conversion,the other path is subjected to 90-degree phase shifting and then down-conversion, and the equivalent power of the 2GHz/2.2GHz/2.4GHz signal output by the switch filter bank is divided into two paths for down-conversion respectively, so that two paths of frequency conversion radio frequency signals f RF Two local oscillation signals f with phase difference of 90 DEG LO The phases are the same, intermediate frequency spurious components cancel each other in the combining process, and output spurious signals are reduced. The frequency division multiple can be reduced by adopting a mode that the frequency division signal of the feedback circuit is down-converted to the intermediate frequency by the frequency mixing circuit and enters the phase discriminator, and the phase noise of the output end of the phase-locked circuit is improved.
The phase discriminator carries out phase discrimination processing on the intermediate frequency signal output by the feedback circuit and the 200MHz bandwidth signal output by the DDS, and then outputs a phase discrimination voltage signal through the loop filter to control the VCO to output 10-20 GHz signals.
3. Frequency dividing circuit
The frequency dividing circuit comprises a variable frequency divider II, and carries out frequency dividing processing on the 10-20 GHz signals output by the phase locking circuit according to an external control level, expands the signal bandwidth and outputs the 10 MHz-20 GHz signals.
4. Radio frequency output circuit
The radio frequency output circuit outputs 10 MHz-20 GHz broadband signals through attenuation, modulation, amplification and switch filtering treatment, and finally outputs low-phase-noise and low-spurious 10 MHz-20 GHz signals. Specifically, as shown in fig. 3, the radio frequency output circuit is composed of a numerical control attenuator, a modulation switch, an amplifier, a numerical control attenuator, a modulation switch, an amplifier and a switch filter group II which are sequentially connected. The output power is controllable through the numerical control attenuator, the modulation mode is controllable through the modulation switch, and the output harmonic wave and spurious emissions are reduced through the second switch filter bank.

Claims (5)

1. A broadband low phase noise low spurious frequency source comprising: the reference clock circuit, the phase-locked circuit, the frequency dividing circuit and the radio frequency output circuit are sequentially connected;
the reference clock circuit locks an internal 100MHz constant-temperature crystal oscillator by utilizing an external reference signal through an integer phase-locked loop and outputs a 100MHz clock signal to the phase-locked circuit;
the phase-locked circuit comprises a power divider, a frequency multiplier, a DDS, a feedback circuit, a phase discriminator, a loop filter and a VCO, wherein the power divider is a 100MHz one-to-two power divider, and outputs a 100MHz signal power outputted by the reference clock circuit into two paths, one path is outputted to the frequency multiplier, and the other path is outputted to the feedback circuit; the frequency multiplier performs frequency multiplication processing on the signal output by the power divider and outputs the signal to the DDS, and the DDS outputs a 200MHz bandwidth signal to the phase discriminator; the feedback circuit consists of a harmonic generator, a first switch filter bank, a first variable frequency divider and a mixer circuit, wherein the harmonic generator processes signals output by the power divider, outputs harmonic signals with different frequencies to the first switch filter bank, filters the harmonic signals with different frequencies by the first switch filter bank, and outputs 2GHz, 2.2GHz or 2.4GHz signals to a local oscillation input port of the mixer circuit according to different external input control levels; the VCO outputs a signal to the first variable divider, and the first variable divider divides the frequency of the signal according to an external input control level and outputs the signal to a radio frequency input port of the mixer circuit; the mixing circuit respectively performs down-conversion and synthesis on the output signal of the switch filter group I and the output signal of the variable frequency divider I, and outputs an intermediate frequency signal to the phase discriminator; the phase discriminator performs phase discrimination processing on the intermediate frequency signal output by the feedback circuit and the 200MHz bandwidth signal output by the DDS, and then outputs a phase discrimination voltage signal through the loop filter to control the VCO to output 10-20 GHz signals;
the frequency dividing circuit comprises a variable frequency divider II, and is used for carrying out frequency dividing processing on the 10-20 GHz signals output by the phase locking circuit according to an external control level, expanding the signal bandwidth and outputting 10 MHz-20 GHz signals;
the radio frequency output circuit outputs the broadband signal of 10 MHz-20 GHz after attenuation, modulation, amplification and switch filtering.
2. A broadband low phase noise low spurious frequency source according to claim 1, wherein: the reference clock circuit internally integrates a 100MHz constant temperature crystal oscillator with low phase noise, the stability and accuracy of outputting a 100MHz reference signal are determined by an external reference signal, and the phase noise depends on the internal 100MHz constant temperature crystal oscillator; when no reference signal is input from the outside, the internal 100MHz constant temperature crystal oscillator works normally, and a reference signal with the phase noise less than or equal to-150 dBc/Hz@1KHz is provided for the frequency source.
3. A broadband low phase noise low spurious frequency source according to claim 1, wherein: the phase noise of the signal filtered from the harmonic generator output signal of the switch filter bank is 20Log (N) worse than that of the 100MHz reference signal.
4. A broadband low phase noise low spurious frequency source according to claim 1, wherein: the mixer circuit outputs a variable frequency divider-output signal f RF Dividing into two paths, wherein one path directly performs down-conversion, the other path performs 90 DEG phase shift and then down-conversion, and outputs a signal f from a switch filter bank LO The equal phase power is divided into two paths for down conversion.
5. A broadband low phase noise low spurious frequency source according to claim 1, wherein: the radio frequency output circuit comprises a numerical control attenuator, a modulation switch, an amplifier, a numerical control attenuator, a modulation switch, an amplifier and a switch filter bank II which are sequentially connected.
CN202310831801.1A 2023-07-07 2023-07-07 Broadband low-phase-noise low-spurious-frequency source Pending CN116915247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310831801.1A CN116915247A (en) 2023-07-07 2023-07-07 Broadband low-phase-noise low-spurious-frequency source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310831801.1A CN116915247A (en) 2023-07-07 2023-07-07 Broadband low-phase-noise low-spurious-frequency source

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CN116915247A true CN116915247A (en) 2023-10-20

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