CN116913349A - Erasing interference detection method, repairing method, device, chip and electronic equipment - Google Patents
Erasing interference detection method, repairing method, device, chip and electronic equipment Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
- G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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Abstract
The application relates to the technical field of memory chips, and particularly discloses an erasure interference detection method, a repair method, a device, a chip and electronic equipment, wherein the detection method comprises the following steps: in the first erasing operation after the chip is powered on, erasing interference detection is carried out based on full address detection; in the non-first erasing operation after the chip is powered on, erasing interference detection is performed based on random detection or polling detection; according to the detection method, the full address detection of erase interference is carried out in the first erase operation after the chip is powered on, so that the erase interference repair is carried out on the memory units with the erase interference problem, all the memory units with the erase interference phenomenon, which are generated by the erase operation before the power-off and the erase rotation in the chip, can be detected for timely repair, and the reliability and the accuracy of the erase interference detection can be effectively improved.
Description
Technical Field
The application relates to the technical field of memory chips, in particular to an erasure interference detection method, a repair device, a chip and electronic equipment.
Background
The erase operation is a main operation mode of the memory chip, and for the nonvolatile memory, as the number of times of programming and erasing increases, the erase performance tends to be poor, the phenomenon that the erase time is obviously prolonged and the data in the un-erased area is easy to change is shown, the phenomenon is called erase disturbance in the industry, the erase disturbance can cause the data to change and cause the error of the data stored in the chip, so that the detection and repair of the erase disturbance are indispensable in the erase operation.
In the prior art, a random address generating circuit is generally selected to generate a random address for erasure interference detection and repair in erasure operation, but the erasure interference detection mode can generate the same address for erasure interference detection and repair after the chip is powered up, and the main reason is that the prior random address is generated based on configuration information obtained by the chip power up, and the last power up and the next power up are not different for the chip, so that the addresses for detection and repair of the first erasure interference after the power up are the same, if the chip fails under the condition that the erasure interference detection and repair are not completed, the first erasure operation after the power up again only carries out erasure interference detection and repair treatment on the same address, so that the memory cells with erasure interference problems before the power down cannot be effectively repaired, and the erasure interference phenomenon is deepened after the power down for many times, a large number of memory cells with error stored data exist in the chip, and the reliability of the prior erasure interference detection and repair treatment is insufficient.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The application aims to provide an erasure interference detection method, a repair device, a chip and electronic equipment, so as to improve the reliability of the erasure interference detection method.
In a first aspect, the present application provides an erase disturbance detection method for detecting whether an erase disturbance phenomenon exists in a chip, the detection method including the steps of:
in the first erasing operation after the chip is powered on, erasing interference detection is carried out based on full address detection;
and in the non-first erasing operation after the chip is powered up, erasing interference detection is performed based on random detection or polling detection.
The method for detecting the erase disturbance detects the full address of the erase disturbance in the first erase operation after the chip is powered up so as to carry out erase disturbance repair on the memory units with the erase disturbance problem, can detect all the memory units with the erase disturbance phenomenon generated by the erase operation before the power-down and the erase rotation in the chip so as to carry out timely repair, can effectively improve the reliability and the accuracy of the erase disturbance detection, and can carry out random detection or polling detection of the erase disturbance in the non-first erase operation after the chip is powered up so as to carry out erase disturbance repair on the memory units with the erase disturbance problem, thereby ensuring that the erase operation of the chip under long-time operation after the power-up can be carried out efficiently.
The erasure interference detection method, wherein the size of the erasure area corresponding to the erasure operation is consistent with the size of the detection area of the random detection or the polling detection.
The detection design mode reasonably plans the size of the detection object, for example, the total sum of the erasure areas of multiple erasure operations covers the storage array of the whole chip, and the total sum of the detection areas of random detection or polling detection under reasonable design can also cover the storage array of the whole chip, which is equivalent to the completion of erasure interference detection of the whole storage array, meets the chip detection requirement and can ensure that the erasure operations are performed efficiently.
The erase disturb detection method, wherein the erase operation is a block erase or a sector erase.
In the erase disturbance detection method, when the erase operation is block erase, the object of the full address detection is all blocks except the block corresponding to the erase operation and connected with the block based on the same substrate.
The erasing interference detection method is characterized in that the random detection is performed by selecting the address generated by the random address generation circuit.
According to the erase disturbance detection method, the polling detection is performed on the basis of the addresses outside the erase area corresponding to the selected erase operation in the preset sequence.
In a second aspect, the present application also provides an erasure disturbing repair method for detecting and repairing an erasure disturbing phenomenon in a chip, the repair method comprising:
in the first erasing operation after the chip is powered on, erasing interference detection and repair are performed based on full address detection;
and in the non-first erasing operation after the chip is powered up, erasing interference detection and repair are performed based on random detection or polling detection.
The method for repairing the erase disturbance detects and repairs the full address of the erase disturbance in the first erase operation after the chip is powered up, can detect and timely repair all the memory units with the erase disturbance phenomenon generated by the erase operation before the power-down and the erase rotation in the chip, can effectively improve the reliability and the accuracy of the erase disturbance detection, and can perform random detection or polling detection and repair of the erase disturbance in the non-first erase operation after the chip is powered up, thereby ensuring that the erase operation of the chip under long-time operation after the power-up can be performed efficiently.
In a third aspect, the present application further provides an erasure disturbing detection apparatus for detecting whether an erasure disturbing phenomenon exists in a chip, the detection apparatus including:
the first detection module is used for performing erasure interference detection based on full address detection in the first erasure operation after the chip is powered on;
and the second detection module is used for performing erasure interference detection based on random detection or polling detection in the non-first erasure operation after the chip is powered up.
The erasing interference detection device provided by the application can be used for carrying out the full address detection of erasing interference in the first erasing operation after the chip is powered on so as to carry out erasing interference repair on the memory cells with the erasing interference problem, and can be used for detecting all the memory cells with the erasing interference phenomenon generated by the erasing operation before the power-off and the erasing rotation in the chip so as to carry out timely repair, thereby effectively improving the reliability and the accuracy of the erasing interference detection.
In a fourth aspect, the present application also provides a memory chip comprising a control circuit and a memory array, the memory chip operating the detection method as provided in the first aspect or the repair method as provided in the second aspect based on the control circuit.
In a fifth aspect, the present application also provides an electronic device comprising a memory chip as provided in the fourth aspect.
The application provides an erasure interference detection method, a repair method, a device, a chip and an electronic device, wherein the erasure interference detection method detects the full address of erasure interference in the first erasure operation after the chip is powered on to perform erasure interference repair on the memory units with erasure interference problems, can detect all the memory units with erasure interference phenomena generated by the erasure operation before the power-off and the erasure rotation in the chip to perform timely repair, can effectively improve the reliability and the accuracy of erasure interference detection, and performs random detection or polling detection of erasure interference in the non-first erasure operation after the chip is powered on to perform erasure interference repair on the memory units with erasure interference problems, thereby ensuring that the erasure operation of the chip in long-time operation after the power-on can be performed efficiently.
Drawings
Fig. 1 is a flowchart of an erase disturbance detection method according to an embodiment of the present application.
Fig. 2 is a flowchart of an erase disturbance repair method according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of an erasure disturbing detection apparatus according to an embodiment of the present application.
Reference numerals: 301. a counting module; 302. a judging module; 303. a first detection module; 304. and a second detection module.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, some embodiments of the present application provide an erase disturb detection method for detecting whether an erase disturb phenomenon exists in a chip, the detection method including the steps of:
in the first erasing operation after the chip is powered on, erasing interference detection is carried out based on full address detection;
and in the non-first erasing operation after the chip is powered up, erasing interference detection is performed based on random detection or polling detection.
Specifically, the erasure interference detection method of the embodiment of the application is mainly applied to flash memory serial chips, in particular to non flash.
More specifically, the nor flash stores data based on memory cells arranged in an array, and the memory cells change the electron binding amount in the floating gate through external input voltages (such as erase voltage and programming voltage) to change the threshold voltage (Vth) of the MOS transistor so as to change the value (expressed as data 0 or 1) of the stored data; the erase operation is an execution command that applies an erase voltage to memory cells in a certain area to adjust the threshold voltage of the memory cells in the erase area to a voltage range corresponding to the erase state, and since the memory cells in other areas in the whole memory array are all connected to the erase area through the substrate, the gate voltages of the memory cells in the other areas are not equal to the substrate voltage, and at this time, a voltage difference exists between the gate and the substrate, which can generate a slight erase effect on the memory cells in the other sectors of the array in the program state (represented as data 0), the threshold voltages of the memory cells drop below the program verification voltage and are in a weak 0 state, and even the original data 0 is converted into data 1, so that the data in the memory areas which are not in the erase operation are changed, which is called erase interference, which can cause the error of the memory data of the original non flash and need to be detected and repaired by the erase interference in the erase operation.
More specifically, the erase operation includes erase processes in which erase voltages of different magnitudes are applied to the memory cells in a plurality of stages, and erase disturbance detection and repair are performed as processing actions performed after all the erase processes are completed in the erase operation.
More specifically, the weak 0 state is a state where the threshold voltage of the memory cell is slightly below or near the lower threshold voltage of data 0.
More specifically, the erase disturbance detection is a detection behavior for detecting each memory cell in the selected area to determine whether the data of the memory cell has changed due to a previous erase behavior, and the detection process is a common means of non flash, which is not described in detail herein; the erase disturbance detection method of the embodiment of the application aims to provide an improved and reliable address selection logic for erase disturbance detection aiming at unexpected power failure of a chip so as to improve the reliability of erase disturbance detection.
More specifically, the erase disturbance detection method of the embodiment of the present application includes two address selection logics, which are respectively used for providing operation addresses for erase disturbance detection operations in a first erase operation after the chip is powered up and in a non-first erase operation after the chip is powered up, wherein the full address detection is to perform erase disturbance detection for all addresses (i.e. all memory cells) in the selected chip, and since the first erased area inevitably does not have a problem of data change caused by erase disturbance, the full address detection of erase disturbance is further preferably to perform erase disturbance detection for all addresses in the selected chip except the first erased area after the chip is powered up; the random detection or polling detection is to select local addresses outside the area erased by the round (the first time after non-power-on) in the chip to carry out erasure interference detection, wherein the random detection is to randomly select local storage areas to carry out detection, and the polling detection is to select local storage areas to carry out detection according to a preset sequence, and both belong to the address selection detection modes available in the existing erasure interference detection.
In the method, the full address detection of the erase disturbance is performed in the first erase operation after the chip is powered up so as to perform erase disturbance repair on the memory cells with erase disturbance problems, all the memory cells with erase disturbance phenomena generated by the erase operation before the power down and the erase rotation in the chip can be detected so as to perform timely repair, the problem that the erase disturbance phenomena caused by the erase operation before the power down cannot be timely found to cause data errors is avoided, the problem that the erase disturbance accumulation is too deep to cause the follow-up repair time is avoided, the reliability and the accuracy of the erase disturbance detection can be effectively improved, the random detection or the polling detection of the erase disturbance is performed in the non-first erase operation after the chip is powered up so as to perform the erase disturbance repair on the memory cells with erase disturbance problems, and the erase operation of the chip under the long-time running after the power up can be ensured to be efficiently performed.
In some preferred embodiments, the size of the erase region corresponding to the erase operation corresponds to the size of the detection region of random detection or polling detection.
Specifically, the detection area of random detection or polling detection is set to be consistent with the size of the erasure area corresponding to the erasure operation, so that the erasure interference detection and repair can be ensured to be performed efficiently, and the time increase of the erasure operation caused by the excessive time occupied by the erasure interference detection and repair in the erasure operation is avoided; the detection design mode reasonably plans the size of the detection object, for example, the total sum of the erasure areas of multiple erasure operations covers the storage array of the whole chip, and the total sum of the detection areas of random detection or polling detection under reasonable design can also cover the storage array of the whole chip, which is equivalent to the completion of erasure interference detection of the whole storage array, meets the chip detection requirement and can ensure that the erasure operations are performed efficiently.
In some preferred embodiments, the erase operation is a block erase or a sector erase.
Specifically, the erase operation of the nor flash may be divided into array erase, block erase, and sector erase, where the array erase is to erase all memory cells of one memory array in an array chip, and for a chip having a plurality of memory arrays, memory cells of different memory arrays are not located on the same substrate, so that erase interference problem will not occur between different memory arrays, and therefore in the erase interference detection method of the embodiment of the present application, the array erase does not need to perform erase interference detection processing.
Note that the full address detection, random detection, or polling detection are all performed for the memory cells in the memory array where the area of the erase operation is located.
More specifically, the detection area of random detection or polling detection is set to coincide with the size of the erasure area corresponding to the erasure operation, and then the object of random detection or polling detection corresponds to a block or sector.
In some preferred embodiments, when the erase operation is a block erase, the objects of full address detection are all blocks other than the block to which the erase operation corresponds and connected with the block based on the same substrate.
Specifically, in this embodiment, the full address detection can perform erase disturb detection on the memory cells in all the blocks that may be disturbed by erase in the first erase operation after the chip is powered on, so that it is possible to effectively avoid that erase disturb generated by the power-down behavior of the chip before the power-on behavior affects the data storage in the chip.
In some preferred embodiments, the random detection is performed by selecting an address generated by the random address generation circuit.
Specifically, the random address generating circuit is an address generating circuit designed for repairing erasure interference in the nor flash, and the circuit structure is not repeated here, and the random address generating circuit generates a random address based on configuration information determined by chip power-on, and the address generated for the first time after the chip power-on is generally fixed, so the random address generating circuit belongs to a pseudo random address generating circuit; for the erase operation of power-up after multiple power-down, if the first erase operation after power-up directly adopts the address selected by the random address generating circuit to perform erase interference detection, the detected addresses of the first detection based on the address generated by the random address generating circuit are consistent, and the area of erase interference generated before power-down cannot be detected and repaired, so that the serious erase interference phenomenon is caused, if the design of the existing circuit is modified, the circuit design cost and the area are increased.
In some preferred embodiments, the polling detection is performed based on a preset sequence of selecting addresses outside the erase region to which the erase operation corresponds.
Specifically, the polling detection is erase disturbance detection performed in an address detection selection order according to the chip operation characteristics (the erasing characteristics and the characteristics of the occurrence range of erase disturbance), for example, for the erase operation performed on the block numbered n, the object of the polling detection is the block numbered n+1.
Based on the foregoing, it can be seen that the erase disturbance detection method according to the embodiment of the present application is equivalent to selecting an appropriate address detection mode to complete erase disturbance detection based on the number of erase operations or the number of rounds after power-up, so as shown in fig. 1, in some embodiments, the detailed execution steps of the erase disturbance detection method according to the embodiment of the present application are as follows:
a1, acquiring the number x of times of erasing operation executed by a chip after power-on;
a2, judging whether x is larger than 1, if yes, jumping to a step A4, otherwise, executing a step A3;
a3, performing erasure interference detection on all storage areas except the erasure area for performing erasure operation based on full address detection;
a4, performing erasure interference detection based on random detection or polling detection.
In a second aspect, some embodiments of the present application provide an erase disturb repair method for detecting and repairing erase disturb phenomenon in a chip, the repair method including:
in the first erasing operation after the chip is powered on, erasing interference detection and repair are performed based on full address detection;
and in the non-first erasing operation after the chip is powered up, erasing interference detection and repair are performed based on random detection or polling detection.
Specifically, the erase disturbance detection and repair includes an erase disturbance detection behavior and an erase disturbance repair behavior, wherein the erase disturbance repair is a program verify operation, and is used for reprogramming the stored data of the memory cell having the erase disturbance phenomenon to data 0, i.e. programming the threshold voltage thereof to be above the program verification voltage, as the name implies the operation behavior of enhancing the program data.
In the method, the full address detection and repair of the erase disturbance are carried out in the first erase operation after the chip is powered up, all the memory units with erase disturbance phenomena generated by the erase operation before the power failure and the erase rotation in the chip can be detected and repaired in time, the problem that the erase disturbance phenomena caused by the erase operation before the power failure cannot be found in time to cause data errors is avoided, the problem that the erase disturbance accumulation is too deep to cause the subsequent repair time to be long due to the erase operation before the power failure and the erase operation after the power failure is avoided, the reliability and the accuracy of the erase disturbance detection can be effectively improved, the random detection or the polling detection and repair of the erase disturbance are carried out in the non-first erase operation after the chip is powered up, and the efficient erase operation under the long-time operation after the power failure of the chip can be ensured.
The erase disturbance repair method of the embodiment of the present application is equivalent to selecting a suitable address detection mode to complete erase disturbance detection and repair based on the number of erase operations or the number of rounds after power-up, so as shown in fig. 2, in some embodiments, the detailed execution steps of the erase disturbance repair method of the embodiment of the present application are as follows:
b1, acquiring the number x of times of erasing operation executed by a chip after power-on;
b2, judging whether x is larger than 1, if yes, jumping to a step B4, otherwise, executing a step B3;
b3, performing erasure interference detection and repair on all storage areas except the erasure area for performing the erasure operation based on full address detection;
and B4, performing erasure interference detection and repair based on random detection or polling detection.
In a third aspect, some embodiments of the present application further provide an erase disturbance detection apparatus for detecting whether an erase disturbance phenomenon exists in a chip, where the detection apparatus includes:
the first detection module 303 is configured to perform erase interference detection based on full address detection in a first erase operation after the chip is powered on;
the second detection module 304 is configured to perform erase disturbance detection based on random detection or polling detection in a non-first erase operation after the chip is powered up.
The erasing interference detection device provided by the embodiment of the application can detect the full address of the erasing interference in the first erasing operation after the chip is powered on so as to carry out erasing interference repair on the memory units with the erasing interference problem, can detect all the memory units with the erasing interference phenomenon, which are generated by the erasing operation before the power-off and the erasing rotation of the chip, so as to carry out timely repair, and can effectively improve the reliability and the accuracy of the erasing interference detection.
In some preferred embodiments, as shown in fig. 3, the detection device further comprises:
a counting module 301, configured to obtain the number of times of the erase operation performed by the chip after power-up;
the judging module 302 is configured to judge whether the current erase operation is the first erase operation after the chip is powered up according to the number of erase operations performed after the chip is powered up.
In some preferred embodiments, the erase disturbance detection apparatus according to the embodiments of the present application is configured to perform the erase disturbance detection method provided in the first aspect.
In a fourth aspect, some embodiments of the present application further provide a memory chip, where the memory chip includes a control circuit and a memory array, and the memory chip operates the detection method as provided in the first aspect or the repair method as provided in the second aspect based on the control circuit.
In a fifth aspect, some embodiments of the present application also provide an electronic device, including a memory chip as provided in the fourth aspect.
In summary, the embodiment of the application provides an erasure interference detection method, a repair method, a device, a chip and an electronic device, wherein the erasure interference detection method detects full addresses of erasure interference in a first erasure operation after the chip is powered on to perform erasure interference repair on memory units with erasure interference problems, can detect all the memory units with erasure interference phenomena generated by the erasure operation before the power-off and the erase rotation in the chip to perform timely repair, can effectively improve the reliability and the accuracy of erasure interference detection, and performs random detection or polling detection of erasure interference in a non-first erasure operation after the chip is powered on to perform erasure interference repair on the memory units with erasure interference problems, thereby ensuring that the erasure operation under long-time operation after the chip is powered on can be performed efficiently.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. An erasure disturbing detection method for detecting whether an erasure disturbing phenomenon exists in a chip, the detection method comprising the steps of:
in the first erasing operation after the chip is powered on, erasing interference detection is carried out based on full address detection;
and in the non-first erasing operation after the chip is powered up, erasing interference detection is performed based on random detection or polling detection.
2. The erasure disturbance detection method according to claim 1, wherein a size of an erasure area corresponding to the erasure operation coincides with a size of a detection area of the random detection or the polling detection.
3. The erase disturb detection method of claim 1, wherein the erase operation is a block erase or a sector erase.
4. The erasure disturbance detection method according to claim 3, wherein when the erasure operation is a block erasure, the objects of the full address detection are all blocks other than the block corresponding to the erasure operation and connected with the block based on the same substrate.
5. The erasure disturbance detection method according to claim 1, wherein the random detection is performed by selecting an address generated by a random address generation circuit.
6. The erasure disturbance detection method according to claim 1, wherein the polling detection is performed based on an address outside an erasure area to which the predetermined sequence selects the erasure operation.
7. An erase disturb repair method for detecting and repairing erase disturb phenomenon in a chip, the repair method comprising:
in the first erasing operation after the chip is powered on, erasing interference detection and repair are performed based on full address detection;
and in the non-first erasing operation after the chip is powered up, erasing interference detection and repair are performed based on random detection or polling detection.
8. An erasure disturbing detection apparatus for detecting whether or not an erasure disturbing phenomenon exists in a chip, the detection apparatus comprising:
the first detection module is used for performing erasure interference detection based on full address detection in the first erasure operation after the chip is powered on;
and the second detection module is used for performing erasure interference detection based on random detection or polling detection in the non-first erasure operation after the chip is powered up.
9. A memory chip comprising a control circuit and a memory array, the memory chip operating the detection method according to any one of claims 1-6 or the repair method according to claim 7 based on the control circuit.
10. An electronic device comprising the memory chip of claim 9.
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