CN116885058A - Micro LED preparation method and Micro LED - Google Patents

Micro LED preparation method and Micro LED Download PDF

Info

Publication number
CN116885058A
CN116885058A CN202310905128.1A CN202310905128A CN116885058A CN 116885058 A CN116885058 A CN 116885058A CN 202310905128 A CN202310905128 A CN 202310905128A CN 116885058 A CN116885058 A CN 116885058A
Authority
CN
China
Prior art keywords
layer
etching
inorganic protective
micro led
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310905128.1A
Other languages
Chinese (zh)
Inventor
汪恒青
张星星
林潇雄
胡加辉
金从龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangxi Zhao Chi Semiconductor Co Ltd
Original Assignee
Jiangxi Zhao Chi Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangxi Zhao Chi Semiconductor Co Ltd filed Critical Jiangxi Zhao Chi Semiconductor Co Ltd
Priority to CN202310905128.1A priority Critical patent/CN116885058A/en
Publication of CN116885058A publication Critical patent/CN116885058A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Led Devices (AREA)

Abstract

The application provides a preparation method of a Micro LED and the Micro LED, wherein the method comprises the following steps: providing a substrate, sequentially depositing an epitaxial layer, a transparent conductive layer, a metal electrode layer, an inorganic protective layer and an etching photoresist layer on the substrate, etching by using a dry method, and introducing CF with a preset flow rate ratio 4 With O 2 Etching the etching photoresist layer to a preset position, removing the etching photoresist layer by total etching and removing the inorganic protective layer by partial etching, and depositing a metal pad layer on the surface of the inorganic protective layer after the partial etching to obtain the Micro LEDAnd the surface is flattened by combining an etching process, so that a flat metal pad layer is conveniently manufactured, and the yield of the chip in the mass transfer and subsequent bonding processes is improved.

Description

Micro LED preparation method and Micro LED
Technical Field
The application belongs to the technical field of LEDs, and particularly relates to a Micro LED preparation method and a Micro LED.
Background
Conventional LED chips are die-bonded by means of solder, and Micro LED chips are die-bonded by means of metal bonding or ACF film (anisotropic conductive film) because the bonding pad area is too small (less than 10 μm) and die bonding is difficult to use by means of solder.
The solder paste has fluidity during soldering, the uneven surface of the bonding pad of the chip can be filled by the solder paste, but for Micro LED chips, metal bonding (Au-Au, au-In, au-Cu, cu-In and the like) can be basically only relied on, the uneven surface of the bonding pad can cause low yield during bonding, the prior art also has the flattening process, but the grinding is difficult to accurately control the thickness reduction, and the requirement of accurately controlling the size is difficult to meet when the thickness of the chip is required to be In a micron level.
Disclosure of Invention
In order to solve the technical problems, the application provides a preparation method of a Micro LED and the Micro LED, so as to solve the problems in the background art.
In a first aspect, an embodiment of the present application provides the following technical solutions, a method for preparing a Micro LED, including the following steps:
s1, providing a substrate, and sequentially growing an N-type GaN layer, a multiple quantum well layer and a P-type GaN layer on the substrate to obtain an epitaxial layer;
s2, using an ISO coating as a first mask to carry out photoresist coating and photoetching on the epitaxial layer, and then carrying out ICP etching on the epitaxial layer to form a plurality of channels on the epitaxial layer;
s3, depositing a transparent conductive layer on the epitaxial layer, sequentially performing photoresist coating and photoetching treatment on the surface of the transparent conductive layer to form a first pattern layer, putting the transparent conductive layer into etching liquid for etching treatment based on the first pattern layer, and performing annealing treatment after cleaning;
s4, photoresist coating and photoetching are carried out by using the MESA layer as a second mask, and then ICP etching is carried out on the epitaxial layer so as to form an N-type semiconductor MESA on the epitaxial layer;
s5, evaporating a metal electrode layer on the surface of the epitaxial layer;
s6, depositing an inorganic protective layer on the surfaces of the metal electrode layer and the epitaxial layer, and depositing a photoresist layer on the inorganic protective layer;
s7, using dry etching and introducing CF with preset flow ratio 4 With O 2 Etching the etching photoresist layer to a preset position so as to remove all etching photoresist layer and remove part of the inorganic protective layer;
s8, sequentially performing photoresist coating and photoetching treatment on the surface of the inorganic protective layer after the partial etching is finished to form a second image layer, and introducing CF based on the second image layer 4 And etching the inorganic protective layer to expose part of the metal electrode layer, and evaporating a bonding pad metal layer on the exposed metal electrode layer to obtain the Micro LED.
Compared with the prior art, the application has the beneficial effects that: CF in the present application 4 The etching rate of the gas to the inorganic protective layer is high, the etching rate to the etching photoresist layer is low, and O in the application 2 The etching rate of the gas for etching the photoresist layer is high, the etching rate of the inorganic protective layer is low, and the CF is arranged 4 Gas and O 2 The etching rate of the inorganic protective layer and the etching photoresist layer reaches 1:1, after the photoresist is spin-coated on the surface, the surface gully of the inorganic protective layer can be filled to obtain a flat surface, then etching is carried out, the flat inorganic protective layer can be obtained after the photoresist is completely etched, the residual thickness of the inorganic protective layer after the etching is finished can be precisely controlled by controlling the thickness and the etching rate of the etching photoresist layer, and in the application, the inorganic protective layer is used as the filling of the high and low fluctuation in the front process of the chip, the surface is flattened by combining with the etching process, and the flat metal pad layer is conveniently manufactured, thereby being beneficial to improving the mass transfer and the subsequent bonding process of the chipIs a good yield of (a).
Preferably, the substrate is a Si substrate, a SiC substrate, a ZnO substrate, or a sapphire substrate.
Preferably, the transparent conductive layer is used for connecting the P-type GaN layer and the metal electrode layer, the transparent conductive layer is made of GIO, ZITO, ITO or nano silver wire, and the resistivity of the transparent conductive layer is lower than that of the P-type GaN layer.
Preferably, in the step S3, the soaking time ranges from 3min to 15min, and the temperature range of the annealing furnace ranges from 450 ℃ to 650 ℃.
Preferably, the thickness of the metal electrode layer ranges from 1 μm to 3 μm.
Preferably, the inorganic protective layer comprises a reflective layer and a single-layer insulating layer, wherein the reflective layer is made of SiO 2 With Ti 3 O 5 A DBR structure comprising a single insulating layer made of SiO 2 、Al 2 O 3 、Ti 3 O 5 The thickness of the reflecting layer ranges from 0.5 mu m to 2 mu m, and the thickness of the single-layer insulating layer ranges from 2 mu m to 10 mu m.
Preferably, in the step S7, CF 4 With O 2 The preset flow ratio of (2) is 7:1-15:1.
Preferably, in the step S7, CF 4 Is 145sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 3-15 mtorr, the ICP power is 400-1500W, and the RF power is 50-700W.
Preferably, in the step S8, CF 4 The flow range of the etching solution is 70 sccm-150 sccm, the etching pressure is 3-15 mtorr, and the etching time is 10-30 min.
In a second aspect, the embodiment of the application further provides a Micro LED, which is prepared by the Micro LED preparation method.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for preparing Micro LEDs provided by an embodiment of the application;
fig. 2 is a schematic diagram of a semi-finished product generated in step S1 of the Micro LED manufacturing method according to the embodiment of the present application;
fig. 3 is a schematic diagram of a semi-finished product generated in step S3 of the Micro LED manufacturing method according to the embodiment of the present application;
fig. 4 is a schematic diagram of a semi-finished product generated in step S4 of the Micro LED manufacturing method according to the embodiment of the present application;
fig. 5 is a schematic diagram of a semi-finished product generated in step S5 of the Micro LED manufacturing method according to the embodiment of the present application;
fig. 6 is a schematic diagram of a semi-finished product generated in step S6 of the Micro LED manufacturing method according to the embodiment of the present application;
fig. 7 is a schematic diagram of a semi-finished product generated in step S7 of the Micro LED manufacturing method according to the embodiment of the present application;
fig. 8 is a schematic diagram of a finished product generated in step S8 of the Micro LED manufacturing method according to the embodiment of the present application;
fig. 9 is a schematic structural diagram of a Micro LED according to another embodiment of the present application.
Reference numerals illustrate:
embodiments of the present application will be further described with reference to the accompanying drawings.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the application and should not be construed as limiting the application.
In the description of the embodiments of the present application, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the embodiments of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present application, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
In the embodiments of the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present application will be understood by those of ordinary skill in the art according to specific circumstances.
Example 1
As shown in fig. 1, a first embodiment of the present application provides a method for preparing a Micro LED, which includes the following steps:
as shown in fig. 2, S1, a substrate 1 is provided, and an N-type GaN layer 2, a multiple quantum well layer 3 and a P-type GaN layer 4 are sequentially grown on the substrate 1 to obtain an epitaxial layer;
specifically, the substrate 1 is a Si substrate, a SiC substrate, a ZnO substrate, or a sapphire substrate.
S2, using an ISO coating as a first mask to carry out photoresist coating and photoetching on the epitaxial layer, and then carrying out ICP etching on the epitaxial layer to form a plurality of channels 9 on the epitaxial layer;
specifically, the trenches 9 are formed above the substrate 1, and the whole chip can be divided into several chiplets according to the trenches 9 in the subsequent chip dividing process by etching the epitaxial layer and forming several trenches 9.
S3, depositing a transparent conductive layer 5 on the epitaxial layer, sequentially performing photoresist coating and photoetching treatment on the surface of the transparent conductive layer 5 to form a first layer, putting the transparent conductive layer 5 into etching solution for etching treatment based on the first layer, and performing annealing treatment after cleaning;
the step S3 specifically includes: depositing a transparent conductive layer 5 on the epitaxial layer, coating a layer of photoresist on the surface of the transparent conductive layer 5, photoetching the transparent conductive layer 5 by utilizing a photoetching technology to form a first pattern layer on the photoresist, taking the first pattern layer as a first barrier layer, soaking the transparent conductive layer 5 in etching liquid, etching the transparent conductive layer 5 which is not covered by the first barrier layer, removing the photoresist on the epitaxial layer, cleaning, and then putting the etched transparent conductive layer 5 into an annealing furnace for annealing;
specifically, after the transparent conductive layer 5 is formed by deposition, coating photoresist on the transparent conductive layer 5, and performing photoetching by utilizing a photoetching technology to obtain a first pattern layer, in the subsequent etching process, etching the transparent conductive layer 5 according to the shape of the first pattern layer, wherein the transparent conductive layer 5 wrapped by the photoresist is not etched, and the exposed transparent conductive layer 5 not wrapped by the photoresist is completely etched by etching liquid according to the shape of the first pattern layer, so that the surface shape of the etched transparent conductive layer 5 corresponds to the shape of the first pattern layer;
the transparent conductive layer 5 is used for connecting the P-type GaN layer 4 and the metal electrode layer 6, that is, the transparent conductive layer 5 is used for conducting current from the metal electrode layer 6 to the P-type GaN layer 4, the material of the transparent conductive layer 5 is GIO, ZITO, ITO or nano silver wire, GIO, ZITO, ITO is inorganic material, nano silver wire is organic material, the resistivity of the transparent conductive layer is lower than the resistivity of the P-type GaN layer 4, the material of the transparent conductive layer 5 needs to meet the requirement that the transparency is higher than 80% and the resistivity is lower than the resistivity of the P-type GaN layer 4, in the step S3, particularly taking ITO material as an example, the deposition method of the transparent conductive layer 5 adopts magnetron sputtering to form a high-density transparent conductive layer;
in this embodiment, in the step S3, the soaking time ranges from 3min to 15min, and the annealing furnace temperature ranges from 450 ℃ to 650 ℃.
As shown in fig. 4, S4, performing photoresist coating and photolithography using the MESA layer as a second mask, and performing ICP etching on the epitaxial layer to form an N-type semiconductor MESA 11 on the epitaxial layer;
specifically, the N-type semiconductor mesa 11 is formed on the N-type GaN layer 2, and in the ICP etching process of the epitaxial layer, the multiple quantum well layer 3 and the P-type GaN layer 4 are partially etched, so that the N-type GaN layer 2 is partially exposed, and when the metal electrode layer 6 is evaporated in a subsequent manner, the metal electrode layer 6 can be evaporated on the N-type GaN layer 2 and the P-type GaN layer 4, so that the N-type electrode in the metal electrode layer 6 is arranged on the N-type GaN layer 2, the P-type electrode in the metal electrode layer 6 is arranged on the P-type GaN layer 4, and the N-type electrode in the metal electrode layer 6 is ensured to be communicated with the N-type GaN layer 2, and the P-type electrode is communicated with the P-type GaN layer 4.
As shown in fig. 5, S5, evaporating a metal electrode layer 6 on the surface of the epitaxial layer;
the step S5 specifically includes: coating a layer of negative photoresist on the upper surface of the epitaxial layer, exposing and developing, evaporating a metal electrode layer 6 on the surface of the epitaxial layer by utilizing an electron beam evaporation technology, removing redundant photoresist and the metal electrode layer 6 by utilizing a lift-off technology, and cleaning the surface;
specifically, in this embodiment, the metal electrode layer 6 includes a P-type electrode and an N-type electrode, where the P-type electrode and the N-type electrode are respectively disposed on the P-type GaN layer 4 and the N-type GaN layer 2, and the N-type electrode is specifically disposed on the N-type semiconductor mesa 11, and meanwhile, the metal electrode layer 6 in this embodiment is formed by overlapping multiple layers of metals, and the overlapped metals are specifically Ni, al, ti, au, pt;
meanwhile, in the present embodiment, the thickness of the metal electrode layer 6 ranges from 1 μm to 3 μm.
As shown in fig. 6, S6, depositing an inorganic protective layer 7 on the surfaces of the metal electrode layer 6 and the epitaxial layer, and depositing an etching photoresist layer 8 on the inorganic protective layer 7;
wherein the inorganic protective layer 7 in the present embodiment comprises a reflective layer and a single-layer insulating layer, and the reflective layer is specifically made of SiO 2 With Ti 3 O 5 A DBR structure comprising a single insulating layer made of SiO 2 、Al 2 O 3 、Ti 3 O 5 The thickness range of the reflective layer is 0.5 μm to 2 μm, and the thickness range of the single-layer insulating layer is 2 μm to 10 μm, so that the specific deposition method of the inorganic protective layer 7 in this embodiment is as follows: first, a layer of SiO is deposited on the surface of the metal electrode layer 6 and the epitaxial layer not covered by the metal electrode layer 6 2 With Ti 3 O 5 A reflective layer of a DBR structure, and then a layer of SiO deposited on the reflective layer 2 、Al 2 O 3 、Ti 3 O 5 A single-layer insulating layer, an inorganic protective layer 7 is formed by the single-layer insulating layer and the reflecting layer, and the inorganic protective layer 7 can be formed of SiO 2 、Al 2 O 3 、Ti 3 O 5 Is composed of one or more materials;
meanwhile, in this embodiment, the etching photoresist layer 8 is essentially a photoresist layer, and the etching photoresist layer 8 has good surface planarization capability, so that after the etching photoresist layer 8 is deposited on the inorganic protective layer 7, the etching photoresist layer 8 can completely cover and fill the gaps above the inorganic protective layer 7 to make the surface flat.
As shown in FIG. 7, S7, CF with preset flow ratio is etched and introduced by dry etching 4 With O 2 Etching the etching photoresist layer 8 to a preset position so as to etch the etching photoresist layer8, completely etching and removing the inorganic protective layer 7;
in the present embodiment, in the step S7, CF 4 With O 2 The preset flow ratio of (2) is 7:1-15:1, in the step S7, CF 4 Is 145sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 3-15 mtorr, the ICP power is 400-1500W, the RF power is 50-700W, wherein, the CF 4 With O 2 The preset flow ratio of (2) can be adjusted according to experiments;
in particular, CF 4 O with high etching rate of gas to inorganic protective layer 7 and low etching rate to etching photoresist layer 8 2 The etching rate of the gas to the etching photoresist layer 8 is high and the etching rate of the inorganic protective layer 7 is low, by setting the CF 4 Gas and O 2 The preset flow ratio of the gas can obtain the etching rate of the inorganic protective layer 7 and the etching photoresist layer 8 to reach 1:1, after the photoresist is spin-coated on the surface, the surface gully of the inorganic protective layer 7 can be filled to obtain a flat surface, then etching is carried out, the flat inorganic protective layer 7 can be obtained after the photoresist is completely etched, the residual thickness of the inorganic protective layer 7 after the etching is finished can be precisely controlled by controlling the thickness and the etching rate of the etching photoresist layer 8, and in the application, the inorganic protective layer 7 is used as the filling of the high and low fluctuation in the front-end process of the chip, the surface is flattened by combining with the etching process, and the flat metal pad layer 10 is conveniently manufactured, so that the yield of the chip in the mass transfer and the subsequent bonding process is improved.
As shown in fig. 8, S8, sequentially performing photoresist coating and photolithography on the surface of the inorganic protective layer 7 after the partial etching is completed, so as to form a second layer, and introducing CF based on the second layer 4 Etching the inorganic protective layer 7 to expose part of the metal electrode layer 6, and evaporating a bonding pad metal layer 10 on the exposed metal electrode layer 6 to obtain a Micro LED;
the step S8 specifically includes: coating photoresist on the surface of the inorganic protective layer 7 after the partial etching is finished, and photoetching the photoresist on the surface of the inorganic protective layer 7 by utilizing a photoetching technology so as to obtain the photoresist on the surface of the inorganic protective layer 7Forming a second pattern layer on the photoresist, using dry etching and introducing CF as a second barrier layer 4 Etching the inorganic protective layer 7 according to the second barrier layer to expose part of the metal electrode layer 6, coating negative photoresist on the exposed metal electrode layer 6, exposing and developing, evaporating a metal pad layer 10 on the exposed metal electrode layer 6 by using an electron beam evaporation technology, and removing redundant photoresist and the metal pad layer on the surface by using a lift-off process to obtain a Micro LED;
in the present embodiment, in the step S8, CF 4 The flow range of the etching solution is 70 sccm-150 sccm, the etching pressure is 3-15 mtorr, and the etching time is 10-30 min;
the metal pad layer in the embodiment is formed by overlapping a plurality of layers of metal, wherein the overlapped metal comprises Ni, al, ti, au, pt;
it should be noted that after the photoresist on the surface of the inorganic protective layer 7 is subjected to photolithography, a second pattern layer is correspondingly formed, wherein the second pattern layer has a preset shape, and in the subsequent etching process, the inorganic protective layer 7 not covered by the second barrier layer is etched, so that the metal electrode layer 6 is partially exposed, and then the metal pad layer 10 is evaporated on the exposed metal electrode layer 6;
specifically, the metal pad layer 10 includes a P-type pad and an N-type pad, the P-type pad is correspondingly communicated with the P-type electrode in the metal electrode layer 6, and the N-type pad is correspondingly communicated with the N-type electrode in the metal electrode layer;
it should be noted that after the Micro LED is manufactured, the whole chip obtained in step S8 may be divided into a plurality of small finished Micro LEDs along the channel 9.
In this example, several experimental groups and control groups were introduced for further explanation of the present application.
The experimental groups comprise an experimental group I, an experimental group II, an experimental group III, an experimental group IV, an experimental group five, an experimental group six and an experimental group seven, the control group adopts a Micro LED preparation method in the prior art, and the adopted method is approximately the same as the implementation one, but the differences are as follows:the control group was conventional in the prior art, i.e. without CF 4 With O 2 。
The method for preparing Micro LEDs provided in experiment group one is the same as that of example one, and in the method for preparing Micro LEDs provided in experiment group one, in the step S7, CF 4 Is 145sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 4mtorr, the ICP power is 400W, and the RF power is 150W;
the method for preparing Micro LEDs provided in the second experimental group is substantially the same as that of the first embodiment, and in the step S7, CF 4 Is 145sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 3mtorr, the ICP power is 400W, and the RF power is 150W;
the method for preparing Micro LEDs provided in experiment group three is substantially the same as that of the first embodiment, and in the method for preparing Micro LEDs provided in experiment group three, in the step S7, CF 4 Is 145sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 15mtorr, the ICP power is 400W, and the RF power is 150W;
the method for preparing Micro LEDs provided in the fourth experimental group is substantially the same as that of the first embodiment, and in the method for preparing Micro LEDs provided in the third experimental group, in the step S7, CF 4 Is 145sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 4mtorr, the ICP power is 1500W, and the RF power is 700W;
the method for preparing Micro LEDs provided in experiment group five is substantially the same as that of the first embodiment, and in the method for preparing Micro LEDs provided in experiment group five, in the step S7, CF 4 Is 145sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 4mtorr, the ICP power is 400W, and the RF power is 50W;
the method for preparing Micro LEDs provided in experiment group six is substantially the same as that of the first embodiment, and in the step S7, CF 4 Is 140sccm, O 2 The flow rate of the etching solution is 20sccm, the etching pressure is 4mtorr, the ICP power is 400W, and the RF power is 150W;
the method for preparing Micro LEDs provided in experiment group seven is substantially the same as that of the first embodiment, and in the method for preparing Micro LEDs provided in experiment group seven, in the step S7, CF 4 Is 225sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 4mtorr, the ICP power is 400W, and the RF power is 150W;
the method for preparing Micro LEDs provided in experiment group eight is substantially the same as that of example one, and in the method for preparing Micro LEDs provided in experiment group eight, in the step S7, CF 4 Is introduced at a flow rate of 0sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 4mtorr, the ICP power is 400W, and the RF power is 150W;
the method for preparing Micro LEDs provided in experiment group nine is substantially the same as that of the first embodiment, and in the method for preparing Micro LEDs provided in experiment group nine, in the step S7, CF 4 Is 145sccm, O 2 The flow rate of the etching solution is 0sccm, the etching pressure is 4mtorr, the ICP power is 400W, and the RF power is 150W;
chips were fabricated according to the Micro LED fabrication methods provided in the above several experimental groups and the control group, and their roughness was tested, respectively, with test results shown in table 1:
TABLE 1
As can be seen from table 1, the Micro LED prepared by the Micro LED preparation method disclosed in the experimental group one has the smallest surface roughness, so that the chip surface is smoother than those of the Micro LEDs provided by the other experimental groups and the control group.
As shown in fig. 9, in another embodiment of the present application, there is also provided a Micro LED prepared by the Micro LED preparation method as described in embodiment one.
To sum up, CF in the present application 4 The etching rate of the gas to the inorganic protective layer is high, the etching rate to the etching photoresist layer is low, and O in the application 2 The etching rate of the gas for etching the photoresist layer is high, and the etching rate of the inorganic protective layer is low, by arrangingCF set 4 Gas and O 2 The etching rate of the inorganic protective layer and the etching photoresist layer can reach 1:1, after the photoresist is coated on the surface in a spin mode, gaps on the surface of the inorganic protective layer can be filled to obtain a flat surface, then etching is carried out, the flat inorganic protective layer can be obtained after the photoresist is completely etched, the residual thickness of the inorganic protective layer after etching is finished can be accurately controlled by controlling the thickness and the etching rate of the etching photoresist layer, and in the application, the inorganic protective layer is used as filling of the high-low fluctuation in the front-end process of a chip, the surface is flattened by combining with an etching process, and a flat metal pad layer is conveniently manufactured, so that the yield of the chip in the mass transfer and the subsequent bonding process is improved.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.

Claims (10)

1. The preparation method of the Micro LED is characterized by comprising the following steps of:
s1, providing a substrate, and sequentially growing an N-type GaN layer, a multiple quantum well layer and a P-type GaN layer on the substrate to obtain an epitaxial layer;
s2, using an ISO coating as a first mask to carry out photoresist coating and photoetching on the epitaxial layer, and then carrying out ICP etching on the epitaxial layer to form a plurality of channels on the epitaxial layer;
s3, depositing a transparent conductive layer on the epitaxial layer, sequentially performing photoresist coating and photoetching treatment on the surface of the transparent conductive layer to form a first pattern layer, putting the transparent conductive layer into etching liquid for etching treatment based on the first pattern layer, and performing annealing treatment after cleaning;
s4, photoresist coating and photoetching are carried out by using the MESA layer as a second mask, and then ICP etching is carried out on the epitaxial layer so as to form an N-type semiconductor MESA on the epitaxial layer;
s5, evaporating a metal electrode layer on the surface of the epitaxial layer;
s6, depositing an inorganic protective layer on the surfaces of the metal electrode layer and the epitaxial layer, and depositing a photoresist layer on the inorganic protective layer;
s7, using dry etching and introducing CF with preset flow ratio 4 With O 2 Etching the etching photoresist layer to a preset position so as to remove all etching photoresist layer and remove part of the inorganic protective layer;
s8, sequentially performing photoresist coating and photoetching treatment on the surface of the inorganic protective layer after the partial etching is finished to form a second image layer, and introducing CF based on the second image layer 4 And etching the inorganic protective layer to expose part of the metal electrode layer, and evaporating a bonding pad metal layer on the exposed metal electrode layer to obtain the Micro LED.
2. The Micro LED manufacturing method according to claim 1, wherein the substrate is a Si substrate, a SiC substrate, a ZnO substrate, or a sapphire substrate.
3. The method of claim 1, wherein the transparent conductive layer is used for connecting the P-type GaN layer and the metal electrode layer, the transparent conductive layer is GIO, ZITO, ITO or nano silver wire, and the resistivity of the transparent conductive layer is lower than that of the P-type GaN layer.
4. The method for manufacturing Micro LEDs according to claim 1, wherein in the step S3, the soaking time ranges from 3min to 15min, and the annealing furnace temperature ranges from 450 ℃ to 650 ℃.
5. The method for manufacturing a Micro LED according to claim 1, wherein the thickness of the metal electrode layer ranges from 1 μm to 3 μm.
6. The method for manufacturing Micro LEDs according to claim 1, wherein,the inorganic protective layer comprises a reflecting layer and a single-layer insulating layer, wherein the reflecting layer is specifically formed by SiO 2 With Ti 3 O 5 A DBR structure comprising a single insulating layer made of SiO 2 、Al 2 O 3 、Ti 3 O 5 The thickness of the reflecting layer ranges from 0.5 mu m to 2 mu m, and the thickness of the single-layer insulating layer ranges from 2 mu m to 10 mu m.
7. The method of manufacturing Micro LEDs according to claim 6, wherein in the step S7, CF 4 With O 2 The preset flow ratio of (2) is 7:1-15:1.
8. The method of manufacturing Micro LEDs according to claim 7, wherein in the step S7, CF 4 Is 145sccm, O 2 The flow rate of the etching solution is 15sccm, the etching pressure is 3-15 mtorr, the ICP power is 400-1500W, and the RF power is 50-700W.
9. The method of manufacturing Micro LEDs according to claim 1, wherein in said step S8, CF 4 The flow range of the etching solution is 70 sccm-150 sccm, the etching pressure is 3-15 mtorr, and the etching time is 10-30 min.
10. The Micro LED is characterized in that the Micro LED is prepared by the Micro LED preparation method according to any one of claims 1-9.
CN202310905128.1A 2023-07-24 2023-07-24 Micro LED preparation method and Micro LED Pending CN116885058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310905128.1A CN116885058A (en) 2023-07-24 2023-07-24 Micro LED preparation method and Micro LED

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310905128.1A CN116885058A (en) 2023-07-24 2023-07-24 Micro LED preparation method and Micro LED

Publications (1)

Publication Number Publication Date
CN116885058A true CN116885058A (en) 2023-10-13

Family

ID=88261861

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310905128.1A Pending CN116885058A (en) 2023-07-24 2023-07-24 Micro LED preparation method and Micro LED

Country Status (1)

Country Link
CN (1) CN116885058A (en)

Similar Documents

Publication Publication Date Title
CN104916527B (en) Display base plate and its manufacture method, display device
KR101681242B1 (en) Method of fabricating light emitting diode and light emitting diode manufactured thereby
CN107195747A (en) A kind of micron-scale flip LED chips and preparation method thereof
US7943942B2 (en) Semiconductor light-emitting device with double-sided passivation
WO2023284226A1 (en) Silicon-based light-emitting diode structure and preparation method therefor
CN206834196U (en) A kind of micron-scale flip LED chips
CN108231966A (en) A kind of LED chip with speculum and preparation method thereof
CN110444562A (en) A kind of display panel and display device
CN107731975B (en) Nanotube LED and manufacturing method thereof
CN106058003A (en) Method for improving the brightness of LED chip
CN109860349A (en) A kind of LED chip and its manufacturing method
JP2012529170A (en) Light emitting semiconductor device and manufacturing method
CN108766972A (en) Thin film transistor and its manufacturing method, display base plate
US9159865B2 (en) Method of forming zinc oxide prominence and depression structure and method of manufacturing solar cell using thereof
CN116885058A (en) Micro LED preparation method and Micro LED
CN116525737A (en) GaAs-based flip-chip Mini LED chip and preparation method thereof
CN107910406A (en) The LED chip and its manufacture method of membrane structure
CN115621401A (en) Micro LED packaging structure and packaging method thereof
CN111799357A (en) Preparation method of LED chip with tin bonding pad
CN109346405B (en) Preparation method of GaN-based SBD flip chip
CN109052311B (en) Method for preparing all-covered side electrode
CN219716889U (en) Inverted mini LED chip
CN215377438U (en) Micro LED packaging structure
CN112366254B (en) LED chip preparation method and LED chip thereof
CN114188455B (en) Preparation method of flip mini light-emitting diode chip

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination