CN116884984A - Image sensor and manufacturing method thereof - Google Patents

Image sensor and manufacturing method thereof Download PDF

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Publication number
CN116884984A
CN116884984A CN202311126791.8A CN202311126791A CN116884984A CN 116884984 A CN116884984 A CN 116884984A CN 202311126791 A CN202311126791 A CN 202311126791A CN 116884984 A CN116884984 A CN 116884984A
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layer
interlayer dielectric
dielectric layer
image sensor
region
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CN202311126791.8A
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CN116884984B (en
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夏小峰
张维
李岩
范春晖
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Hefei Haitu Microelectronics Co ltd
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Hefei Haitu Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the field of image sensors. At least comprises: the substrate comprises a photoelectric sensing region, an electronic storage region and an isolation well region, wherein the isolation well region is arranged at two sides of the adjacent photoelectric sensing region and the electronic storage region; the grid structure is arranged on the substrate between the photoelectric sensing area and the electronic storage area; the light guide structure is arranged on the photoelectric sensing area; the interlayer dielectric layer covers the electron storage area and the isolation well area, is higher than the light guide structure, and the side wall of part of the interlayer dielectric layer is in a step shape; the metal interconnection layer is arranged in the interlayer dielectric layer and connected with the grid structure, and part of the metal interconnection layer is arranged in a biased way towards the direction of incident light; and the isolation structure is covered on the interlayer dielectric layer and the light guide structure, and at least part of the isolation structure is trapezoid in shape. The image sensor and the manufacturing method thereof can improve the performance of the image sensor.

Description

Image sensor and manufacturing method thereof
Technical Field
The invention belongs to the field of image sensors, and particularly relates to an image sensor and a manufacturing method thereof.
Background
The complementary metal oxide image sensor (Complementary Metal Oxide Semiconductor Image Sensor, CIS) has the advantages of low power consumption, high response speed and the like, and is widely applied to devices such as digital cameras, video cameras, palm computers, camera phones and the like. The front-illuminated (Front side illumination, FSI) image sensor has high yield, reliability and yield, and is widely applied to the fields of notebook computers, digital video cameras, digital cameras and the like. However, FSI is affected by the height of Micro lenses (Micro Lens), and the optical path is long relative to the back-illuminated CIS, resulting in a decrease in the intensity of light that eventually enters the photodiode, affecting the imaging effect of the sensor. Meanwhile, in the charge domain global shutter image sensor, the uniformity of imaging is also affected by leakage and parasitic light pollution in the electronic storage area (memory node). And the incidence of light rays at the edge and the center of the image sensor array is different, and the sensitivity uniformity of pixels in different areas is poor.
Disclosure of Invention
The invention aims to provide an image sensor and a manufacturing method thereof, and the image sensor and the manufacturing method thereof can improve the sensitivity of edge pixels of the image sensor and improve the performance of the image sensor.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides an image sensor, which at least comprises:
the substrate comprises a photoelectric sensing region, an electronic storage region and an isolation well region, wherein the photoelectric sensing region and the electronic storage region are arranged in parallel, and the isolation well region is arranged at two sides adjacent to the photoelectric sensing region and the electronic storage region;
the grid structure is arranged on the substrate and between the photoelectric sensing area and the electron storage area;
the light guide structure is arranged on the photoelectric sensing area;
the interlayer dielectric layer is arranged on the substrate and covers the electron storage area and the isolation well area, the interlayer dielectric layer is higher than the light guide structure, and the side wall of part of the interlayer dielectric layer is in a step shape;
the metal interconnection layer is arranged in the interlayer dielectric layer, connected with the grid structure and arranged in a biased way in the direction of incident light; and
and the isolation structure is covered on the interlayer dielectric layer and the light guide structure, and at least part of the isolation structure is trapezoid in shape.
In an embodiment of the present invention, the image sensor includes a center pixel unit and an edge pixel unit disposed around the center pixel unit.
In an embodiment of the present invention, the interlayer dielectric layer on the edge pixel unit is provided with a step structure, and the step structure is disposed on a side of the metal interconnection layer away from the central pixel unit.
In an embodiment of the present invention, on the edge pixel unit, a portion of the isolation structure and the interlayer dielectric layer higher than the light guiding structure has a trapezoid shape.
In an embodiment of the present invention, on the central pixel unit, a portion of the isolation structure and the interlayer dielectric layer higher than the light guiding structure has a rectangular shape.
In one embodiment of the present invention, the isolation structure includes a protective layer that continuously covers the top of the light guiding structure, and the top and sidewalls of the interlayer dielectric layer.
In an embodiment of the present invention, the isolation structure includes a reflective layer, the reflective layer covers the top and the sidewalls of the interlayer dielectric layer, and the reflective layer has a triangular shape on top of the interlayer dielectric layer.
In an embodiment of the present invention, the metal interconnection layer includes at least a top metal interconnection layer, an intermediate metal interconnection layer, and a bottom metal interconnection layer, and on the edge pixel unit, the top metal interconnection layer and the intermediate metal interconnection layer are sequentially biased toward the central pixel unit direction with respect to the bottom metal layer.
In one embodiment of the invention, a metal light blocking layer is arranged on the side wall of the light guide structure.
The invention also provides a method for manufacturing the image sensor, which at least comprises the following steps:
providing a substrate, and forming a photoelectric sensing region, an electron storage region and an isolation well region in the substrate;
forming a gate structure on the substrate, the gate structure being disposed between the photo-sensing region and the electron storage region;
forming an interlayer dielectric layer on the substrate, and forming a metal interconnection layer in the interlayer dielectric layer on the electronic storage region;
etching the interlayer dielectric layer of the photoelectric sensing region to form a light guide structure;
etching the part of the interlayer dielectric layer higher than the light guide structure, and forming the side wall of the interlayer dielectric into a step shape or a plane; and
and forming an isolation structure on the interlayer dielectric layer.
In summary, the image sensor and the manufacturing method thereof provided by the invention can shorten the optical path entering the photodiode and inhibit the crosstalk of optical signals between pixels with different colors. The rear metal interconnection layer is offset along with the application of the lens angle of the terminal, so that the sensitivity of the edge pixels of the image sensor can be effectively improved, and the performance of the image sensor is improved. Meanwhile, the isolation structure between the metal interconnection layer and the light gathering unit is arranged to be a rectangular or trapezoid offset structure along with the metal interconnection layer, so that crosstalk between adjacent pixels can be prevented, the isolation structure can be connected with two sides of the light guide structure, additional light is prevented from entering the electronic storage area, and the influence of parasitic light response is reduced.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
Having more clearly described the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1a is a schematic diagram of a metal interconnect layer formed on a central pixel cell according to an embodiment.
FIG. 1b is a schematic diagram of a side edge pixel cell after forming a metal interconnect layer thereon according to one embodiment.
FIG. 1c is a schematic diagram of an embodiment of a metal interconnect layer formed on a pixel cell at the other side edge.
FIG. 2a is a schematic diagram of a metal light blocking layer formed on an interlayer dielectric layer and a light guiding trench on a central pixel cell in an embodiment.
FIG. 2b is a schematic diagram of a metal light blocking layer formed on an interlayer dielectric layer and a light guiding trench on a side edge pixel cell in an embodiment.
FIG. 2c is a schematic diagram of a metal light blocking layer formed on an interlayer dielectric layer and a light guiding trench on a pixel cell at the other side edge in an embodiment.
FIG. 3a is a schematic diagram of an etched metal light blocking layer on a center pixel unit in an embodiment.
FIG. 3b is a schematic diagram of an etched metal light blocking layer on a side edge pixel cell in an embodiment.
FIG. 3c is a schematic diagram of an etched metal light blocking layer on a pixel cell at the other side edge in one embodiment.
FIG. 4a is a schematic diagram of a light guiding material layer formed in a light guiding trench on a central pixel unit in an embodiment.
FIG. 4b is a schematic diagram of a light guiding material layer formed in a light guiding trench on a side edge pixel cell in an embodiment.
FIG. 4c is a schematic diagram of a light guiding material layer formed in a light guiding trench on a pixel unit at the other side edge in an embodiment.
FIG. 5a is a schematic diagram illustrating a first photoresist layer formed on a central pixel unit according to an embodiment.
FIG. 5b is a schematic diagram illustrating a first photoresist layer formed on a side edge pixel unit according to one embodiment.
FIG. 5c is a schematic diagram illustrating a first photoresist layer formed on a pixel unit at the other side edge in an embodiment.
FIG. 6a is a schematic diagram of an interlayer dielectric layer on a central pixel unit according to an embodiment.
FIG. 6b is a schematic diagram illustrating a first step formed on an interlayer dielectric layer on a side edge pixel unit according to an embodiment.
Fig. 6c is a schematic diagram illustrating formation of a first step on the interlayer dielectric layer on the pixel unit at the other side edge in an embodiment.
FIG. 7a is a schematic diagram illustrating a second photoresist layer formed on a central pixel unit according to an embodiment.
FIG. 7b is a schematic diagram illustrating a second photoresist layer formed on a side edge pixel unit according to an embodiment.
FIG. 7c is a schematic diagram illustrating a second photoresist layer formed on the pixel unit at the other side edge in one embodiment.
FIG. 8a is a schematic diagram of an interlayer dielectric layer on a central pixel unit in an embodiment.
FIG. 8b is a schematic diagram of forming a second step on the interlayer dielectric layer on a side edge pixel unit in an embodiment.
Fig. 8c is a schematic diagram illustrating a second step formed on the interlayer dielectric layer on the pixel unit at the other side edge in an embodiment.
FIG. 9a is a schematic diagram illustrating a third photoresist layer formed on a central pixel unit according to an embodiment.
FIG. 9b is a schematic diagram illustrating a third photoresist layer formed on a side edge pixel unit according to an embodiment.
FIG. 9c is a schematic diagram illustrating a third photoresist layer formed on the pixel unit at the other side edge in one embodiment.
FIG. 10a is a schematic diagram of an interlayer dielectric layer on a central pixel unit in an embodiment.
FIG. 10b is a schematic diagram of forming a third step on the interlayer dielectric layer on a side edge pixel unit according to an embodiment.
Fig. 10c is a schematic diagram illustrating formation of a third step on the interlayer dielectric layer on the pixel unit at the other side edge in an embodiment.
FIG. 11a is a schematic diagram of a central pixel unit with a protective layer formed on an interlayer dielectric layer and a photoconductive structure according to an embodiment.
FIG. 11b is a schematic diagram of a passivation layer formed on an interlayer dielectric layer and a light guiding structure on a side edge pixel cell according to an embodiment.
FIG. 11c is a schematic diagram illustrating a protective layer formed on an interlayer dielectric layer and a light guiding structure on a pixel cell at the other side edge in an embodiment.
FIG. 12a is a schematic diagram illustrating a reflective layer formed on a protective layer on a central pixel unit according to an embodiment.
FIG. 12b is a schematic diagram of a reflective layer formed on a passivation layer on a side edge pixel cell according to an embodiment.
FIG. 12c is a schematic diagram illustrating a reflective layer formed on the passivation layer on the pixel unit at the other side according to one embodiment.
FIG. 13a is a schematic diagram of an etched reflective layer on a center pixel cell in an embodiment.
FIG. 13b is a schematic diagram of etching a reflective layer on a side edge pixel cell in one embodiment.
FIG. 13c is a schematic diagram of etching a reflective layer on a pixel cell at the other side edge in one embodiment.
FIG. 14a is a schematic diagram of a filter layer formed on a light guiding structure on a central pixel unit in an embodiment.
FIG. 14b is a schematic diagram of a filter layer formed on a light guiding structure on a side edge pixel unit in an embodiment.
FIG. 14c is a schematic diagram of a filter layer formed on a light guiding structure on a pixel unit at the other side of the pixel unit in an embodiment.
Fig. 15a is a schematic diagram illustrating a condensing unit formed on a filter layer on a central pixel unit in an embodiment.
FIG. 15b is a schematic diagram of a light condensing unit formed on a filter layer on a side edge pixel unit in an embodiment.
Fig. 15c is a schematic diagram illustrating a condensing unit formed on the filter layer on the pixel unit at the other side edge of the embodiment.
FIG. 16a is a schematic diagram of light incident on a central pixel unit according to an embodiment.
FIG. 16b is a schematic diagram of light incident on a side edge pixel cell according to an embodiment.
FIG. 16c is a schematic diagram of light incident on a pixel unit at the other side edge in an embodiment.
Description of the reference numerals:
10. a substrate; 101. an isolation well region; 102. a photo-electric sensing region; 1021. a doped region; 1022. pinning the layer; 103. an electronic storage area; 104. a gate structure; 20. a light guide structure; 21. a light guide groove; 22. a metal light blocking layer; 23. a layer of photoconductive material; 30. an interlayer dielectric layer; 31. a first step; 32. a second step; 33. a third step; 301. a first photoresist layer; 302. a second photoresist layer; 303. a third photoresist layer; 40. a metal interconnection layer; 41. a top metal interconnect layer; 42. an intermediate metal interconnect layer; 43. a bottom metal interconnect layer; 44. a connection hole; 50. an isolation structure; 51. a protective layer; 52. a reflective layer; 60. a filter layer; 70. and a condensing unit.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 15a to 16c, in an embodiment of the invention, the image sensor includes a substrate 10, an isolation well 101, a photo-sensing region 102, an electron storage region 103, a gate structure 104, a light guiding structure 20, an interlayer dielectric layer 30, a metal interconnection layer 40, an isolation structure 50, a filter layer 60, and a light condensing unit 70. The pixel units on the image sensor are located at the central position or the edge position, and the terminal application lens visual angle field angles on the pixel units at different positions are different, so that the sensitivity of the edge pixels of the image sensor is affected. The image sensor provided by the invention can set the offset structure on the interlayer dielectric layer 30, the metal interconnection layer 40 and the isolation structure 50 according to the angle of the principal optical axis angle of the application terminal application lens above the light guide structure 20, and can set the angle of the offset structure according to the magnitude of the principal optical axis angle of the pixel unit at different positions so as to improve the sensitivity of the edge pixels of the image sensor and the performance of the image sensor, and can be widely applied to the production of the image sensor with different structures.
Referring to fig. 1a to 1c, in an embodiment of the present invention, a substrate 10 is provided first, and the substrate 10 may be any material suitable for forming a semiconductor device, for example, a semiconductor material formed of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compounds, and the like, and further includes a stacked structure formed of these semiconductor materials, or a silicon on insulator, a stacked silicon on insulator, a silicon germanium on insulator, a germanium on insulator, and the like. In the present embodiment, the substrate 10 is selected according to the specific manufacturing requirements of the image sensor, specifically, for example, a silicon wafer substrate is selected.
Referring to fig. 1a to 1c, in an embodiment of the present invention, a photo sensing region 102, an electron storage region 103 and an isolation well region 101 are formed on a substrate 10. The photo sensing region 102 and the electron storage region 103 are disposed in parallel in the substrate 10, and the isolation well region 101 is disposed between adjacent photo sensing regions 102 and electron storage regions 103 for isolating adjacent pixel units. Specifically, for example, the isolation well region 101 is formed by implanting impurity ions into the substrate 10, and in this embodiment, the impurity ions of the isolation well region 101 are P-type impurity ions such as boron (B) or gallium (Ga). After forming the isolation well region 101, a photo sensing region 102 is formed on one side of the isolation well region 101, where the photo sensing region 102 includes, for example, a doped region 1021 and a pinned layer 1022, and the pinned layer 1022 is disposed, for example, above the doped region 1021, and provides surface passivation by providing the pinned layer 1022, thereby serving to reduce dark current and white pixels. In this embodiment, the impurity ions implanted into the doped region 1021 are, for example, N-type impurity ions such As phosphorus (P) or arsenic (As), and the impurity ions implanted into the pinning layer 1022 are, for example, P-type impurity ions such As boron (B) or gallium (Ga).
Referring to fig. 1a to 1c, in an embodiment of the invention, after forming the photo-sensing region 102, impurity ions are implanted into the substrate 10 at one side of the photo-sensing region 102 between adjacent isolation well regions 101 to form an electron storage region 103, and the implanted impurity ions are, for example, N-type impurity ions of the same type as the doped region 1021, and a predetermined distance is provided between the electron storage region 103 and the photo-sensing region 102, for example. The doping concentration, width and depth of the doped region 1021, the pinning layer 1022 and the electron storage region 103 are set according to actual production conditions, for example. After forming the electron storage region 103, the gate structure 104 is formed on the substrate 10 of the electron storage region 103 and the photo-sensing region 102, and the specific forming method of the gate structure 104 is not limited in the present invention. The gate structure 104 is disposed, for example, between the photo-sensing region 102 and the electron storage region 103, and one end of the gate structure 104 is aligned, for example, with one end of the photo-sensing region 102, and the other end is partially overlapped, for example, with the electron storage region 103, for transferring photoelectrons.
Referring to fig. 1a to 1c, in an embodiment of the present invention, after forming the gate structure 104, an interlayer dielectric layer 30 is formed on the substrate 10, a metal interconnection layer 40 and a connection hole 44 are formed in the interlayer dielectric layer 30 above the electronic storage region 103, and the metal interconnection layer 40 for interconnection may be formed by depositing the interlayer dielectric layer 30, photolithography and etching the connection hole 44, depositing a barrier layer and the metal interconnection layer 40 in the connection hole 44, and etching back or chemical mechanical polishing the metal interconnection layer 40, which will not be described herein. The metal interconnect layer 40 includes, for example, at least two layers, and in this embodiment, the metal interconnect layer 40 includes, for example, 3 layers, and is, for example, a top metal interconnect layer 41, an intermediate metal interconnect layer 42, and a bottom metal interconnect layer 43, respectively. The bottom metal interconnect layer 43, the intermediate metal interconnect layer 42, and the top metal interconnect layer 41 are, for example, sequentially distant from the substrate 10, and the bottom metal interconnect layer 43 and the gate structure 104 are, for example, connected through the connection hole 44. In other embodiments, when the number of layers of the metal interconnection layer 40 is greater than 3, the metal interconnection layer 40 near the connection hole 44 is defined as a bottom metal interconnection layer 43, the metal interconnection layer 40 located at the middle of the metal layers is defined as an intermediate metal interconnection layer 42, and the metal interconnection layer 40 on top is defined as a top metal interconnection layer 41.
Referring to fig. 1a and 16c, in an embodiment of the present invention, the structures of the metal interconnection layers 40 on the pixel units at different positions are different, in this embodiment, for example, by sequentially biasing the top metal interconnection layer 41 and the middle metal interconnection layer 42 with respect to the bottom metal interconnection layer 43 toward the incident light direction, that is, biasing the metal interconnection layers 40 on the edge pixel units toward the central pixel unit direction, the biasing angle changes, for example, along with the change of the angle of view field of the terminal application lens, and the angle θ of the view field is, for example, 0 ° to 12 °, so as to improve the effective collection of the light in the area outside the photosensitive element. Specifically, in the center pixel unit, the terminal application lens angle of view field is, for example, 0 °, the top metal interconnection layer 41 and the intermediate metal interconnection layer 42 are not set to be offset, and in the edge pixel unit, the terminal application lens angle of view field is, for example, greater than 0 ° and less than 12 °, and the top metal interconnection layer 41 and the intermediate metal interconnection layer 42 are set to be offset, for example, following the terminal application lens angle of view field.
Referring to fig. 1a to 4c, in an embodiment of the present invention, after forming the metal interconnection layer 40, the interlayer dielectric layer 30 on the photo-sensing region 102 is etched, and the etching is stopped until the pad nitride layer (not shown) on the substrate 10 is exposed, so as to form the light guiding trench 21, and the width of the light guiding trench 21 is smaller than the width of the photo-sensing region 102. Then, a metal light blocking material is deposited on the bottom, the side wall and the interlayer dielectric layer 30 of the light guide groove 21, and the metal light blocking material on the side wall of the light guide groove 21 is reserved to form a metal light blocking layer 22, so that the incident light is prevented from influencing the signal of the electron storage area 103. The metal light blocking layer 22 is deposited, for example, by a radio frequency sputtering physical vapor deposition method (Radio Frequency Chemical Vapor Deposition, RFPVD) or the like, for example, a dry etching method is selected to remove the bottom of the light guide groove 21 and deposit a metal light blocking material on the interlayer dielectric layer 30, only the metal light blocking material on the side wall of the light guide groove 21 is remained, the metal light blocking layer 22 is formed, and the metal light blocking material is, for example, one or more of opaque metals or metal compound materials such as titanium, tungsten, aluminum, copper, cobalt, nickel and the like, and the deposition method and the material of the specifically deposited metal light blocking layer 22 are set according to actual production conditions. After the metal light blocking layer 22 is formed, a light guiding material layer 23 is formed in the light guiding trench 21, specifically, for example, a light guiding material such as an organic material or an inorganic material having high light transmittance is filled in the light guiding trench 21, and the light guiding material is planarized so that the light guiding material is on the same plane as the surface of the interlayer dielectric layer 30, thereby forming the light guiding structure 20.
Referring to fig. 4a to 6c, after forming the optical waveguide structure 20, a first photoresist layer 301 is formed on the interlayer dielectric layer 30, and then the first photoresist layer 301 is exposed and developed to form a patterned first photoresist layer 301. The exposed positions of the first photoresist layer 301 on the pixel cells at different positions are different, and the first photoresist layer 301 located in the central pixel cell, for example, completely covers the interlayer dielectric layer 30, i.e., the two side edges of the first photoresist layer 301 are aligned with the interface between the interlayer dielectric layer 30 and the light guiding structure 20. The first photoresist layer 301 located in the edge pixel unit, for example, covers the interlayer dielectric layer 30 on the top metal interconnection layer 41, and an end edge of the first photoresist layer 301 near the center pixel is aligned with the interface between the interlayer dielectric layer 30 and the light guiding structure 20, and an end edge of the first photoresist layer 301 away from the center pixel is located on the interlayer dielectric layer 30 between the top metal interconnection layer 41 and the middle metal interconnection layer 42. The exposed interlayer dielectric layer 30 and the light guiding structure 20 are subjected to a first etching, for example, a dry etching process or an etching method in which the dry etching process and the wet etching process are combined, using the first photoresist layer 301 as a mask. In this embodiment, for example, the interlayer dielectric layer 30 and the light guiding structure 20 are etched by a dry etching method, the surface formed by etching the interlayer dielectric layer 30 is located between the surface of the top metal interconnection layer 41 and the surface of the intermediate metal interconnection layer 42, for example, the etching depth of the light guiding structure 20 is etched with the etching depth of the interlayer dielectric layer 30, for example, and the light guiding structure 20 is etched to remove the metal light blocking layer 22 and the light guiding material at the same time, for example. After the first etching, the intermediate metal interconnection layer 42 on the edge pixel unit extends out of the top metal interconnection layer 41 to form a first step 31, and the first step 31 is disposed on the interlayer dielectric layer 30 on the side of the metal interconnection layer 40 away from the central pixel.
Referring to fig. 6a to 10c, in an embodiment of the invention, the first photoresist layer 301 is removed, and a second photoresist layer 302 is formed on the interlayer dielectric layer 30. In this embodiment, the second photoresist layer 302 on the central pixel unit covers the same position as the first photoresist layer 301, for example, completely covers the inter-layer dielectric layer 30. The second photoresist layer 302 located on the edge pixel cell, for example, completely covers the top metal interconnect layer 41 and the first step 31, i.e., one end edge of the second photoresist layer 302 near the center pixel is aligned with the interface of the interlayer dielectric layer 30 and the light guiding structure 20, and the other end edge is aligned with the edge of the first step 31. The exposed interlayer dielectric layer 30 and the light guiding structure 20 are subjected to a second etch using the second photoresist layer 302 as a mask. In the present embodiment, the method and depth of the second etching are the same as those of the first etching, for example, and the second step 32 is formed at the end of the first step 31 remote from the center pixel. The second photoresist layer 302 is removed, a third photoresist layer 303 is formed on the interlayer dielectric layer 30, the third photoresist layer 303 located in the central pixel unit, for example, completely covers the interlayer dielectric layer 30, the second photoresist layer 302 located in the edge pixel unit, for example, completely covers the top metal interconnection layer 41, the first step 31 and the second step 32, and a third step 33 is formed at an end of the second step 32 away from the interconnection layer of the intermediate reflection layer 52 through third etching.
Referring to fig. 10a to 10c, in an embodiment of the present invention, the metal interconnection layer 40 on the edge pixel unit is biased and follows the metal interconnection layer 40, for example, a step structure is disposed on the interlayer dielectric layer 30. The number of the step structures is not limited, and is at least 1, for example, 2 to 8, for example, and the step structures are disposed on the metal interconnection layer 40 disposed in a biased manner. In the present embodiment, the number of steps is, for example, 3, and the number of steps is, for example, one more than the number of metal interconnection layers 40 arranged in a biased manner, so as to avoid that the difference between the angle of the bias and the angle of field of view of the terminal application is too large, the light condensation effect is affected, and the subsequent inability to form the isolation structure 50 with a special shape on the interlayer dielectric layer 30 is avoided. The step structures are oriented in the same direction as the bias direction of the metal interconnect layer 40, for example, and extend away from the substrate 10 from the edge pixels toward the center pixels, for example. Specifically, in the present embodiment, the metal interconnect layer 40 disposed offset on the edge pixel unit is the top metal interconnect layer 41 and the middle metal interconnect layer 42, and a step structure including the first step 31, the second step 32, and the third step 33 is formed on the interlayer dielectric layer 30 following the top metal interconnect layer 41 and the middle metal interconnect layer 42. The directions of the first step 31 to the third step 33 are, for example, directions extending from the edge pixels to the center pixels, i.e., the inclined planes where the step structures are located are identical to the directions of the incident light. The etching depth of the light guiding structure 20 is the same as the etching depth of the interlayer dielectric layer 30 while the step structure is formed on the interlayer dielectric layer 30. When the step structure includes a plurality of steps, the width and height of each step are set, for example, according to the offset distance between the metal interconnect layers 40 of each layer, and in the present embodiment, the depths of the first step 31, the second step 32, and the third step 33 are, for example, equal, and the widths are, for example, equal. By providing the offset arrangement of the metal interconnection layer 40 and the step structure of the interlayer dielectric layer 30 on the edge pixel unit, the acceptance of the edge pixel to incident light is increased, and the sensitivity of the image sensor edge pixel is improved.
Referring to fig. 10a to 11c, in an embodiment of the invention, after removing the third photoresist layer 303, an isolation structure 50 is formed on the interlayer dielectric layer 30 and the light guiding structure 20, and the isolation structure 50 includes, for example, a protection layer 51 and a reflective layer 52. The protective layer 51 is for example provided on top of the interlayer dielectric layer 30, on the sidewalls, and on top of the light guiding structure 20 and deposited on the step structure filling the step structure. After the protective layer 51 is formed, the interlayer dielectric layer 30 above the adjacent light guiding structure 20 on the central pixel unit has a rectangular shape, for example, and the interlayer dielectric layer 30 above the adjacent light guiding structure 20 on the edge pixel unit has a trapezoidal shape, for example. The material and the forming method of the protection layer 51 are not limited, in this embodiment, the material of the protection layer 51 is an insulating material such as silicon oxide, the forming method of the protection layer 51 is one of chemical vapor deposition, and the thickness of the protection layer 51 is 100 a to 300 a, for example. The sensitivity of the edge pixel cell is further improved by depositing the protective layer 51, and the protective layer 51 can serve as an etch stop layer for the subsequent reflective layer 52, protecting the interlayer dielectric layer 30 and the photoconductive structure 20, and improving the image sensor performance.
Referring to fig. 11a to 13c, in an embodiment of the invention, after forming the protection layer 51, a reflective layer 52 is formed on the protection layer 51, the reflective layer 52 covers, for example, two side walls and a top of the inter-layer dielectric layer 30, the thickness of the reflective layer 52 is, for example, 200 a to 3000 a, and a special shape is formed on the top of the inter-layer dielectric layer 30. In this embodiment, the reflective layer 52 on top of the interlayer dielectric layer 30 is triangular, for example, which increases the reflective area for incident light, enhances the effective collection of incident light, and optimizes the pixel sensitivity at each individual pixel edge. Specifically, a metal material, such as silver, aluminum, tungsten, or other high-reflectivity metal material, is deposited on the protective layer 51 to improve the reflection efficiency of incident light. And then etching to remove the metal material on the photoconductive structure 20, thinning the metal material on the interlayer dielectric layer 30, and etching the metal material on the interlayer dielectric layer 30 to form a special shape, thereby forming the reflective layer 52 on the protective layer 51. By providing the isolation structure 50, noise generation is effectively reduced, while occurrence of crosstalk between pixels is further prevented.
Referring to fig. 13a to 16c, in an embodiment of the invention, after the isolation structures 50 are formed, a filter layer 60 is formed between adjacent isolation structures 50, the filter layer 60 is disposed, for example, above the light guiding structure 20, and a surface of the filter layer 60 is, for example, higher than a surface of the interlayer dielectric layer 30 and lower than a highest surface of the reflective layer 52. In the present embodiment, the material of the filter layer 60 is, for example, a color filter layer material, for example, having red, blue, and green, and the filter layers 60 of the respective colors are arranged in, for example, a Bayer (Bayer) array, or in other arrangement methods, for example. By disposing the optical filter layer 60 on the optical guide structure 20, the optical filter layer 60 and the optical guide structure 20 form an incident channel for incident light, and the color optical filter film in the optical filter layer 60 is combined with the light guide material in the optical guide structure 20, so that the optical path of light is shortened and crosstalk of optical signals between pixels of different colors is suppressed on the basis of ensuring light transmission. After the filter layer 60 is formed, the condensing unit 70 is formed on the filter layer 60, for example, by a microlens process, to obtain an image sensor. The condensing units 70 are, for example, covered on the filter layer 60 and the isolation structure 50, and edges of the condensing units 70 are aligned with the highest positions of the reflective layers 52 on adjacent sides, reducing the loss of edge incident light.
In summary, the present invention provides an image sensor and a method for manufacturing the same, in which an offset structure is set by a top metal interconnection layer and an intermediate metal interconnection layer following a view angle field angle of a terminal application lens, an interlayer dielectric layer following a metal interconnection layer is set to have a step structure, and an isolation structure disposed on the interlayer dielectric layer is set to have a special triangle structure, so that the sensitivity of an edge pixel of the image sensor is effectively improved, and meanwhile, additional light is prevented from entering an electronic storage area, and the influence of parasitic light response is reduced. By arranging the filter layer on the light guide structure, the optical path of light entering the photodiode is effectively shortened, crosstalk of optical signals between pixels with different colors is restrained, and the performance of the image sensor is improved.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (10)

1. An image sensor, comprising at least:
the substrate comprises a photoelectric sensing region, an electronic storage region and an isolation well region, wherein the photoelectric sensing region and the electronic storage region are arranged in parallel, and the isolation well region is arranged at two sides adjacent to the photoelectric sensing region and the electronic storage region;
the grid structure is arranged on the substrate and between the photoelectric sensing area and the electron storage area;
the light guide structure is arranged on the photoelectric sensing area;
the interlayer dielectric layer is arranged on the substrate and covers the electron storage area and the isolation well area, the interlayer dielectric layer is higher than the light guide structure, and the side wall of part of the interlayer dielectric layer is in a step shape;
the metal interconnection layer is arranged in the interlayer dielectric layer, connected with the grid structure and arranged in a biased way in the direction of incident light; and
and the isolation structure is covered on the interlayer dielectric layer and the light guide structure, and at least part of the isolation structure is trapezoid in shape.
2. An image sensor according to claim 1, wherein the image sensor comprises a central pixel unit and edge pixel units, the edge pixel units being arranged around the central pixel unit.
3. An image sensor according to claim 2, wherein the interlayer dielectric layer on the edge pixel cell is provided with a step structure, the step structure being provided on a side of the metal interconnect layer remote from the central pixel cell.
4. An image sensor according to claim 2, wherein on the edge pixel cell, the isolation structure and the portion of the interlayer dielectric layer above the light guiding structure are trapezoidal in shape.
5. An image sensor according to claim 2, wherein on the central pixel element, the isolation structure and the portion of the interlayer dielectric layer above the light guiding structure are rectangular in shape.
6. An image sensor as in claim 1, wherein said isolation structure comprises a protective layer that continuously covers the top of said light guiding structure, and the top and sidewalls of said interlayer dielectric layer.
7. The image sensor of claim 1 wherein the isolation structure comprises a reflective layer overlying the top and sidewalls of the interlayer dielectric layer, and wherein the reflective layer has a triangular shape on top of the interlayer dielectric.
8. The image sensor of claim 2, wherein the metal interconnect layer comprises at least a top metal interconnect layer, an intermediate metal interconnect layer, and a bottom metal interconnect layer, the top metal interconnect layer and the intermediate metal interconnect layer being sequentially offset relative to the bottom metal layer toward the center pixel cell on the edge pixel cell.
9. An image sensor as claimed in claim 1, characterized in that a metallic light-blocking layer is provided on the side walls of the light-guiding structure.
10. A method for manufacturing an image sensor, comprising at least the steps of:
providing a substrate, and forming a photoelectric sensing region, an electron storage region and an isolation well region in the substrate;
forming a gate structure on the substrate, the gate structure being disposed between the photo-sensing region and the electron storage region;
forming an interlayer dielectric layer on the substrate, and forming a metal interconnection layer in the interlayer dielectric layer on the electronic storage region;
etching the interlayer dielectric layer of the photoelectric sensing region to form a light guide structure;
etching the part of the interlayer dielectric layer higher than the light guide structure, and forming the side wall of the interlayer dielectric into a step shape or a plane; and
and forming an isolation structure on the interlayer dielectric layer.
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