CN116387335A - Image sensor and manufacturing method thereof - Google Patents

Image sensor and manufacturing method thereof Download PDF

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Publication number
CN116387335A
CN116387335A CN202310483224.1A CN202310483224A CN116387335A CN 116387335 A CN116387335 A CN 116387335A CN 202310483224 A CN202310483224 A CN 202310483224A CN 116387335 A CN116387335 A CN 116387335A
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light
image sensor
transmitting
pixel array
dielectric layer
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张维
范春晖
李岩
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Hefei Haitu Microelectronics Co ltd
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Hefei Haitu Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B3/00—Simple or compound lenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The invention provides an image sensor and a method for manufacturing the same, wherein the image sensor comprises: the pixel array structure comprises a plurality of photoelectric reaction areas and a plurality of storage areas, and the photoelectric reaction areas are adjacent to the storage areas; the dielectric layer is arranged on the pixel array structure; the light-transmitting structure penetrates through the dielectric layer and is connected with the photoelectric reaction area, and the side wall of the light-transmitting structure, which is close to the center of the pixel array structure, is a slope structure; the micro lens is arranged on the light-transmitting structure, covers the photoelectric reaction area and deflects towards the inclined direction of the slope structure; and a plurality of metal wirings disposed in the dielectric layer, the metal wirings being offset in a direction in which the slope structure is inclined. The invention provides an image sensor and a manufacturing method thereof, which can reduce the parasitic light response of the outer ring of a pixel array in the image sensor.

Description

Image sensor and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to an image sensor and a method for manufacturing the same.
Background
Among the image sensors, an electronic shutter image sensor electronically controls the exposure time of the image sensor, and has high shutter speed and no flare phenomenon and shutter sound. In a globally exposed electronic shutter pattern sensor, the parasitic photoresponse (Parasitic Light Sensitivity, PLS) of the charge storage node is a very important indicator for the global exposure of the charge domain. Wherein the parasitic light response is a stray light response and a photodiode response received by the charge storage node in the absence of a signal.
Since the image sensor lens has a main light axis Angle (CRA), the incident light Angle is different at different positions of the pixel array, and the outer ring parasitic light response of the image sensor pixel array is difficult to be reduced.
Disclosure of Invention
The invention aims to provide an image sensor and a manufacturing method thereof, which can reduce the parasitic light response of the outer ring of a pixel array in the image sensor.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides an image sensor, comprising:
the pixel array structure comprises a plurality of photoelectric reaction areas and a plurality of storage areas, wherein the photoelectric reaction areas are adjacent to the storage areas;
the dielectric layer is arranged on the pixel array structure;
the light-transmitting structure penetrates through the dielectric layer and is connected with the photoelectric reaction area, and the side wall, close to the center of the pixel array structure, of the light-transmitting structure is of a slope structure;
the micro lens is arranged on the light-transmitting structure, covers the photoelectric reaction area and deflects towards the direction of inclining the slope structure; and
and the metal wiring layers are arranged in the dielectric layers and are offset towards the direction of inclination of the slope structure.
In an embodiment of the present invention, a main offset distance is provided between a central axis of the microlens and a symmetry plane of the photoelectric reaction region, and a sub offset distance is provided between the metal wiring and a central axis of the storage region, wherein the sub offset distance is 1/3-19/20 of the main offset distance.
In one embodiment of the present invention, in the plurality of layers of the metal wirings, the metal wiring on the top layer is offset in a direction in which the slope structure is inclined.
In one embodiment of the present invention, in the plurality of layers of the metal wirings, the metal wiring on the top layer and the metal wiring on the sub-top layer are offset in a direction inclined toward the slope structure.
In an embodiment of the present invention, a gate is disposed on the pixel array structure, the gate is located between the photo-electric reaction region and the storage region, and the gate covers the storage region and a part of the photo-electric reaction region.
In an embodiment of the present invention, an orthographic projection of the metal wiring on the pixel array structure is located in the storage region and on the gate structure.
In one embodiment of the present invention, the image sensor includes a color filter layer disposed on the light-transmitting structure and a planarization layer disposed between the color filter layer and the microlens.
In an embodiment of the present invention, a refractive index of the light-transmitting structure is greater than a refractive index of the dielectric layer.
The invention provides a manufacturing method of an image sensor, which comprises the following steps:
providing a pixel array structure, wherein the pixel array comprises a plurality of photoelectric reaction areas and a plurality of storage areas, and the photoelectric reaction areas are adjacent to the storage areas;
forming a dielectric layer on the pixel array structure;
forming a plurality of layers of metal wiring in the dielectric layer;
forming a light-transmitting structure on the photoelectric reaction region, wherein the light-transmitting structure penetrates through the dielectric layer and is connected with the photoelectric reaction region, the side wall, close to the center of the pixel array structure, of the light-transmitting structure is a slope structure, and the metal wiring is offset towards the direction of inclination of the slope structure; and
and forming a micro lens on the light-transmitting structure, wherein the micro lens covers the photoelectric reaction area, and the micro lens is offset towards the inclined direction of the slope structure.
In an embodiment of the present invention, the step of forming the light-transmitting structure includes:
etching the dielectric layer to form a light-transmitting groove;
etching the groove wall of the light-transmitting groove for multiple times to form a step structure;
burying the step structure, and forming the slope structure in the light-transmitting groove; and
and filling the light-transmitting groove to form the light-transmitting structure.
In an embodiment of the present invention, the step of burying the step structure includes:
forming a buried layer in the light-transmitting groove and on the dielectric layer; and
and etching the buried layer to expose the photoelectric reaction area.
As described above, the present invention provides an image sensor and a method of manufacturing the same, which can improve the response intensity of a photo-reaction region in the image sensor and reduce the parasitic photo-response of a charge storage node. According to the image sensor and the manufacturing method thereof, the receiving quantity of the pixel units at different positions in the pixel array to the incident light can be improved, and the occurrence of outer ring parasitic light response of the pixel array of the image sensor is avoided, so that the accuracy of optical signal processing of the image sensor is improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view of a principal ray axis angle according to an embodiment of the present invention.
FIG. 2 is a schematic view of the photo-electric reaction area and the storage area and the structure according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of forming a first metal wiring according to an embodiment of the invention.
FIG. 4 is a schematic diagram of a metal interconnect structure according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a light-transmitting trench in an embodiment of the invention.
Fig. 6 is a schematic structural diagram of a light-transmitting trench in another embodiment of the present invention.
FIG. 7 is a schematic diagram of a distribution of etched walls of a dielectric layer according to an embodiment of the present invention.
Fig. 8 is a schematic view illustrating formation of a first step structure according to an embodiment of the present invention.
FIG. 9 is a schematic view of forming a second step structure according to an embodiment of the present invention.
Fig. 10 is a schematic view illustrating formation of a first step structure according to another embodiment of the present invention.
FIG. 11 is a schematic view of forming a second step structure according to an embodiment of the present invention.
Fig. 12 is a schematic structural diagram of a buried layer according to an embodiment of the present invention.
Fig. 13 is a schematic view of a second slope structure according to an embodiment of the invention.
Fig. 14 is a schematic view of a light-transmitting structure according to an embodiment of the invention.
Fig. 15 is a schematic structural diagram of an image sensor according to an embodiment of the invention.
FIG. 16 is a schematic top view of a microlens and a light transmissive structure according to an embodiment of the present invention.
FIG. 17 is a schematic diagram of an image sensor with a principal ray axis angle of 0 according to an embodiment of the present invention.
Fig. 18 is a circuit diagram of a charge domain pixel in accordance with an embodiment of the present invention.
In the figure: 10. a pixel array; 11. a pixel unit; 20. a lens; 100. a substrate; 101. a photoelectric reaction region; 102. a storage area; 103. a gate; 200. a metal interconnect structure; 201. a dielectric layer; 202. a metal wiring; 2021. a first metal wiring; 2022. a second metal wiring; 2023. a third metal wiring; 300. a light-transmitting groove; 400. a step structure; 401a, a first photoresist layer; 401b, a second photoresist layer; 402a, a third photoresist layer; 402b, a fourth photoresist layer; 500. a buried layer; 600. a light-transmitting structure; 601. a light-transmitting layer; 700. a functional layer; 800. and a microlens.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Electronic shutter image sensors are classified into rolling shutter type and global exposure type image sensors. In a rolling shutter electronic image sensor, the exposure time of each line in the pixel array 10 is different, and thus there is a smear when capturing a high-speed object. The invention provides a global exposure type electronic shutter image sensor, which completes exposure of each row of a pixel array 10 at the same time, thereby solving the problem of smear when shooting a high-speed object. The global exposure type image sensor can be widely applied to vehicle-mounted cameras, industrial cameras, road monitoring cameras and high-speed cameras, and has a wide application range. In the present embodiment, the image sensor may be a CMOS image sensor. Referring to fig. 1, the CMOS image sensor includes a pixel array 10 and a lens assembly 20. Wherein the pixel array 10 comprises a plurality of pixel units 11. The incident light passes through the lens assembly 20 and is focused onto the pixel unit 11. Where the principal ray axis angle is the maximum angle of the light focused onto the pixel cell 11, as shown by α in fig. 1. As shown in fig. 1, the incident light angles of different pixel units 11 are different. The principal ray axis angle beta of the lens assembly 20 is shown in fig. 1. According to the image sensor and the manufacturing method thereof provided by the invention, errors caused by different angles of incident light can be eliminated.
Referring to fig. 2, the present invention provides a method for manufacturing an image sensor, which comprises providing a substrate 100, and implanting dopant ions into the substrate 100 to form a photo-reaction region 101 and a charge storage region 102. The substrate 100 is, for example, a silicon substrate forming a semiconductor structure. The substrate 100 may include a base material, such as silicon (Si), silicon carbide (SiC), sapphire (Al), and a silicon layer disposed over the base material 2 O 3 ) Gallium arsenide (GaAs), lithium aluminate (LiAlO) 2 ) The semiconductor substrate material, and a silicon layer formed over the substrate. The invention is not limited to the material and thickness of the substrate 100. In this embodiment, the substrate 100 may be implanted with, for example, a P-type dopant such as boron ions to form a P-type semiconductor. And then implanting N-type dopants, such as phosphorus ions, into the substrate 100 to form a plurality of doped regions. In the present embodiment, a plurality of photoelectric reaction regions 101 and a plurality of charge reaction regions 102 are provided in the substrate 100, and the photoelectric reaction regions 101 and the charge reaction regions 102 are spaced apart. Wherein the ion doping concentrations of the photo-electric reaction region 101 and the charge reaction region 102 are different. The specific ion concentration of the photoelectric reaction region 101 and the charge reaction region 102 is not limited in the present invention. The order of formation of the photo-electric reaction region 101 and the plurality of charge reaction regions 102 is not limited by the present invention. The ion implantation depths of the photoelectric reaction region 101 and the charge reaction region 102 may be different, and the present invention is not limited to the specific ion implantation depths of the photoelectric reaction region 101 and the charge reaction region 102.
Referring to fig. 2 to 4, in an embodiment of the present invention, a gate 103 is formed on a substrate 100, and a metal interconnection structure 200 is formed on the substrate 100. Wherein a polysilicon layer is formed on the substrate 100 by chemical vapor deposition (Chemical Vapor Deposition, CVD), and the polysilicon layer is etched to form the gate electrode 103. In this embodiment, the gate 103 may cover a part of the charge storage region 102 or may cover the charge storage region 102 entirely. And, the gate electrode 103 covers a portion of the photo reaction region 101. Next, silicon oxide or tetraethyl silicate (Tetraethyl orthosilicate, TEOS) is deposited on the substrate 100 by chemical vapor deposition or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) or the like to form the dielectric layer 201. Next, the dielectric layer 201 is etched, a wiring trench is formed on the dielectric layer 201, and the metal wiring 202 is formed by filling the wiring trench. In this embodiment, the metal wiring 202 may be a metal such as copper or aluminum. The metal interconnection structure 200 includes a plurality of metal interconnection layers, and the metal interconnection layers include a dielectric layer 201 and a metal wiring 202. The present invention is not limited to the number of metal interconnect layers, and in this embodiment, the technical features of the present invention are described in terms of, for example, 3 metal interconnect layers. As shown in fig. 4, the metal interconnect structure 200 includes a first metal wiring 2021, a second metal wiring 2022, and a third metal wiring 2023.
Referring to fig. 4, in one embodiment of the present invention, the orthographic projection of the metal wiring 202 on the substrate 100 is located in the charge storage region 102. Wherein the metal wiring 202 has a symmetrical metal wiring structure as shown in fig. 4. In each metal wiring 202, the metal wiring structure corresponding to the charge storage region 102 is a symmetrical structure. The charge storage region 102 has a pattern central axis a, and the first metal wiring 2021 is symmetrical about the pattern central axis a. A first offset distance d is provided between the symmetry axis b of the second metal wiring 2022 and the central axis a of the pattern 1 . A second offset distance d is provided between the symmetry axis c of the third metal wiring 2023 and the central axis a of the pattern 2 . The present invention is not limited to the offset direction of the second metal wiring 2022 and the third metal wiring 2023. In the present invention, the third metal wiring 2023 is a metal top layer, and the second metal wiring is a metal sub-top layer. In other embodiments of the invention, the metal sub-top layer has a first slave offset distance d when the number of metal interconnect layers changes 1 The metal top layer has a second offset distance d 2 。
Referring to fig. 5 to 7, in an embodiment of the invention, the dielectric layer 201 is etched to form a transparent trench 300. Wherein the light-transmitting trench 300 is connected to the photo-electric reaction area 101. In this embodiment, a portion of the dielectric layer 201 is etched by a plasma gas or an etching solution and etched to the surface of the substrate 100 to form the light guide trench 300 as shown in fig. 5. In another embodiment of the present invention, a portion of the dielectric layer 201 is etched away, and a portion of the dielectric layer 201 covering the photo-electric reaction region 201 remains, so as to form the light guide trench 300 as shown in fig. 6. The invention does notDefining the groove depth of the light guide groove 300. Wherein a predetermined distance d is provided between the wall of the light guiding trench 300 and the first metal wiring 2021 3 . The reserved distance is greater than, for example, 0.1 μm, thereby allowing for a process margin for subsequent processes. When the light-transmitting trench 300 is formed, the gate electrode 200 may be partially exposed in the light-transmitting trench 300, or the gate electrode 200 may be completely covered in the dielectric layer 201, which is not limited in the present invention. After the metal interconnection layer is divided by the light-transmitting trench 300, the metal interconnection layers are distributed in a linear array.
Referring to fig. 5 to 10, in an embodiment of the invention, sidewalls of the transparent trench 300 are etched to form a plurality of step structures 400. Wherein the sidewall of the light-transmitting trench 300 near the center point C of the pixel array 10 is etched. Specifically, as shown in fig. 7, taking the pixel unit 11 at four corners of the pixel array 10 as an example, in the pixel unit 11, four side walls of the light-transmitting structure 600 are wall surfaces e respectively 1 Wall e 2 Wall e 3 And wall surface e 4 . Wherein the wall surface e 1 And wall surface e 2 Near the center point C of the pixel array 10, thus facing the wall e during the etching step 1 And wall surface e 2 Etching is performed to form the step structure 400. Wall e 3 And wall surface e 4 Away from the center point C of the pixel array 10 and thus remain in a vertical plane during the etching step. It should be noted that during the actual etching process, the wall surface e is affected by process errors and parameters 3 And wall surface e 4 May not be strictly vertical planes. Wherein the center point C of the pixel array 10 is the center of the pattern of the entire pixel array 10.
Referring to fig. 5 and fig. 7 to fig. 9, in the step of forming the step structure 400, a first photoresist layer 401a is first formed on the wall of the light-transmitting trench 300 and on a portion of the dielectric layer 201. In this embodiment, the first photoresist layer 401a covers a portion of the dielectric layer 201, the bottom wall and one side wall of the light-transmitting trench 300. Wherein, the first photoresist layer 401a covers the groove wall of the light-transmitting groove 300 far from the center C of the pixel array 10. As shown in fig. 7 and 8, the first photoresist layer 401a covers the wall surface e 3 And wall surface e 4 And (3) upper part. In the present embodiment, the firstA photoresist layer 401a covers a portion of the first dielectric layer 201, exposing the area where the step structure 400 is to be formed, as shown in fig. 8. Then, the exposed sidewall of the transparent trench 300 is etched by plasma gas or etching solution to form the first step structure 400. Next, the first photoresist layer 401a is removed, and a second photoresist layer 401b is formed on the bottom wall of the light-transmitting trench 300, on one side wall of the light-transmitting trench 300, on the step structure 400, and on a portion of the dielectric layer 201. Wherein, the second photoresist layer 401a covers the sidewall of the light-transmitting trench 300 away from the center point C of the pixel array 10. Wherein the second photoresist layer 401a covers a portion of the first dielectric layer 201, exposing the area where the second step structure 400 is to be formed. Then, the exposed sidewall of the transparent trench 300 is etched by plasma gas or etching solution to form a second step structure 400. Similarly, a plurality of step structures 400 may be formed on the sidewalls of the light-transmitting trench 300 near the center C of the pixel array 10 by adjusting the coverage area of the photoresist. In the present embodiment, the width of the step structure 400 is, for example, 0.01 μm to 0.3 μm.
Referring to fig. 6 and 7, and fig. 10 and 11, in another embodiment of the present invention, in the step of forming the step structure 400, a third photoresist layer 402a is first formed on the wall of the light-transmitting trench 300 and on a portion of the dielectric layer 201. In this embodiment, the third photoresist layer 402a covers the dielectric layer 201 and one side wall of the light-transmitting trench 300. Specifically, the third photoresist layer 402a covers the sidewalls of the light-transmitting trench 300 away from the center C near the pixel array 10. Wherein, the third photoresist layer 402a covering the wall of the transparent trench 300 is connected to the bottom wall of the transparent trench 300. Then, the exposed sidewall of the transparent trench 300 is etched by plasma gas or etching solution to form the first step structure 400. After the first step structure 400 is formed, the light-transmitting trench 300 extends to the surface of the photo-electric reaction region 101, and the light-transmitting trench 300 is connected with the photo-electric reaction region 101. Then, the third photoresist layer 402a is removed, and a fourth photoresist layer 402b is formed on the dielectric layer 201, on the bottom wall of the transparent trench 300, on a side wall of the transparent trench 300, and on a part of the step structure 400. The fourth photoresist layer 402b covers a portion of the step surface of the step structure 400, exposing a region where the next step structure 400 is to be formed. Then, the exposed sidewall of the transparent trench 300 is etched by plasma gas or etching solution to form a second step structure 400. Similarly, a plurality of step structures 400 may be formed on the sidewalls of the light-transmitting trench 300 near the center C of the pixel array 10 by adjusting the coverage area of the photoresist. In the present embodiment, the width of the step structure 400 is, for example, 0.01 μm to 0.3 μm.
Referring to fig. 9, 11 and 12, in an embodiment of the present invention, after forming the plurality of step structures 400, a buried layer 500 is formed on the dielectric layer 201 and in the transparent trench 300. In this embodiment, the buried layer 500 is formed by depositing silicon oxide on the dielectric layer 201 and within the transparent trench 300 by chemical vapor deposition. Wherein the buried layer 500 and the dielectric layer 201 may be of the same material, such as silicon oxide. And the thickness of the buried layer 500 is greater than the maximum step height of the step structure 400. In this embodiment, the buried layer 500 covers the dielectric layer 201 and the walls of the light-transmitting trench 300, and the step structure 400. In this embodiment, the step structure 400 is filled with silicon oxide and planarized, and the silicon oxide is continuously deposited, forming a first slope structure 501 as shown in fig. 12. The present invention does not limit the number of step structures 400. And in the present invention, the gradient of the first slope structure 501 may be adjusted according to the number and width of the step structures 400. Specifically, in the case where the number of the step structures 400 is uniform, the larger the width of the step structure 400, the larger the gradient of the first slope structure 501. In the case where the step structures 400 are uniform in width, the larger the number of step structures 400, the larger the gradient of the first slope structure 501.
Referring to fig. 12 and 13, in an embodiment of the present invention, a portion of the buried layer 500 and a portion of the dielectric layer 201 are etched to form a second slope structure 502. In this embodiment, a portion of the buried layer 500 and a portion of the dielectric layer 201 are removed by a plasma gas or an etching solution, so that the surface of the photo-electric reaction region 101 and the surface of the metal top layer are exposed. In this embodiment, a part of the buried layer 500 and a part of the dielectric layer 201 are removed, and the surface of the third metal wiring 2023 is exposed. Wherein the first ramp structure 501 is etched to form a second ramp structure 502. In this embodiment, the second ramp structure 502 has a slope greater than the first ramp structure 501. The buried layer 502 and the dielectric layer 201 are made of the same material, and for convenience of illustrating the shape of the first slope structure 501, the buried layer 502 and the dielectric layer 201 are combined and shown as shown in fig. 12. In this embodiment, after the second ramp structure 502 is formed, the dielectric layer 201 covers the gate 200. In other embodiments of the present invention, after the second ramp structure 502 is formed, the dielectric layer 201 may cover a portion of the gate 200, and another portion of the gate 200 may be exposed in the light-transmitting trench 300.
Referring to fig. 13 and 14, in an embodiment of the present invention, the light-transmitting trench 300 is filled to form a light-transmitting structure 600. In this embodiment, the light transmissive structure 600 is formed by depositing a high refractive index material, such as silicon nitride, in the light transmissive trench 300 by chemical vapor deposition. In the step of forming the light-transmitting structure 600, after the light-transmitting trench 300 is filled, a high refractive index material may be deposited continuously, so that the high refractive index material covers the dielectric layer 201 and the metal top layer, and a light-transmitting layer 601 is formed. The thickness of the light-transmitting layer 601 is not limited in the present invention. Wherein the refractive index difference between the light transmitting structure 600 and the dielectric layer 201 is large, and when light is incident at the principal optical axis angle, the light is totally reflected when contacting the slope surface of the second slope structure 502. While another portion of the light directly incident against the storage region 102 is blocked by the metal wiring. Therefore, light does not reach the storage area 102, and redundant signal quantity of the storage area 102 is avoided, so that the signal accuracy of the image sensor is improved.
Referring to fig. 14 to 16, in an embodiment of the present invention, after forming a light-transmitting structure 600 and a light-transmitting layer 601, a functional layer 700 is formed on the light-transmitting layer 601, and a microlens 800 is disposed on the functional layer 700. In this embodiment, the functional layer 700 includes a Color Filter (CF) and a flat layer. The color filter layer is disposed on the light-transmitting layer 601, and a dielectric material may be disposed between adjacent color filters to balance and stabilize the placement of the color filters. The flat layer is arranged on the color filter layer. Wherein the planarization layer may be polyimide to stabilize the placement of the microlens 800. The micro-lens 800 may be used to concentrate light so that the incident light can be concentrated through the light transmissive structure 600 to reach the photo-electric reaction area 101. In this embodiment, the incident light reaches the microlens 800 and is refracted. Wherein when the incident light is incident at the principal ray axis angle β, the incident light is totally reflected when it contacts the slope surface of the second slope surface structure 502, thereby returning to the light transmitting structure 600 and reaching the photo-electric reaction area 101.
Referring to fig. 7 and 14-16, in an embodiment of the present invention, a lateral main offset distance x and a longitudinal main offset distance y are provided between a central axis of the micro lens 800 and a symmetry axis of the photo-reactive region 101. In the present embodiment, as shown in fig. 16, in the pixel array 10, the first linear arrangement direction of the pixel array 10 is taken as the X axis, and the second linear arrangement direction of the pixel array 10 is taken as the Y axis, wherein the first linear arrangement direction and the second linear arrangement direction are perpendicular to each other. Comparing the positions of the central axes of the patterns of the microlens 800 and the photoreaction area 101, the microlens 800 is offset with respect to the photoreaction area 101 by a lateral principal offset distance x and a longitudinal principal offset distance y, as shown in fig. 16. The offset microlens 800 can accommodate the incidence of light at a particular angle, and the microlens 800 can translate toward a position away from the center of the pixel array 10. The metal top layer and the metal sub-top layer may be offset according to the offset amount of the microlens 800, or may be offset only with respect to the metal top layer. Wherein the offset direction of the metal top layer is consistent with the offset direction of the micro lens. And the offset of the metal top layer or the metal sub-top layer in the X-axis direction and the Y-axis direction is related to the lateral main offset distance X and the longitudinal main offset distance Y, respectively. Specifically, the offset of the metal top layer is, for example, 1/3 to 19/20 of the offset of the microlens, and the offset of the metal sub-top layer is, for example, 1/3 to 19/20 of the offset of the microlens. Corresponding to the offset of the metal top layer and the metal sub-top layer, the wall surface of the light-transmitting trench 300 near the center of the pixel array 10 has a second slope structure 502. The position of the light-transmitting structure 600 is shown in the dashed block diagram of fig. 16, corresponding to the second slope structure 502. The light-transmitting structure 600 is disposed on the photoelectric reaction region 101, and a wall surface of the light-transmitting structure 600 connected to the second slope structure 502 is a slope, as shown in an outer dashed frame of fig. 16. In this embodiment, the slope gradient of the light-transmitting structure 600 in the X-axis direction and the Y-axis direction may be different or the same. And the slope gradient of the light-transmitting structure 600 may be different by changing the width of the step structure 400 in different pixel units 11.
Referring to fig. 15 and 17, in an embodiment of the invention, when the principal ray angle is 0, the offset of the microlens 800 is 0. Correspondingly, the first slave offset distance of the metal sub-top layer is 0, and the second slave offset distance of the metal top layer is 0. The incident light is refracted through the microlens 800 and then passes through the functional layer 700 and the light-transmitting layer 601, the light-transmitting structure 600, and reaches the photo-electric reaction region 101. When the principal ray axis angle is greater than 0, the lateral principal shift distance of the microlens 800 is x, and the longitudinal principal shift distance is y. When an incident light ray passes through the microlens 800, a part of the incident light ray is blocked by the metal top layer and reflected, and another part of the incident light ray passes through the dielectric layer 201 and reaches the storage region 102, so that a parasitic light response occurs in the storage region 102. Thus, in the present invention, when the lateral main offset distance of the microlens 800 is x, the longitudinal main offset distance is y. The metal top layer has a second slave offset distance and the metal sub-top layer has a first slave offset distance. And the second slope structure 502 is arranged on the dielectric layer 201, as shown in fig. 15, the incident light is difficult to enter the dielectric layer 201, and parasitic light response of the storage area 102 is avoided.
Referring to fig. 17 and 18, in one embodiment of the present invention, fig. 18 provides a global exposure charge domain pixel circuit diagram. The charge domain pixel circuit diagram shown in fig. 18 is based on the method of manufacturing an image sensor according to the present invention. And the pixel circuit of the image sensor provided by the invention can be distributed according to the layout shown in fig. 18. And as shown in fig. 18, the pixel circuit includes a first transfer tube M1, a second transfer tube M2, a global reset tube M3, a reset tube M4, a source follower tube M5, and a selection tube M6, as well as a storage capacitor C and a photodiode PD. In the present embodiment, the photodiode PD corresponds to the photo-reaction region 101, and the storage capacitor C corresponds to the storage region 102. In the pixel circuit provided by the invention, one end of the global reset tube M3 is electrically connected with the power supply V DD . The other end of the global reset tube M3 is electrically connected to one end of the photodiode PD and one end of the first transmission tube M1. Wherein the other end of the photodiode PD is grounded. In the present embodiment, the firstThe other end of the transmission tube M1 is electrically connected to one end of the second transmission tube M2 and one end of the storage capacitor C. Wherein the other end of the storage capacitor C is grounded. In this embodiment, the other end of the second transmission tube M2 is electrically connected to one end of the reset tube M4 and the driving end of the source follower tube M5. Wherein the other end of the reset tube M4 is electrically connected to the power supply V DD . In the present embodiment, one end of the source follower tube M5 is electrically connected to one end of the selection tube M6, and the other end of the source follower tube M5 is electrically connected to the power supply V DD . The other end of the selection tube M6 is used as the output terminal of the pixel circuit. In the present embodiment, the first transfer tube M1, the second transfer tube M2, the global reset tube M3, the reset tube M4, the source follower tube M5, and the selection tube M6 are Metal-Oxide-semiconductor field effect transistors (MOSFETs).
The invention provides an image sensor and a manufacturing method thereof, wherein the image sensor comprises a pixel array structure, a dielectric layer, a light transmission structure, a micro lens and a plurality of layers of metal wires. The pixel array structure comprises a plurality of photoelectric reaction areas and a plurality of storage areas, wherein the photoelectric reaction areas are adjacent to the storage areas. The dielectric layer is disposed on the pixel array structure. The light-transmitting structure penetrates through the medium layer and is connected with the photoelectric reaction area, and the side wall of the light-transmitting structure, which is far away from the center of the pixel array structure, is of a slope structure. The micro-lens is arranged on the light-transmitting structure, covers the photoelectric reaction area and deflects towards the direction of inclination of the slope structure. The multi-layer metal wiring is arranged in the dielectric layer, and the metal wiring is offset towards the direction of inclination of the slope structure. According to the image sensor provided by the invention, the receiving quantity of the pixel units at different positions in the pixel array to the incident light can be improved, and the outer ring parasitic light response of the pixel array of the image sensor is avoided, so that the accuracy of the optical signal processing of the image sensor is improved.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (11)

1. An image sensor, comprising:
the pixel array structure comprises a plurality of photoelectric reaction areas and a plurality of storage areas, wherein the photoelectric reaction areas are adjacent to the storage areas;
the dielectric layer is arranged on the pixel array structure;
the light-transmitting structure penetrates through the dielectric layer and is connected with the photoelectric reaction area, and the side wall, close to the center of the pixel array structure, of the light-transmitting structure is of a slope structure;
the micro lens is arranged on the light-transmitting structure, covers the photoelectric reaction area and deflects towards the direction of inclining the slope structure; and
and the metal wiring layers are arranged in the dielectric layers and are offset towards the direction of inclination of the slope structure.
2. The image sensor of claim 1, wherein a main offset distance is provided between a central axis of the microlens and a symmetry plane of the photoelectric reaction region, and a sub offset distance is provided between the metal wiring and a central axis of the storage region, wherein the sub offset distance is 1/3 to 19/20 of the main offset distance.
3. An image sensor according to claim 1, wherein in the plurality of layers of the metal wiring, the metal wiring on the top layer is offset in a direction in which the slope structure is inclined.
4. An image sensor according to claim 3, wherein in the plurality of layers of the metal wiring, the metal wiring on the top layer and the metal wiring on the sub-top layer are offset in a direction inclined toward the slope structure.
5. An image sensor according to claim 1, wherein a gate is provided on the pixel array structure, the gate is located between the photo-reactive region and the storage region, and the gate covers the storage region and a portion of the photo-reactive region.
6. An image sensor as in claim 5, wherein an orthographic projection of said metal wiring on said pixel array structure is located within said storage area and on said gate structure.
7. The image sensor of claim 1, wherein the image sensor comprises a color filter layer disposed on the light transmissive structure and a planarization layer disposed between the color filter layer and the microlenses.
8. An image sensor as in claim 1, wherein the light transmissive structure has a refractive index greater than a refractive index of the dielectric layer.
9. A method of manufacturing an image sensor, comprising the steps of:
providing a pixel array structure, wherein the pixel array comprises a plurality of photoelectric reaction areas and a plurality of storage areas, and the photoelectric reaction areas are adjacent to the storage areas;
forming a dielectric layer on the pixel array structure;
forming a plurality of layers of metal wiring in the dielectric layer;
forming a light-transmitting structure on the photoelectric reaction region, wherein the light-transmitting structure penetrates through the dielectric layer and is connected with the photoelectric reaction region, the side wall, close to the center of the pixel array structure, of the light-transmitting structure is a slope structure, and the metal wiring is offset towards the direction of inclination of the slope structure; and
and forming a micro lens on the light-transmitting structure, wherein the micro lens covers the photoelectric reaction area, and the micro lens is offset towards the inclined direction of the slope structure.
10. The method of manufacturing an image sensor of claim 9, wherein the step of forming the light transmissive structure comprises:
etching the dielectric layer to form a light-transmitting groove;
etching the groove wall of the light-transmitting groove for multiple times to form a step structure;
burying the step structure, and forming the slope structure in the light-transmitting groove; and
and filling the light-transmitting groove to form the light-transmitting structure.
11. The method of manufacturing an image sensor of claim 10, wherein the step of burying the step structure comprises:
forming a buried layer in the light-transmitting groove and on the dielectric layer; and
and etching the buried layer to expose the photoelectric reaction area.
CN202310483224.1A 2023-04-27 2023-04-27 Image sensor and manufacturing method thereof Pending CN116387335A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116884984A (en) * 2023-09-04 2023-10-13 合肥海图微电子有限公司 Image sensor and manufacturing method thereof
CN117319822A (en) * 2023-11-24 2023-12-29 合肥海图微电子有限公司 Image sensor and control method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116884984A (en) * 2023-09-04 2023-10-13 合肥海图微电子有限公司 Image sensor and manufacturing method thereof
CN116884984B (en) * 2023-09-04 2023-12-29 合肥海图微电子有限公司 Image sensor and manufacturing method thereof
CN117319822A (en) * 2023-11-24 2023-12-29 合肥海图微电子有限公司 Image sensor and control method thereof
CN117319822B (en) * 2023-11-24 2024-03-26 合肥海图微电子有限公司 Image sensor and control method thereof

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