CN116884856A - Integrated circuit product packaging method - Google Patents

Integrated circuit product packaging method Download PDF

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Publication number
CN116884856A
CN116884856A CN202310950660.5A CN202310950660A CN116884856A CN 116884856 A CN116884856 A CN 116884856A CN 202310950660 A CN202310950660 A CN 202310950660A CN 116884856 A CN116884856 A CN 116884856A
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CN
China
Prior art keywords
integrated circuit
solder
substrate
pins
packaging method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310950660.5A
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Chinese (zh)
Inventor
张一弛
王政尧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Riyuexin Semiconductor Suzhou Co ltd
Original Assignee
Riyuexin Semiconductor Suzhou Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Riyuexin Semiconductor Suzhou Co ltd filed Critical Riyuexin Semiconductor Suzhou Co ltd
Priority to CN202310950660.5A priority Critical patent/CN116884856A/en
Publication of CN116884856A publication Critical patent/CN116884856A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The application provides an integrated circuit product packaging method. The integrated circuit product packaging method comprises the following steps: providing a substrate; coating solder on the pins of the substrate; solidifying the solder on the pins; and soldering the pin contacts of the integrated circuit frame with the solidified solder by laser.

Description

Integrated circuit product packaging method
Technical Field
The present application relates to the field of semiconductors, and more particularly, to a method for packaging an integrated circuit product.
Background
In recent years, due to the continuous progress of semiconductor technology, the variety of integrated circuit products is also more diversified, with the recent progress of packaging technology. Currently, an emerging integrated circuit product using a ceramic substrate is gradually developed, however, a technology for improving the efficiency and yield of packaging the ceramic substrate is lacking in the market.
Disclosure of Invention
In view of the above, the present application provides an integrated circuit product packaging method to solve the above-mentioned problems.
According to an embodiment of the present application, an integrated circuit product packaging method is provided. The integrated circuit product packaging method comprises the following steps: providing a substrate; coating solder on the pins of the substrate; solidifying the solder on the pins; and soldering the pin contacts of the integrated circuit frame with the solidified solder by laser.
According to an embodiment of the present application, coating solder on the pins of the substrate includes: and coating the solder on the pins by adopting a steel screen printing mode.
According to an embodiment of the application, solidifying the solder on the pins comprises: and solidifying the solder on the pins through reflow soldering.
According to an embodiment of the application, the temperature of the reflow soldering is greater than 250 ℃.
According to an embodiment of the application, the solder is solder paste.
According to an embodiment of the application, the integrated circuit product packaging method further comprises the step of electrically connecting the integrated circuit chip with the circuit on the substrate.
According to an embodiment of the present application, electrically connecting the integrated circuit chip with the circuit on the substrate includes: coating solder on the circuit on the substrate in a steel screen printing mode; attaching the integrated circuit chip to a circuit on the substrate; and solidifying the solder by reflow soldering.
According to an embodiment of the present application, electrically connecting the integrated circuit chip with the circuit on the substrate includes: bonding the integrated circuit chip to the substrate by an adhesive; curing the adhesive by baking; and bonding wires on the integrated circuit chip and the substrate for connection.
According to an embodiment of the application, the baking temperature is 100-200 ℃.
According to an embodiment of the present application, the material of the pin contact of the integrated circuit frame is different from the material of the pin of the substrate.
In the integrated circuit product packaging method provided by the application, the solder is coated on the pins of the substrate in a steel screen printing mode, so that the solder can be uniformly and rapidly coated on the pins, and the condition of bridging caused by excessive solder or cold joint caused by too little solder is avoided; in addition, the pins of the integrated circuit frame are welded on the solder through laser, and the laser welding machine can accurately and automatically position, so that high-precision heterogeneous metal connection can be realized.
Drawings
The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute a part of this specification, illustrate the application and together with the description serve to explain, without limitation, the application. In the drawings:
FIG. 1 illustrates a method flow diagram of a method for packaging an integrated circuit product according to one embodiment of the application.
Fig. 2A is a schematic diagram illustrating a stage of an integrated circuit product in a method for packaging an integrated circuit product according to an embodiment of the application.
Fig. 2B illustrates a schematic structure of an integrated circuit product at a stage in a method for packaging an integrated circuit product according to an embodiment of the application.
Fig. 2C illustrates a schematic structure of an integrated circuit product at a stage in a method for packaging an integrated circuit product according to an embodiment of the application.
Fig. 2D illustrates a schematic structure of an integrated circuit product at a stage in a method for packaging an integrated circuit product according to an embodiment of the application.
Fig. 3 illustrates a method flow diagram of a method of packaging an integrated circuit product according to another embodiment of the application.
Fig. 4 illustrates a schematic structure of an integrated circuit product at a stage in a method for packaging an integrated circuit product according to an embodiment of the application.
Fig. 5 illustrates a method flow diagram of a method of packaging an integrated circuit product according to another embodiment of the application.
Fig. 6A is a schematic diagram illustrating a stage of an integrated circuit product in a method for packaging an integrated circuit product according to an embodiment of the application.
Fig. 6B illustrates a schematic structure of an integrated circuit product at a stage in a method of packaging an integrated circuit product according to an embodiment of the application.
Fig. 6C illustrates a schematic structure of an integrated circuit product at a stage in a method of packaging an integrated circuit product according to an embodiment of the application.
Detailed Description
The following disclosure provides various embodiments or examples that can be used to implement the various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. It is to be understood that these descriptions are merely exemplary and are not intended to limit the present disclosure. For example, in the following description, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may include embodiments in which additional components are formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for brevity and clarity purposes and does not itself represent a relationship between the different embodiments and/or configurations discussed.
Moreover, spatially relative terms, such as "under," "below," "lower," "upper," and the like, may be used herein to facilitate a description of the relationship between one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be placed in other orientations (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally means that the actual value is within plus or minus 10%, 5%, 1% or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within an acceptable standard error of the average value, depending on the consideration of the person having ordinary skill in the art to which the present application pertains. It is to be understood that all ranges, amounts, values, and percentages used herein (e.g., to describe amounts of materials, lengths of time, temperatures, operating conditions, ratios of amounts, and the like) are modified by the word "about" unless otherwise specifically indicated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present specification and attached claims are approximations that may vary depending upon the desired properties. At least these numerical parameters should be construed as the number of significant digits and by applying ordinary rounding techniques. Herein, a numerical range is expressed as from one end point to another end point or between two end points; unless otherwise indicated, all numerical ranges recited herein include endpoints.
Fig. 1 illustrates a method flow diagram of an integrated circuit product packaging method 1 according to an embodiment of the application. In certain embodiments, the integrated circuit product packaging method 1 is applied to the packaging of an integrated circuit product comprising a ceramic substrate. In other embodiments, the integrated circuit product packaging method 1 may also be applied to packaging of integrated circuit products including other kinds of substrates. The present application is not limited to follow the process flow shown in fig. 1, provided that substantially the same results are obtained. In some embodiments, the integrated circuit product packaging method 1 can be generalized as follows:
step 11: providing a substrate;
step 12: coating solder on the pins of the substrate;
step 13: solidifying the solder on the pins; and
step 14: and welding the pin joints of the integrated circuit frame with the solidified solder by laser.
Referring to fig. 2A, fig. 2A illustrates a schematic structure of an integrated circuit product at a stage in the method 1 for packaging an integrated circuit product according to an embodiment of the application. As shown in fig. 2A, a substrate 20 is provided as a substrate for an integrated circuit product, wherein the substrate 20 includes pins 21 and circuitry 22 thereon. In some embodiments, the substrate 20 may be a ceramic substrate. In some embodiments, pins 211 are configured to connect with pins of an integrated circuit frame, and circuit 22 is configured to connect with an integrated circuit chip.
Referring to fig. 2B, fig. 2B illustrates a schematic structure of an integrated circuit product at a stage in the method 1 for packaging an integrated circuit product according to an embodiment of the application. As shown in fig. 2B, solder P21 is coated on the leads 21 of the substrate 20. In some embodiments, the solder P21 may be a solder paste. In certain embodiments, the solder P21 comprises lead or antimony. In some embodiments, the solder P21 may be applied to the pins 21 using a steel screen printing process. Since no other objects are blocked, the solder P21 can be coated on the pins 21 rapidly and uniformly by adopting a steel screen printing mode, and the flatness is good, so that the condition of bridging caused by excessive solder or cold joint caused by too little solder is avoided.
Referring to fig. 2C, fig. 2C illustrates a schematic structure of an integrated circuit product at a stage in the method 1 for packaging an integrated circuit product according to an embodiment of the application. As shown in fig. 2C, the solder P21 on the leads 21 is solidified to form solidified solder P21'. In some embodiments, solder P21 'on pins 21 may be solidified by reflow to form solder P21'. The temperature of the reflow soldering can be regulated and controlled by parameters, so that the temperature of the reflow soldering can be preset according to the types of solder paste (such as high-temperature solder paste or low-temperature solder paste), and the types of solder paste are more abundant. In certain embodiments, the temperature of the reflow is greater than 250 ℃.
Referring to fig. 2D, fig. 2D illustrates a schematic structure of an integrated circuit product at a stage in the method 1 for packaging an integrated circuit product according to an embodiment of the application. As shown in fig. 2D, the pin contacts 30 of the integrated circuit frame are soldered to the solidified solder P21' by a laser. In some embodiments, the material of the pin contacts 30 of the integrated circuit frame is different from the material of the pins 21 of the substrate 20. In some embodiments, the pin contacts 30 of the integrated circuit frame comprise copper, nickel, silver, or nickel palladium gold or other materials, and the substrate 20 comprises an aluminum nitride ceramic substrate, an aluminum oxide ceramic substrate, a PCB board, or other substrate. The leads 21 of the substrate 20 may be made of copper, nickel, silver, nickel palladium, gold, or other materials. Since the laser welding machine can be accurately and automatically positioned, the welding of the solidified solder P21' to the pin contact 30 using the laser has an advantage of high accuracy. Accordingly, the integrated circuit product packaging method 1 achieves connection of dissimilar metals between the leads 21 of the substrate 20 and the lead pads 30 of the integrated circuit frame.
In the integrated circuit product packaging method 1 provided by the application, the solder P21 is coated on the pins 21 of the substrate 20 in a steel screen printing mode, so that the solder P21 can be coated on the pins 21 rapidly and uniformly, and the condition of bridging caused by excessive solder or cold joint caused by too little solder is avoided; in addition, the pins 30 of the integrated circuit frame are welded on the solder P21' by laser, and since the laser welding machine can accurately and automatically position, high-precision heterogeneous metal connection can be realized.
Fig. 3 illustrates a method flow diagram of an integrated circuit product packaging method 1' according to another embodiment of the application. In certain embodiments, the integrated circuit product packaging method 1' is applied to the packaging of an integrated circuit product comprising a substrate. The present application is not limited to follow the process flow shown in fig. 3, provided that substantially the same results are obtained. In some embodiments, the integrated circuit product packaging method 1 'is substantially the same as the integrated circuit product packaging method 1 of the embodiment of fig. 1, except that step 40 follows step 13, and therefore, the same parts of the integrated circuit product packaging method 1' as the integrated circuit product packaging method 1 are omitted herein.
Step 40: the integrated circuit chip is electrically connected with the circuit on the substrate.
Referring to fig. 4 for step 40, fig. 4 illustrates a schematic structure of an integrated circuit product at a stage in an integrated circuit product packaging method 1' according to an embodiment of the application. As shown in fig. 4, after the solder P21 is solidified to form solder P21', the integrated circuit chip 51 and the integrated circuit chip 52 are electrically connected to the circuit 22 on the substrate 20. In the embodiment of fig. 4, the integrated circuit chip 51 and the integrated circuit chip 52 are electrically connected to the circuit 22 on the substrate 20 in different ways, respectively. For example, the integrated circuit chip 51 and the integrated circuit chip 52 may be connected by soldering or mounting, respectively.
Specifically, for the integrated circuit chip 51, the solder P51' may be coated on the circuit 22 on the substrate 20 by a steel screen printing method; next, the integrated circuit chip 51 is attached to the circuit 22 on the substrate 20; finally, the solder is cured by reflow to electrically connect the integrated circuit chip 51 and the circuit 22 on the substrate 20. In certain embodiments, the reflow temperature is about 250 ℃ or less than 250 ℃.
Specifically, for the integrated circuit chip 52, the integrated circuit chip 52 may be stuck on the substrate 20 by the adhesive P52; next, the adhesive P52 is cured by baking; finally, bonding wires are used to make the connection between the integrated circuit chip 52 and the circuitry 22 on the substrate 20. In certain embodiments, the baking temperature is between 100-200 ℃. In some embodiments, the adhesive P52 may comprise silver paste.
It should be noted that, since the process temperature of the integrated circuit chip 51 and the integrated circuit chip 52 in the step 40 is less than the reflow temperature of the step 13, the process conforms to the flow of the high temperature process to the low temperature process, and the post process will not have adverse effect on the pre-process.
Although in the embodiment of fig. 4, integrated circuit chip 51 and integrated circuit chip 52 are electrically connected to circuit 22 on substrate 20 in different ways, this is not a limitation of the present application. The integrated circuit chip 51 and the integrated circuit chip 52 can also be electrically connected to the circuit 22 on the substrate 20 in the same manner.
Step 14 in the embodiment of fig. 1 follows step 40, whereby the connection of the dissimilar metals between the leads 21 of the substrate 20 and the lead contacts 30 of the integrated circuit frame is achieved.
In the embodiment of fig. 4, step 40 follows step 13. As described above, since the process temperature of the integrated circuit chip 51 and the integrated circuit chip 52 is lower than the reflow temperature of step 13 in step 40, the process is in line with the flow of the high temperature process to the low temperature process, and the post process will not adversely affect the pre-process. It should be noted that the present application is not limited to the execution sequence of step 40 following step 13. Referring to fig. 5, fig. 5 illustrates a method flow diagram of an integrated circuit product packaging method 1 "according to another embodiment of the present application. The embodiment of fig. 5 is substantially the same as the embodiment of fig. 3, except that the execution sequence of step 40 follows step 14, and those skilled in the art will readily understand the details of the embodiment of fig. 5 after reading the above embodiments, so that the detailed description is omitted herein for brevity. Since the process steps shown in the embodiment of fig. 5 are identical to the process steps from the high temperature process to the low temperature process, the post process will not adversely affect the pre process.
In other embodiments, the soldering process of the integrated circuit chip 51 and the mounting process of the integrated circuit chip 52 are not limited to be implemented in the same step. In some embodiments, the soldering process of the integrated circuit chip 51 may be performed in step 12. Specifically, referring to fig. 6A, similar to that shown in fig. 2B, when the solder P21 is coated on the leads 21 of the substrate 20, the solder P51 may be synchronously coated on the circuit 22. In some embodiments, a steel screen printing process may be used to apply solder P21 and solder P51 on both the leads 21 and the circuit 22. Next, referring to fig. 6B, the integrated circuit chip 51 is placed on the solder P51; next, referring to fig. 6C, similar to that shown in fig. 2C, the solder P21 on the lead 21 and the solder P51 on the circuit 22 are solidified to form solidified solder P21 'and solder P51', respectively. In certain embodiments, the temperature of the reflow is greater than 250 ℃. Next, the mounting process of the integrated circuit chip 52 may be first performed with reference to the embodiment of fig. 3, or the pin pads 30 of the integrated circuit frame may be first soldered to the solidified solder P21' with reference to the embodiment of fig. 2D by laser. The process flow from high temperature process to low temperature process is also satisfied, so that the post process will not have adverse effect on the pre process.
The process shown in fig. 6A-6C simultaneously completes the solder coating process on pins 21 and circuits 22, which is more efficient than the process shown in fig. 2A-2D.
As used herein, the terms "approximately," "substantially," and "about" are used to describe and account for minor variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely and instances where it occurs to the close approximation. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1% or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to the other endpoint, or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term "substantially coplanar" may refer to two surfaces within a few micrometers (μm) positioned along a same plane, for example, within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm positioned along the same plane. When referring to "substantially" the same value or property, the term may refer to a value that is within ±10%, 5%, 1% or 0.5% of the average value of the values.
As used herein, the terms "approximately," "substantially," and "about" are used to describe and explain minor variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely and instances where it occurs to the close approximation. For example, when used in conjunction with a numerical value, the term can refer to a range of variation of less than or equal to ±10% of the numerical value, e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values may be considered to be "substantially" or "about" the same if the difference between the two values is less than or equal to ±10% (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%) of the average value of the values. For example, "substantially" parallel may refer to a range of angular variation of less than or equal to ±10° relative to 0 °, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, "substantially" perpendicular may refer to a range of angular variation of less than or equal to ±10° relative to 90 °, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.
For example, two surfaces may be considered to be coplanar or substantially coplanar if the displacement between the two surfaces is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm. A surface may be considered planar or substantially planar if the displacement of the surface relative to the plane between any two points on the surface is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm.
As used herein, the singular terms "a" and "an" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the former component is directly on (e.g., in physical contact with) the latter component, as well as the case where one or more intermediate components are located between the former component and the latter component.
As used herein, spatially relative terms such as "below," "lower," "above," "upper," "lower," "left," "right," and the like may be used herein for ease of description to describe one component or feature's relationship to another component or feature as illustrated in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.
The foregoing has outlined features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure and are susceptible to various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

Claims (10)

1. An integrated circuit product packaging method, comprising:
providing a substrate;
coating solder on the pins of the substrate;
solidifying the solder on the pins; and
and welding the pin joints of the integrated circuit frame with the solidified solder by laser.
2. The integrated circuit product packaging method of claim 1, wherein coating solder on the pins of the substrate comprises:
and coating the solder on the pins by adopting a steel screen printing mode.
3. The integrated circuit product packaging method of claim 2, wherein curing the solder on the pins comprises:
and solidifying the solder on the pins through reflow soldering.
4. The integrated circuit product packaging method of claim 3, wherein the reflow soldering temperature is greater than 250 ℃.
5. The integrated circuit product packaging method of claim 3, wherein the solder is a solder paste.
6. The integrated circuit product packaging method of claim 1, further comprising:
and electrically connecting the integrated circuit chip with the circuit on the substrate.
7. The method of claim 6, wherein electrically connecting the integrated circuit chip to circuitry on the substrate comprises:
coating solder on the circuit on the substrate in a steel screen printing mode;
attaching the integrated circuit chip to a circuit on the substrate; and
the solder is cured by reflow.
8. The method of claim 6, wherein electrically connecting the integrated circuit chip to circuitry on the substrate comprises:
bonding the integrated circuit chip to the substrate by an adhesive;
curing the adhesive by baking; and
and circuit bonding wires on the integrated circuit chip and the substrate are used for connection.
9. The integrated circuit product packaging method of claim 8, wherein the baking temperature is between 100-200 ℃.
10. The integrated circuit product packaging method of claim 1, wherein the material of the pin contacts of the integrated circuit frame is different from the material of the pins of the substrate.
CN202310950660.5A 2023-07-31 2023-07-31 Integrated circuit product packaging method Pending CN116884856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310950660.5A CN116884856A (en) 2023-07-31 2023-07-31 Integrated circuit product packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310950660.5A CN116884856A (en) 2023-07-31 2023-07-31 Integrated circuit product packaging method

Publications (1)

Publication Number Publication Date
CN116884856A true CN116884856A (en) 2023-10-13

Family

ID=88268099

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310950660.5A Pending CN116884856A (en) 2023-07-31 2023-07-31 Integrated circuit product packaging method

Country Status (1)

Country Link
CN (1) CN116884856A (en)

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