CN116865100A

CN116865100A - VCSEL wafer

Info

Publication number: CN116865100A
Application number: CN202310816578.3A
Authority: CN
Inventors: 林珊珊; 李念宜; 刘赤宇
Original assignee: Zhejiang Ruixi Technology Co ltd
Current assignee: Zhejiang Ruixi Technology Co ltd
Priority date: 2023-07-05
Filing date: 2023-07-05
Publication date: 2023-10-10

Abstract

A VCSEL wafer is disclosed. The VCSEL wafer includes: the wafer comprises a wafer body and a test circuit structure integrated on the wafer level in the wafer body, wherein the wafer body comprises a bonding pad and a plurality of VCSEL chips, at least part of the VCSEL chips in the VCSEL chips are points to be tested, and the test circuit structure comprises a plurality of electrical connection wires electrically connected between the points to be tested and the bonding pad. Therefore, the VCSEL wafer can be tested without cutting, packaging and other working procedures, the testing difficulty and the testing cost can be reduced, the influence of the cutting, packaging and other working procedures on the accuracy of the testing result can be avoided, the testing period can be shortened to a greater extent, and the testing result can be obtained faster. Further, since the test result can be obtained before dicing and whether the VCSEL chip has a defect can be determined, if the VCSEL chip has a defect, the VCSEL chip can be screened out in advance, and the dicing, packaging and other steps are omitted.

Description

VCSEL wafer

Technical Field

The present application relates to the field of semiconductor lasers, and more particularly to VCSEL wafers.

Background

A VCSEL (Vertical-Cavity Surface Emitting Laser) is a semiconductor Laser that emits Laser light in a direction perpendicular to its substrate. The VCSEL has the characteristics of small divergence angle, symmetrical light beams, high wavelength heat stability, stable light beam quality, single longitudinal mode output, high photoelectric conversion efficiency, small volume, low threshold current, low power consumption, easy integration and the like, and has huge application potential in the fields of communication, consumption and vehicle-mounted. Currently, VCSEL products are widely applied to industries such as close-range optical fiber communication, face recognition, 3D sensing and the like.

In VCSEL chip production, typically, an initial wafer is processed to form a VCSEL wafer having a multi-VCSEL structure, and then the VCSEL wafer is diced and packaged to obtain packaged VCSEL chips. To ensure the reliability of the VCSEL chips, more stringent inspection and screening of the VCSEL chips is required, for example, not only conventional ATE (Automatic test equipment ) testing, but also wafer level burn-in acceleration test is required to determine the reliability of the VCSEL wafer. However, the existing accelerated aging test has a number of problems.

Specifically, the conventional burn-in acceleration test requires sampling the diced VCSEL wafer, packaging the decimated VCSEL wafer, and then testing the packaged VCSEL wafer to determine the performance of the VCSEL wafer. That is, the conventional burn-in acceleration test is to test a VCSEL wafer after dicing and packaging. However, the package may add additional influencing factors, which may further influence the reliability of the test results. The reliability of the test results may depend on the uniformity of the package, and additional packages also increase the time cost, which is detrimental to the market competitiveness of VCSEL chips.

It is worth mentioning that VCSEL wafer production is done by the chip manufacturer and VCSEL packaging is done by the packaging manufacturer. The VCSEL wafer passes through at least two industry chain nodes from the chip fabrication facility to the packaging facility, during which time the performance of the VCSEL wafer is also affected. The non-uniformity of the packaging of individual VCSEL wafers by the packaging factory can further affect the testing results of the VCSEL wafers.

In existing burn-in schemes for VCSEL chips, the VCSEL wafer can be tested by custom probe cards, however, custom probe card circuits are complex and the test cost is expensive.

Therefore, a new VCSEL wafer burn-in acceleration test scheme is needed.

Disclosure of Invention

An advantage of the present application is that it provides a VCSEL wafer that is suitable for testing directly by probe energization, which reduces testing difficulties.

Another advantage of the present application is to provide a VCSEL wafer, in which the VCSEL wafer forms a test circuit structure on a wafer level, and the testing can be performed without performing dicing, packaging, and the like, so that the testing cost can be reduced.

Another advantage of the present application is to provide a VCSEL wafer, where the VCSEL wafer can be tested without dicing, packaging, etc., and the effect of the dicing, packaging, etc. process on the accuracy of the test result can be avoided.

Still another advantage of the present application is to provide a VCSEL wafer, in which the VCSEL wafer can be tested without dicing, packaging, etc., and the test cycle can be shortened to a greater extent, and the test result can be obtained faster.

Still another advantage of the present application is to provide a VCSEL wafer, in which the VCSEL can be tested before dicing, further, a test result can be obtained before dicing and whether a VCSEL chip has a defect can be determined, and if a defect exists, the VCSEL chip can be screened out in advance, so that dicing, packaging, and the like steps are omitted.

Still another advantage of the present application is to provide a VCSEL wafer, in which the VCSEL wafer can additionally add a point to be inspected and select its layout position, and in some embodiments of the present application, the additionally added point to be inspected does not occupy the forming space of the original VCSEL chip.

It is yet another advantage of the present application to provide a VCSEL wafer in which the test coverage of the VCSEL wafer is adjustable.

Yet another advantage of the present application is to provide a VCSEL wafer that can be manufactured by a mature chip manufacturing process, improving the structural stability and reliability of the VCSEL wafer.

To achieve at least one of the above or other advantages and objects, according to one aspect of the present application, there is provided a VCSEL-enabled wafer comprising:

the wafer main body comprises a bonding pad and a plurality of VCSEL chips, wherein at least part of the VCSEL chips in the plurality of VCSEL chips are points to be tested; and

the test circuit structure integrated on the wafer level in the wafer main body comprises a plurality of electric connection wires electrically connected between the to-be-tested point and the bonding pad.

In the VCSEL wafer of the present application, the wafer body has a plurality of PCM test regions, at least one of the sites to be tested being formed in the PCM test regions.

In the VCSEL wafer of the present application, the wafer body has at least one scribe line, and at least one of the points to be tested is formed in the scribe line.

In the VCSEL wafer of the present application, the length dimension of the point to be measured formed in the scribe line is less than or equal to 55 μm, and the width dimension is less than or equal to 55 μm.

In the VCSEL wafer of the present application, all of the VCSEL chips form the point to be measured.

In the VCSEL wafer of the present application, at least three VCSEL chips among the plurality of VCSEL chips are the points to be measured, and at least three points to be measured are uniformly distributed.

In the VCSEL wafer of the present application, the bonding pad includes a plurality of bonding pads, and the test circuit structure includes a first electrical connection line connected between the plurality of bonding pads and a second electrical connection line connected between the point to be tested and the first electrical connection line.

In the VCSEL wafer of the present application, the first electrical connection line has a closed loop structure end to end.

In the VCSEL wafer of the present application, a plurality of the solder joints are adjacent to an outer edge of the VCSEL wafer.

In the VCSEL wafer of the present application, the point to be tested has a chip positive electrode and a chip negative electrode, and the second electrical connection line includes a positive electrical connection line connected to the chip positive electrode and a negative electrical connection line connected to the chip negative electrode.

Further objects and advantages of the present application will become fully apparent from the following description and the accompanying drawings.

These and other objects, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the appended claims.

Drawings

These and/or other aspects and advantages of the present application will become more apparent and more readily appreciated from the following detailed description of the embodiments of the application, taken in conjunction with the accompanying drawings, wherein:

fig. 1 illustrates a schematic structure of a VCSEL wafer according to an embodiment of the present application.

Fig. 2 illustrates a partially enlarged schematic view of a VCSEL wafer in accordance with an embodiment of the present application.

Fig. 3 illustrates another partial enlarged schematic view of a VCSEL wafer according to an embodiment of the present application.

Fig. 4 illustrates yet another partial enlarged schematic view of a VCSEL wafer according to an embodiment of the present application.

Detailed Description

The terms and words used in the following description and claims are not limited to literal meanings, but are used only by the inventors to enable a clear and consistent understanding of the application. It will be apparent to those skilled in the art, therefore, that the following description of the various embodiments of the application is provided for illustration only and not for the purpose of limiting the application as defined by the appended claims and their equivalents.

It will be understood that the terms "a" and "an" should be interpreted as referring to "at least one" or "one or more," i.e., in one embodiment, the number of elements may be one, while in another embodiment, the number of elements may be plural, and the term "a" should not be interpreted as limiting the number.

Although ordinal numbers such as "first," "second," etc., will be used to describe various components, those components are not limited herein. The term is used merely to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component, without departing from the teachings of the present inventive concept. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, or groups thereof.

Summary of the application: as described above, the conventional burn-in acceleration test tests the packaged VCSEL wafer to determine the performance of the VCSEL wafer. That is, the conventional burn-in acceleration test is to test a VCSEL wafer after dicing and packaging. However, the package may add additional influencing factors, which may further influence the reliability of the test results. The reliability of the test results may depend on the uniformity of the package, and additional packages also increase the time cost, which is detrimental to the market competitiveness of VCSEL chips.

Considering the influence of packaging on the aging test of the VCSEL wafer, the application proposes to optimize the structure of the VCSEL wafer so that the VCSEL wafer can realize the aging test under the condition of no packaging. In particular, test circuit structures may be formed on a wafer level so that the VCSEL wafer can be burn-in tested directly by probes.

Based on this, according to one aspect of the present application, the present application proposes a VCSEL wafer comprising: the wafer comprises a wafer body and a test circuit structure integrated on the wafer level in the wafer body, wherein the wafer body comprises a bonding pad and a plurality of VCSEL chips, at least part of the VCSEL chips in the VCSEL chips are points to be tested, and the test circuit structure comprises a plurality of electrical connection wires electrically connected between the points to be tested and the bonding pad.

Having described the basic principles of the present application, various non-limiting embodiments of the present application will now be described in detail with reference to the accompanying drawings.

Illustrative VCSEL wafer: as shown in fig. 1 to 4, a VCSEL wafer according to an embodiment of the present application is illustrated, wherein the VCSEL wafer includes a wafer body and a test circuit structure integrated with the wafer body at a wafer level. The wafer body includes a plurality of VCSEL chips and pads (pads) formed on a surface of the wafer body. At least some of the VCSEL chips are used as points to be measured. The bonding pad comprises a plurality of welding spots serving as connecting ends for connecting the wafer main body with external equipment. The test circuit structure comprises a plurality of electric connection wires electrically connected between the to-be-tested point and the bonding pad. That is, the VCSEL wafer is formed into a test circuit structure suitable for testing. In this way, the requirements on the detection equipment and the testing difficulty can be reduced, and the testing cost is reduced, for example, the test is not required to be performed through a customized probe card provided with a complex circuit. The VCSEL wafer can be tested by using the contact probe, and the contact probe is abutted against the bonding pad and can be tested by a tester connected with the contact probe after being powered on. In addition, the VCSEL wafer can be tested without cutting, packaging and other working procedures, so that the test cost can be further reduced, the influence of the cutting, packaging and other working procedures on the accuracy of the test result can be avoided, the test period can be shortened to a greater extent, and the test result can be obtained faster. Further, since the test result can be obtained before dicing and whether the VCSEL chip has a defect can be determined, if the VCSEL chip has a defect, the VCSEL chip can be screened out in advance, and the dicing, packaging and other steps are omitted.

The connection mode between the point to be tested, the point to be tested and the bonding pad can be selected according to actual requirements, and then a test circuit structure suitable for testing is formed. It should be appreciated that the VCSEL wafer provided with the test circuit structure is suitable for burn-in testing, and that it may be adapted for other types of performance testing by designing the test circuit structure.

It should be noted that the VCSEL wafer may have VCSEL chips arranged at specific positions and used as points to be measured. For example, the wafer body has a plurality of PCM test regions for performing PCM testing, where VCSEL chips are typically not formed. In the manufacturing process of the VCSEL wafer, VCSEL chips can be formed in the PCM test area and used as to-be-tested points, as shown in figure 2, and the VCSEL chips are specially used for performance test. In this way, the formation space of the VCSEL chips that would otherwise be expected to form the VCSEL package product is not occupied. That is, in some embodiments of the present application, at least one of the points to be tested is formed in the PCM test region.

The to-be-tested points can be arranged in each PCM test area so as to be distributed on all parts of the VCSEL wafer in a scattered way, the whole VCSEL wafer is covered, and the reliability of sampling test results is improved.

For another example, the wafer body has at least one dicing street along which the VCSEL wafer is subsequently diced, so that VCSEL chips are typically not formed at the dicing street. In the application, VCSEL chips can be formed at the dicing channels in the VCSEL wafer manufacturing process and used as to-be-measured points, as shown in figure 3, and the VCSEL chips are specially used for performance testing. In this way, the formation space of the VCSEL chips that would otherwise be expected to form a VCSEL package product is not occupied. And the to-be-tested point at the dicing street does not affect the yield of the VCSEL chip even if the structure is damaged when the VCSEL wafer is subsequently diced.

The size of the point to be measured at the cutting path is smaller than 55 x 55 mu m ² I.e. the length of the point to be measured at the cutting lane is smaller thanOr equal to 55 μm and a width dimension less than or equal to 55 μm. And a plurality of to-be-measured points can be arranged on each cutting channel so as to be distributed on all parts of the VCSEL wafer in a scattered way, and the whole VCSEL wafer is covered. And the size of the to-be-measured point at the cutting channel is smaller, so that the distribution density of the to-be-measured point can be flexibly adjusted according to the requirement, and the coverage rate of the to-be-measured point is further adjusted. For example, the distribution density of the points to be measured is increased, and the coverage rate of the points to be measured is improved.

For the VCSEL chips with higher requirements on performance reliability, each VCSEL chip can be tested, and each VCSEL chip is used as a to-be-tested point. That is, all the VCSEL chips form the point to be tested, with a coverage of 100%, as shown in fig. 4.

Preferably, the points to be measured are uniformly dispersed throughout the VCSEL wafer. Accordingly, in some embodiments of the present application, at least three VCSEL chips among the plurality of VCSEL chips are the points to be measured, and at least three of the points to be measured are uniformly distributed. The distance between every two adjacent points to be measured is basically equal, and can be expressed as follows: the difference value of the distances between every two adjacent points to be detected is smaller than or equal to a preset value.

In an embodiment of the present application, each of the VCSEL chips includes at least one VCSEL emission point, i.e., includes one or more VCSEL emission points. Each VCSEL light emitting point includes a light emitting body including a substrate layer, an N-DBR, an active region, a P-DBR, and a confinement layer having a confinement hole, and a light emitting point anode and a light emitting point cathode connected to the light emitting body.

In an embodiment of the application, the test circuit structure comprises a first electrical connection wire connected between a plurality of welding spots and a second electrical connection wire connected between the to-be-tested point and the first electrical connection wire. That is, the plurality of electrical connection lines includes a first electrical connection line connected between the plurality of pads and a second electrical connection line connected between the point to be measured and the first electrical connection line.

In the embodiment of the application, the point to be tested is provided with a chip anode and a chip cathode, and the second electric connecting wire comprises a positive electric connecting wire connected with the chip anode and a negative electric connecting wire connected with the chip cathode.

In the embodiment of the present application, as shown in fig. 1, a plurality of the solder joints are adjacent to the outer edge of the VCSEL wafer, so as to facilitate contact probing by a probe. The first electric connecting wire is connected between every two adjacent welding spots and is provided with a closed ring structure connected end to end, so that the power-on synchronism of each VCSEL chip is facilitated.

In an embodiment of the present application, during testing of the VCSEL wafer, the VCSEL wafer is electrically connected to a current source. It should be appreciated that the VCSEL wafer may also be electrically connected to a voltage source during testing of the VCSEL wafer. When the VCSEL wafer is electrically connected with a voltage source, a plurality of welding spots and a plurality of points to be tested can be designed in series or in parallel according to actual conditions.

It should be noted that, in the embodiment of the present application, the VCSEL wafer may be manufactured by a mature chip manufacturing process, so as to improve the structural stability and reliability of the VCSEL wafer. Specifically, during the manufacturing process of manufacturing the VCSEL wafer, photolithography is performed on the wafer, and the forming position of the VCSEL chip can be defined by designing the mask pattern, and the VCSEL chip is formed. In the process of manufacturing the VCSEL wafer of the present application, the formation position of the VCSEL chip can be defined in a specific area (for example, PCM test area, scribe line) by adjusting the mask pattern, and the VCSEL chip is formed in the specific area as the point to be measured. And metal can be plated in a preset area in the VCSEL wafer process to form a plurality of electric connection wires which are arranged according to a preset arrangement mode.

In summary, the VCSEL wafer according to the embodiments of the present application is illustrated, and the VCSEL wafer forms a test circuit structure at a wafer level, and can be tested without performing processes such as dicing, packaging, etc., so that the test difficulty and the test cost can be reduced, the influence of the processes such as dicing, packaging, etc. on the accuracy of the test result can be avoided, the test period can be shortened to a greater extent, and the test result can be obtained faster. Further, since the test result can be obtained before dicing and whether the VCSEL chip has a defect can be determined, if the VCSEL chip has a defect, the VCSEL chip can be screened out in advance, and the dicing, packaging and other steps are omitted.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not intended to be limiting, and these advantages, benefits, effects, etc. are not to be considered as essential to the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not necessarily limited to practice with the above described specific details.

Claims

1. A VCSEL wafer, comprising:

2. The VCSEL wafer of claim 1, wherein the wafer body has a plurality of PCM test regions, at least one of the sites to be tested being formed in the PCM test regions.

3. The VCSEL wafer of claim 1, wherein the wafer body has at least one scribe line, at least one of the sites being tested being formed in the scribe line.

4. A VCSEL wafer as claimed in claim 3, wherein the length dimension of the spot to be measured formed in the scribe line is less than or equal to 55 μm and the width dimension is less than or equal to 55 μm.

5. The VCSEL wafer of claim 1, wherein all of the VCSEL chips form the point-to-be-measured.

6. The VCSEL wafer of claim 1, wherein at least three of the plurality of VCSEL chips are the points to be measured, the at least three points to be measured being evenly distributed.

7. The VCSEL wafer of claim 1, wherein the pad comprises a plurality of pads, the test circuit structure comprising a first electrical connection line connected between a plurality of the pads and a second electrical connection line connected between the point to be tested and the first electrical connection line.

8. The VCSEL wafer of claim 7, wherein the first electrical connection line has a closed loop structure end to end.

9. The VCSEL wafer of claim 7, wherein a plurality of the solder joints are adjacent to an outer edge of the VCSEL wafer.

10. The VCSEL wafer of claim 7, wherein the point-to-be-tested has a die positive electrode and a die negative electrode, the second electrical connection line comprising a positive electrical connection line connected to the die positive electrode and a negative electrical connection line connected to the die negative electrode.