CN116864542A - Super junction SBD based on reverse angle groove etching-side wall ion implantation and preparation method - Google Patents

Super junction SBD based on reverse angle groove etching-side wall ion implantation and preparation method Download PDF

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CN116864542A
CN116864542A CN202310666699.4A CN202310666699A CN116864542A CN 116864542 A CN116864542 A CN 116864542A CN 202310666699 A CN202310666699 A CN 202310666699A CN 116864542 A CN116864542 A CN 116864542A
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epitaxial layer
groove
ion implantation
trench
etching
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袁昊
雷邑平
宋庆文
康皓博
汤晓燕
张玉明
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes

Abstract

The invention relates to a super junction SBD based on reverse angle groove etching-side wall ion implantation and a preparation method thereof, wherein a super junction device structure of multilayer epitaxy and groove etching side wall ion implantation is adopted, the super junction device structure is suitable for a side wall ion implantation optimization process method of an inclined super junction device, a key process of deep groove etching is realized by utilizing a plurality of times of better shallow groove etching technology, side wall ion implantation is independently carried out on each layer of groove, doping concentrations of doped P columns and doped N columns of each epitaxial layer are matched, charge balance is realized, and the overall charge balance condition of the device is improved.

Description

Super junction SBD based on reverse angle groove etching-side wall ion implantation and preparation method
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a super junction SBD based on reverse angle trench etching-sidewall ion implantation and a preparation method thereof.
Background
SiC has excellent material characteristics such as wide forbidden bandwidth, high critical breakdown electric field, high electron saturation drift velocity, high thermal conductivity and the like as a third generation wide forbidden bandwidth semiconductor material, so that the SiC has wide application prospects in high-voltage, high-frequency and high-temperature power electronic devices. The SiC unipolar device has the advantages of high breakdown voltage, low specific on-resistance, high switching speed and low switching loss, and has made great progress through long-term research, and the device performance gradually approaches to the one-dimensional theoretical limit of the SiC unipolar device. While the constraint of how to break the one-dimensional theoretical limit, further reducing the specific on-resistance and on-loss of SiC devices is a great challenge for SiC power devices.
The schottky diode is manufactured by utilizing a metal-semiconductor junction principle formed by metal and semiconductor contact, and has smaller starting voltage. Since schottky diodes are single carrier conductive devices, there is a "silicon limit" problem between their breakdown voltage and forward on-resistance. To increase the breakdown voltage of the schottky diode, the thickness of the drift region needs to be increased and/or the doping concentration of the drift region needs to be reduced, but this necessarily results in an increase in the forward conduction voltage drop and an increase in the forward conduction loss of the schottky diode, thereby limiting the application of the schottky diode in the high voltage field.
The super junction technology is firstly applied to a power MOS device, a series of P-type doped regions and N-type doped regions which are alternately arranged are used as drift layers, PN junctions formed by the P-type doped regions and the N-type doped regions are exhausted under reverse bias, charge mutual compensation is achieved, and therefore high reverse breakdown voltage of the P-type and N-type regions can be achieved under high doping concentration, on-resistance of the P-type and N-type regions is smaller, and forward and reverse performances of a Schottky diode are simultaneously improved through the super junction.
For the silicon carbide super junction Schottky barrier diode prepared by the prior art, due to the limitation of the condition of a trench etching process, the current obtaining of a better trench etching depth is often about 6-8 mu m, a deeper trench device can not be obtained any more, and in addition, due to the existence of a trench angle in the trench etching process, the charge imbalance of the upper layer and the lower layer of the device is serious, and the performance of the whole device can be seriously influenced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a super junction SBD based on reverse angle trench etching-side wall ion implantation and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
the invention provides a super junction SBD based on reverse angle groove etching-side wall ion implantation, which comprises the following steps: the cathode, the substrate layer, the first epitaxial layer, the second epitaxial layer and the anode are sequentially stacked from bottom to top; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first epitaxial layer and the second epitaxial layer are epitaxial layers doped with a first conductivity type;
a plurality of first grooves formed by etching are formed in the first epitaxial layer at intervals, and the cross section of each first groove is isosceles trapezoid; the side wall of the first groove is provided with a first doped region;
a plurality of second grooves formed by etching are formed in the second epitaxial layer at intervals, penetrate through the second epitaxial layer and are communicated with the first grooves; the section of the second groove is isosceles trapezoid, and the second groove and the first groove are plane symmetrical along the upper surface of the first epitaxial layer; the side wall of the second groove is provided with a second doping region;
the first doped region and the second doped region are doped regions doped with a second conductivity type, the second conductivity type being different from the first conductivity type;
and insulating media are filled in the first groove and the second groove.
In one embodiment of the invention, the doping concentration of the first epitaxial layer is lower than the doping concentration of the second epitaxial layer.
In one embodiment of the invention, the doping concentration of the first doped region is lower than the doping concentration of the second doped region.
In one embodiment of the present invention, the etching depth of the first trench and the second trench is in the range of 5-10 μm.
In one embodiment of the invention, the first doped region and the second doped region have a width of 0.2-0.4 μm.
In one embodiment of the present invention, a spacing between adjacent ones of the first trenches is 3-5 μm.
In one embodiment of the invention, the first groove and the first groove which are symmetrical in plane are formed by adopting a corresponding positive angle groove etching process and a corresponding negative angle groove etching process, and the etching angle of the groove etching process ranges from 80 degrees to 85 degrees.
In one embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type; alternatively, the first conductivity type is P-type and the second conductivity type is N-type.
In one embodiment of the invention, the material of the substrate layer, the first epitaxial layer and the second epitaxial layer comprises silicon carbide; the material of the insulating medium comprises silicon dioxide.
The invention provides a preparation method of a super junction SBD based on reverse angle groove etching-side wall ion implantation, which comprises the following steps:
step 1: selecting a substrate layer, and epitaxially growing on the substrate layer to obtain a first epitaxial layer;
step 2: preparing a first mask layer on the first epitaxial layer, and etching the first mask layer and the first epitaxial layer to form a first groove;
step 3: carrying out ion implantation on the side wall of the first groove, and then carrying out high-temperature annealing activation treatment to form a first doped region;
step 4: removing the residual first mask layer, and backfilling the first groove with a groove medium by using an insulating medium;
step 5: epitaxially growing a second epitaxial layer on the first epitaxial layer;
step 6: preparing a second mask layer on the second epitaxial layer, and etching the second mask layer and the second epitaxial layer to form a second groove;
step 7: carrying out ion implantation on the side wall of the second groove, and then carrying out high-temperature annealing activation treatment to form a second doped region;
step 8: removing the remaining second mask layer, and backfilling the second trench with a trench medium by using an insulating medium;
step 9: depositing a metal layer on the back of the substrate layer, annealing to form ohmic contact, and sputtering the metal layer on the front of the second epitaxial layer to form Schottky contact with the second epitaxial layer to serve as a device cathode;
wherein the first epitaxial layer and the second epitaxial layer are epitaxial layers doped with a first conductivity type; the first doped region and the second doped region are doped regions doped with a second conductivity type, the second conductivity type being different from the first conductivity type;
the section of the first groove is isosceles trapezoid; the second groove penetrates through the second epitaxial layer and is communicated with the first groove; the section of the second groove is isosceles trapezoid, and the second groove and the first groove are plane symmetrical along the upper surface of the first epitaxial layer.
Compared with the prior art, the invention has the beneficial effects that:
1. compared with the prior silicon carbide super junction Schottky barrier diode which cannot reach deeper etching depth due to the limitation of the condition of a trench etching process, the super junction SBD based on the reverse angle trench etching-side wall ion implantation realizes the silicon carbide deep trench super junction device and meets the requirement of high withstand voltage by arranging two communicated trenches.
2. According to the super junction SBD based on the reverse angle groove etching-side wall ion implantation, two communicated grooves are arranged and are symmetrical in plane along the upper surface of the first epitaxial layer, compared with the grooves formed by single etching at the same depth, the super junction SBD is closer to a vertical structure, and the charge compensation advantage of the super junction device can be more effectively exerted.
3. According to the preparation method of the super junction SBD based on the reverse angle groove etching-side wall ion implantation, the silicon carbide deep groove is formed through two times of etching backfilling, the difficulty in deep groove backfilling caused by the traditional silicon carbide deep groove etching can be reduced in the preparation process, and the backfilling quality of a groove insulating medium can be effectively improved.
4. According to the preparation method of the super junction SBD based on the reverse angle groove etching-side wall ion implantation, the upper layer P column and the lower layer P column are formed by adopting the effects of twice etching and side wall ion implantation, and because the upper layer P column and the lower layer P column are completed based on twice independent side wall ion implantation, the concentration of the upper layer P column and the lower layer P column can be independently regulated, and the super junction charge compensation principle is better utilized to enable the device performance to be optimal.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram of a super junction SBD based on reverse angle trench etching-sidewall ion implantation according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another super junction SBD based on reverse angle trench etching-sidewall ion implantation according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a simulation structure of a super junction SBD based on reverse angle trench etching-sidewall ion implantation according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a simulation structure of another super junction SBD based on reverse angle trench etching-sidewall ion implantation according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a simulation structure of a super junction SBD based on reverse angle trench etching-sidewall ion implantation according to an embodiment of the present invention;
FIG. 6 is a graph showing a comparison of electric field distribution curves in the middle of an N column during avalanche breakdown of 3 silicon carbide superjunction SBDs according to an embodiment of the present invention;
FIG. 7 is a graph showing the comparison of I-V curves of 3 silicon carbide superjunction SBDs in forward conduction according to an embodiment of the present invention;
fig. 8 is a process flow diagram of a preparation process of a super junction SBD based on reverse angle trench etching-sidewall ion implantation according to an embodiment of the present invention.
Detailed Description
In order to further explain the technical means and effects adopted by the invention to achieve the preset aim, the invention provides a super junction SBD based on reverse angle groove etching-side wall ion implantation and a preparation method thereof, which are described in detail below with reference to the accompanying drawings and the specific embodiments.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a super junction SBD based on reverse trench etching-sidewall ion implantation according to an embodiment of the present invention, and fig. 2 is a schematic diagram of another super junction SBD based on reverse trench etching-sidewall ion implantation according to an embodiment of the present invention. As shown in the figure, the super junction SBD based on the reverse angle trench etching-sidewall ion implantation of the present embodiment includes: the cathode 108, the substrate layer 101, the first epitaxial layer 102, the second epitaxial layer 103, and the anode 107 are stacked in this order from bottom to top.
Wherein the first epitaxial layer 102 and the second epitaxial layer 103 are epitaxial layers doped with the first conductivity type; a plurality of first grooves 109 formed by etching are arranged in the first epitaxial layer 102 at intervals, and the cross section of each first groove 109 is isosceles trapezoid; the side wall of the first trench 109 is provided with a first doped region 105; a plurality of second grooves 110 formed by etching are arranged in the second epitaxial layer 103 at intervals, and the second grooves 110 penetrate through the second epitaxial layer 103 and are communicated with the first grooves 109; the cross section of the second groove 110 is isosceles trapezoid, and the second groove 110 and the first groove 109 are plane symmetrical along the upper surface of the first epitaxial layer 102; the side wall of the second trench 110 is provided with a second doped region 104; the first doped region 105 and the second doped region 104 are doped regions doped with a second conductivity type, the second conductivity type being different from the first conductivity type; the first trench 109 and the second trench 110 are filled with an insulating medium 106.
Alternatively, the first groove 109 and the second groove 110 communicate to form an hourglass-shaped groove structure having a narrow middle and wide ends as shown in fig. 1.
Alternatively, the first groove 109 and the second groove 110 communicate to form a drum-shaped groove structure having a wide middle and narrow ends as shown in fig. 2.
In an alternative embodiment, the doping concentration of the first epitaxial layer 102 is lower than the doping concentration of the second epitaxial layer 103. The doping concentration of the first doped region 105 is lower than the doping concentration of the second doped region 104.
Optionally, the first conductivity type is N-type and the second conductivity type is P-type; alternatively, the first conductivity type is P-type and the second conductivity type is N-type.
In this embodiment, the first epitaxial layer 102 has a thickness of 7-12 μm and a doping type of N-type, optionally a doping concentration of 2×10 16 -6×10 16 cm -3 . The first doped region 105 is of a P-type doping type, optionally with a doping concentration of 1.5x10 17 -3×10 17 cm -3 。
In this embodiment, the second epitaxial layer 103 has a thickness of 5-10 μm, a doping type of N-type, and optionally a doping concentration of 4X10 16 -8×10 16 cm -3 . The second doped region 104 is doped P-type, optionally with a doping concentration of 2×10 17 -6×10 17 cm -3 。
In this embodiment, the first doped region 105 and the second doped region 104 form a P-type pillar, the N-type epitaxial layer between adjacent trenches serves as an N-type pillar, and the P-type pillar and the N-type pillar are alternately arranged to form a super junction.
In an alternative embodiment, the width of the first doped region 105 and the second doped region 104 is 0.2-0.4 μm.
In an alternative embodiment, the etching depth of the first trench 109 and the second trench 110 is in the range of 5-10 μm. Optionally, the bottom of the first trench 109 is at a distance of 2-3 μm from the lower surface of the first epitaxial layer 102.
The conventional silicon carbide super junction Schottky barrier diode is limited by the condition of a groove etching process, the groove etching depth is often about 6-8 mu m, and deeper etching depth cannot be achieved.
In an alternative embodiment, the spacing between adjacent first trenches 109 is 3-5 μm, alternatively the width of the first trenches 109 is 3-5 μm, to keep the trench width as close as possible to the width of the N-pillar.
Alternatively, the first trench 109 and the second trench 110 having isosceles trapezoid cross sections are formed by a positive angle trench etching process and a negative angle trench etching process. The first trench 109 in the form of a forward isosceles trapezoid as shown in fig. 1 is etched by using a reverse angle trench etching process, and the second trench 110 in the form of a reverse isosceles trapezoid is etched by using a positive angle trench etching process, wherein the etching angle ranges from 80 ° to 85 °.
It should be noted that, in view of the limitation of the etching process conditions, the rectangular trench with the vertical structure cannot be etched, and as the etching depth increases, the trench etched by the positive angle trench etching process is closer to the inverted triangle structure. In this embodiment, the two trenches are formed in a plane symmetry along the upper surface of the first epitaxial layer, so that the advantage of charge compensation of the superjunction device can be more effectively exerted compared with the trench formed by single etching at the same depth, which is closer to a vertical structure. In an alternative embodiment, the material of the substrate layer 101, the first epitaxial layer 102 and the second epitaxial layer 103 comprises silicon carbide; the material of the insulating medium 106 comprises silicon dioxide.
Further, please refer to fig. 3-5 in combination, which are schematic diagrams of simulation structures of 3 super junction SBDs based on anti-corner trench etching-sidewall ion implantation according to an embodiment of the present invention. The dummy structure of the super junction SBD shown in fig. 3 is denoted by (a) and corresponds to the dummy structure of the SBD having the hourglass-shaped trench structure shown in fig. 1 with a narrow middle and wide ends. The dummy structure of the super junction SBD shown in fig. 4 corresponds to the dummy structure of the SBD of the drum-shaped trench structure having a wide middle and narrow ends as shown in fig. 2, and is denoted by (b). The simulated structure of the super junction SBD shown in fig. 5, corresponding to the simulated structure of the SBD of the trench structure formed by single etching-sidewall ion implantation at the same depth, is denoted as (c).
Parameters and performances of 3 simulation structures of super junction SBD based on anti-angle trench etching-sidewall ion implantation are shown in Table 1.
TABLE 1 parameters and Performance of the simulation Structure of superjunction SBD
N1(cm -3 ) P1(cm -3 ) N2(cm -3 ) P2(cm -3 ) BV(V) Ron,sp(mΩ·cm 2 ) BFOM(GW/cm 2 )
(a) 2e16 1.5e17 4e16 3e17 2000 0.99 4.03
(b) 2e16 1.5e17 4e16 2e17 1960 1.58 2.42
(c) 2e16 1.8e17 - - 2003 1.08 3.71
Referring to fig. 6 and fig. 7 in combination, fig. 6 is a graph showing a comparison of electric field distribution curves in the middle of an N column during avalanche breakdown of 3 silicon carbide superjunction SBD according to an embodiment of the present invention; FIG. 7 is a graph showing the comparison of I-V curves of 3 silicon carbide superjunction SBDs in forward conduction according to an embodiment of the present invention.
As shown in fig. 6, it can be seen that compared with the SBD of the trench structure formed by single trench etching-sidewall ion implantation of the same depth, the breakdown voltage of the super junction SBD of the two trench structures formed by two trench etching-sidewall ion implantation in this embodiment is similar.
For the super junction structure, breakdown usually occurs in the middle of the P column and the N column, the transverse electric field is uniformly distributed when the middle of the N column breaks down, and the total electric field intensity is the longitudinal electric field intensity, so the electric field in the middle of the N column is the key for researching the super junction breakdown, as can be seen from fig. 6, compared with the super junction structure device (fig. 5) manufactured by conventional one-time etching, the super junction structure device (fig. 3 and fig. 4) manufactured by adopting two times of trench etching and sidewall ion implantation maintains the breakdown voltage not to be reduced while the doping concentration of the device is improved, and the super junction structure of the embodiment can greatly improve the charge balance condition of the device and the integral performance of the device.
As shown in fig. 7, it can be seen that, compared with the SBD of the trench structure formed by single trench etching-sidewall ion implantation with the same depth, the forward direction ratio on-resistance of the SBD of the trench structure with the shape of an hourglass with narrow middle and wide ends formed by two times of trench etching-sidewall ion implantation is smaller, the power figure of merit is optimal, and the device performance is improved.
When the device is conducted in the forward direction, the anode is connected in the forward direction, current reaches the substrate through the Schottky contact and passes through the drift region (N column), only N column participates in conduction, namely the effective conduction region of the drift region becomes half compared with that of the traditional Schottky diode, so that the specific on resistance value becomes larger, the doping concentration of the N column is increased by two times compared with that of the traditional Schottky diode, namely, the doping concentration of the N column is increased by about an order of magnitude to 1 multiplied by 10 16 -1×10 17 cm -3 The forward on-resistance is reduced along with the increase of doping concentration, the super junction structures of fig. 3 and 4 adopt upper and lower layers of two-time groove etching structures, the doping concentration of an upper and lower layer drift region (N column) is the same, the super junction structure of fig. 5 is a one-time groove etching structure, the doping concentration of the drift region is the same as the lower layer of the super junction structure of fig. 3 and 4, and the overall doping is smaller than that of the super junction structure of fig. 3 and 4; the drift region (N pillar) of the super junction structure in fig. 4, i.e., the effective on region, is the smallest, and then the super junction structures in fig. 3 and 5 are the largest, so that the simulation result under the comprehensive influence is that, as shown in fig. 7, the specific on resistance value of the super junction structure in fig. 4 is the largest, and since the doping concentration of the super junction structure in fig. 3 is larger than that of the super junction structure in fig. 5, the effective on region is slightly smaller, so that the specific on resistance value of the super junction structure in fig. 3 is the smallest.
The embodiment also provides a super junction SBD based on the reverse angle groove etching-side wall ion implantation, which is used for preparing the super junction SBD based on the reverse angle groove etching-side wall ion implantation, and the preparation method comprises the following steps:
step 1: selecting a substrate layer, and epitaxially growing on the substrate layer to obtain a first epitaxial layer;
step 2: preparing a first mask layer on the first epitaxial layer, and etching the first mask layer and the first epitaxial layer to form a first groove;
step 3: carrying out ion implantation on the side wall of the first groove, and then carrying out high-temperature annealing activation treatment to form a first doped region;
step 4: removing the residual first mask layer, and backfilling the first groove with a groove medium by using an insulating medium;
step 5: epitaxially growing a second epitaxial layer on the first epitaxial layer;
step 6: preparing a second mask layer on the second epitaxial layer, and etching the second mask layer and the second epitaxial layer to form a second groove;
step 7: carrying out ion implantation on the side wall of the second groove, and then carrying out high-temperature annealing activation treatment to form a second doped region;
step 8: removing the remaining second mask layer, and backfilling the second trench with a trench medium by using an insulating medium;
step 9: depositing a metal layer on the back of the substrate layer, annealing to form ohmic contact, and sputtering the metal layer on the front of the second epitaxial layer to form Schottky contact with the second epitaxial layer to serve as a device cathode;
the first epitaxial layer and the second epitaxial layer are epitaxial layers doped with the first conductivity type; the first doped region and the second doped region are doped regions doped with a second conductivity type, and the second conductivity type is different from the first conductivity type;
the section of the first groove is isosceles trapezoid; the second groove penetrates through the second epitaxial layer and is communicated with the first groove; the section of the second groove is isosceles trapezoid, and the second groove and the first groove are plane symmetrical along the upper surface of the first epitaxial layer.
Referring to fig. 8, a process flow chart of preparing a super junction SBD based on reverse angle trench etching-sidewall ion implantation provided by an embodiment of the present invention is shown, and the preparing method of the super junction SBD based on reverse angle trench etching-sidewall ion implantation shown in fig. 1 is specifically described, including:
step a: selecting a silicon carbide substrate layer N+sub, as shown in a diagram (a) in FIG. 8;
in the embodiment, the thickness of the silicon carbide substrate layer N+sub is 1.5 μm, the doping type is N type, and the doping concentration is 5×10 18 cm -3 。
Step b: epitaxially growing an epitaxial layer Nepi1 on the silicon carbide substrate layer to form a first silicon carbide epitaxial layer; deposition of SiO by PECVD on the surface of the first silicon carbide epitaxial layer 2 A layer as a first mask layer for "trench etch-sidewall ion implantation", as shown in fig. 8 (b);
in the present embodiment, the first silicon carbide epitaxial layer has a thickness of 7 μm, a doping type of N-type, and a doping concentration of 2×10 16 cm -3 。
Step c: siO is carried out 2 Etching and SiC trench etching to form a first trench, as shown in (c) of FIG. 8;
in this embodiment, the first trench is etched by an inverse angle trench etching process, the etching depth is 5 μm, the etching width is 3 μm, the etching angle is 85 °, and the distance between the bottom of the first trench and the lower surface of the first epitaxial layer is 2 μm.
Step d: performing first time of groove side wall ion implantation to form a first doped region, performing high-temperature annealing activation treatment, and introducing Al ions to form a super junction P column of a first layer, as shown in (d) and (e) of fig. 8;
in the present embodiment, the first doped region has a doping type of P type, a doping width of 0.2 μm, and a doping concentration of 1.5X10 17 cm -3 。
Step e; removing the first mask layer by using SiO 2 Performing trench dielectric backfill as shown in fig. 8 (f);
step f: epitaxially growing an epitaxial layer Nepi2 on the first silicon carbide epitaxial layerForming a second silicon carbide epitaxial layer; deposition of SiO by PECVD on the surface of the second silicon carbide epitaxial layer 2 A layer as a second mask layer for "trench etch-sidewall ion implantation", as shown in fig. 8 (g);
in the present embodiment, the second silicon carbide epitaxial layer has a thickness of 5 μm, a doping type of N-type, and a doping concentration of 4X10 16 cm -3 。
Step g: siO is carried out 2 Etching and SiC trench etching to form a second trench, as shown in (h) diagram in FIG. 8;
in this embodiment, the second trench etching adopts a positive trench etching process, the etching depth is 5 μm, the etching width is 3 μm, and the etching angle is 85 °.
Step h: performing ion implantation on the side wall of the second groove to form a second doped region, performing high-temperature annealing activation treatment, and introducing Al ions to form a super junction P column of a second layer, as shown in (i) and (j) of fig. 8;
in the present embodiment, the second doped region has a doping type of P type, a doping width of 0.2 μm, and a doping concentration of 3×10 17 cm -3 。
Step i: removing the second mask layer by using SiO 2 Performing trench dielectric backfill as shown in (k) diagram in fig. 8;
step j: depositing metal Ni on the back surface of the silicon carbide substrate layer N+sub, and annealing to enable the Ni and the SiC substrate to form ohmic contact as a device cathode; the metal nickel Ni is sputtered on the front side of the second silicon carbide epitaxial layer, and naturally forms schottky contact with SiC as the device anode, as shown in fig. 8 (l).
It should be noted that, when preparing the super junction SBD based on the reverse angle trench etching-sidewall ion implantation as shown in fig. 2, the first trench etching adopts the positive angle trench etching process, the second trench etching adopts the reverse angle trench etching process, and the other preparation steps are identical to the preparation steps described above, and are not described herein.
According to the preparation method of the super junction SBD based on the reverse angle groove etching-side wall ion implantation, the silicon carbide deep groove is formed through two times of etching backfilling, the difficulty in deep groove backfilling caused by the traditional silicon carbide deep groove etching can be reduced in the preparation process, and the backfilling quality of a groove insulating medium can be effectively improved. And the upper and lower layer P columns are formed by adopting the effects of twice etching and side wall ion implantation, and because the upper and lower layer P columns are completed based on twice independent side wall ion implantation, the concentration of the upper and lower P columns can be independently regulated, so that the super junction charge compensation principle is better utilized to ensure that the device performance is optimal.
When the device is in the reverse state, the N column and the P column of the drift region are mutually depleted (transversely depleted), which requires that the super-junction structure should satisfy the charge balance principle, namely that the product of the impurity concentration of the N column and the impurity concentration of the P column and the corresponding width of the P column is equal, positive and negative fixed charges just offset, and the electric field distribution of the super-junction is changed into rectangular distribution due to the simultaneous existence of longitudinal Schottky contact depletion and transverse depletion, so that the breakdown voltage and the doping concentration are almost in linear relation, the breakdown voltage is reduced along with the increase of the doping concentration, and when the electric field strength exceeds the critical breakdown electric field ec=2×10 of SiC 6 V/cm, device breakdown. However, in practical situations, because the actual process is difficult to achieve charge balance, and the super junction P, N manufactured by adopting the trench etching technology is in a trapezoid shape with narrow upper part and wide lower part, charge balance is more difficult to achieve, in the implementation, compared with the problem that the charge imbalance of the upper layer and the lower layer is serious by two times of trench etching-side wall ion implantation, the concentration of the upper P column and the concentration of the lower P column can be independently adjusted to be matched with the doping concentration of the corresponding N column, and the charge compensation principle of the super junction is better utilized to enable the device performance to be optimal.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises the element. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description and to simplify the description, and is not indicative or implying that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (10)

1. A super junction SBD based on anti-corner trench etch-sidewall ion implantation, comprising: a cathode (108), a substrate layer (101), a first epitaxial layer (102), a second epitaxial layer (103) and an anode (107) which are sequentially stacked from bottom to top; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first epitaxial layer (102) and the second epitaxial layer (103) are epitaxial layers doped with a first conductivity type;
a plurality of first grooves (109) formed by etching are arranged in the first epitaxial layer (102) at intervals, and the cross section of each first groove (109) is isosceles trapezoid; the side wall of the first groove (109) is provided with a first doping region (105);
a plurality of second grooves (110) formed by etching are arranged in the second epitaxial layer (103) at intervals, and the second grooves (110) penetrate through the second epitaxial layer (103) and are communicated with the first grooves (109); the section of the second groove (110) is isosceles trapezoid, and the second groove (110) and the first groove (109) are plane symmetrical along the upper surface of the first epitaxial layer (102); the side wall of the second groove (110) is provided with a second doping region (104);
the first doped region (105) and the second doped region (104) are doped regions doped with a second conductivity type, the second conductivity type being different from the first conductivity type;
the first trench (109) and the second trench (110) are filled with an insulating medium (106).
2. The super junction SBD based on anti-corner trench etch-sidewall ion implantation according to claim 1, characterized in that the doping concentration of the first epitaxial layer (102) is lower than the doping concentration of the second epitaxial layer (103).
3. The super junction SBD based on anti-corner trench etch-sidewall ion implantation according to claim 1, characterized in that the doping concentration of the first doped region (105) is lower than the doping concentration of the second doped region (104).
4. The super junction SBD based on anti-corner trench etching-sidewall ion implantation according to claim 1, characterized in that the etching depth of the first trench (109) and the second trench (110) is in the range of 5-10 μm.
5. The super junction SBD based on anti-corner trench etch-sidewall ion implantation according to claim 1, characterized in that the width of the first doped region (105) and the second doped region (104) is 0.2-0.4 μm.
6. The super junction SBD based on anti-corner trench etch-sidewall ion implantation according to claim 1, characterized in that the spacing between adjacent first trenches (109) is 3-5 μm.
7. The super junction SBD based on anti-corner trench etching-sidewall ion implantation according to claim 1, characterized in that the first trench (109) and the first trench (109) are formed in planar symmetry using corresponding positive and negative corner trench etching processes, the etching angle of the trench etching process being in the range of 80 ° -85 °.
8. The super junction SBD based on anti-corner trench etch-sidewall ion implantation according to claim 1, wherein said first conductivity type is N-type and said second conductivity type is P-type; alternatively, the first conductivity type is P-type and the second conductivity type is N-type.
9. The super junction SBD based on anti-corner trench etch-sidewall ion implantation according to claim 1, characterized in that the material of the substrate layer (101), the first epitaxial layer (102) and the second epitaxial layer (103) comprises silicon carbide; the material of the insulating medium (106) comprises silicon dioxide.
10. The preparation method of the super junction SBD based on the reverse angle groove etching-side wall ion implantation is characterized by comprising the following steps:
step 1: selecting a substrate layer, and epitaxially growing on the substrate layer to obtain a first epitaxial layer;
step 2: preparing a first mask layer on the first epitaxial layer, and etching the first mask layer and the first epitaxial layer to form a first groove;
step 3: carrying out ion implantation on the side wall of the first groove, and then carrying out high-temperature annealing activation treatment to form a first doped region;
step 4: removing the residual first mask layer, and backfilling the first groove with a groove medium by using an insulating medium;
step 5: epitaxially growing a second epitaxial layer on the first epitaxial layer;
step 6: preparing a second mask layer on the second epitaxial layer, and etching the second mask layer and the second epitaxial layer to form a second groove;
step 7: carrying out ion implantation on the side wall of the second groove, and then carrying out high-temperature annealing activation treatment to form a second doped region;
step 8: removing the remaining second mask layer, and backfilling the second trench with a trench medium by using an insulating medium;
step 9: depositing a metal layer on the back of the substrate layer, annealing to form ohmic contact, and sputtering the metal layer on the front of the second epitaxial layer to form Schottky contact with the second epitaxial layer to serve as a device cathode;
wherein the first epitaxial layer and the second epitaxial layer are epitaxial layers doped with a first conductivity type; the first doped region and the second doped region are doped regions doped with a second conductivity type, the second conductivity type being different from the first conductivity type;
the section of the first groove is isosceles trapezoid; the second groove penetrates through the second epitaxial layer and is communicated with the first groove; the section of the second groove is isosceles trapezoid, and the second groove and the first groove are plane symmetrical along the upper surface of the first epitaxial layer.
CN202310666699.4A 2023-06-06 2023-06-06 Super junction SBD based on reverse angle groove etching-side wall ion implantation and preparation method Pending CN116864542A (en)

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