CN116864530A - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents
Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Download PDFInfo
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- CN116864530A CN116864530A CN202310872727.8A CN202310872727A CN116864530A CN 116864530 A CN116864530 A CN 116864530A CN 202310872727 A CN202310872727 A CN 202310872727A CN 116864530 A CN116864530 A CN 116864530A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
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- 229910002601 GaN Inorganic materials 0.000 description 13
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 12
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 6
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- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- -1 Titanium yttrium pentoxide Chemical compound 0.000 description 2
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 229910000892 beryllide Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
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- 239000010980 sapphire Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910021324 titanium aluminide Inorganic materials 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910020658 PbSn Inorganic materials 0.000 description 1
- 101150071746 Pbsn gene Proteins 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- SAOPTAQUONRHEV-UHFFFAOYSA-N gold zinc Chemical compound [Zn].[Au] SAOPTAQUONRHEV-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The application provides a semiconductor device, which comprises a first transistor and a second transistor. The first transistor includes a first gate, a second gate, a first drain, and a first source. The second transistor includes a second drain, a third gate and a second source. The second drain electrode is electrically connected to the first source electrode and serves as a source electrode of the semiconductor device. The third gate is electrically connected to the second gate and serves as a gate of the semiconductor device. The second source electrode is electrically connected with the first grid electrode. The first drain electrode serves as a drain electrode of the semiconductor device. Through the arrangement of the first grid electrode and the second grid electrode of the first transistor and the connection of the first grid electrode and the second source electrode of the second transistor, the floating of the grid electrode of the first transistor is eliminated, the threshold voltage of the first transistor is stabilized, and meanwhile, the first transistor is effectively prevented from being started by mistake and the increase of the overall resistance and the grid current is avoided. The threshold voltage of the overall semiconductor device may be adjusted by adjusting the threshold voltage of the second transistor.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device.
Background
Power transistors (power transistors) are widely used in household appliances, such as power supplies for electric vehicles, driving circuits for displays, and power supplies for computers. In light of the foregoing, power transistors often play an indispensable role in relation to the power supply of living goods, and development of high-quality power transistors is imperative.
Gallium nitride (GaN) materials are widely used in high frequency, high efficiency power conversion systems because of their high electron mobility, low resistance, and wide energy gap characteristics, gaN transistors exhibit excellent characteristics in power switching applications. However, in the high frequency switching process, due to the influence of parasitic inductance, a larger gate voltage oscillation is generated in the driving circuit of the device, and the threshold voltage of a commercial GaN transistor (p-GaN gate high electron mobility transistor) is smaller, so that the oscillation of the gate voltage easily causes a false turn on (false turn on) phenomenon of the device, thereby affecting the safety switching of the circuit. In order to suppress the false turn-on of the GaN device, one method is to use a normally-off silicon transistor with a relatively stable threshold voltage in cascade (cascode) with the GaN transistor, however, the cascode circuit not only introduces additional parasitic parameters, but also increases the resistance of the whole device.
Disclosure of Invention
According to the foregoing, the present application provides a semiconductor device capable of solving the problem of false turn-on of a gallium nitride transistor.
In view of the above, the present application provides a semiconductor device including a first transistor and a second transistor. The first transistor comprises a first grid electrode, a second grid electrode, a first drain electrode and a first source electrode. The second transistor comprises a second drain electrode, a third grid electrode and a second source electrode, wherein the third grid electrode is positioned between the second drain electrode and the second source electrode. The second drain electrode is electrically connected with the first source electrode and serves as a source electrode of the semiconductor device, the third gate electrode is electrically connected with the second gate electrode and serves as a gate electrode of the semiconductor device, the second source electrode is electrically connected with the first gate electrode, and the first drain electrode serves as a drain electrode of the semiconductor device.
In an embodiment of the application, the first transistor has a first substrate and the second transistor has a second substrate, the first substrate and the second substrate being provided independently of each other.
In an embodiment of the application, the first transistor and the second transistor have a common third substrate comprising a first region and a second region, the first transistor being located in the first region and the second transistor being located in the second region.
In an embodiment of the present application, the first transistor includes a channel layer, a barrier layer, a cap layer, a first gate, a second gate, a first source, and a first drain. The channel layer is disposed on the first substrate. The barrier layer is disposed on the channel layer. The cap layer is disposed on the barrier layer. The first grid electrode is arranged on the cap layer. The second grid electrode is arranged on the cap layer and is mutually isolated from the first grid electrode. The first source electrode is arranged on one side of the barrier layer. The first drain electrode is arranged on the other side of the barrier layer.
In an embodiment of the application, the first transistor further includes a buffer layer disposed between the first substrate and the channel layer.
In an embodiment of the present application, the contact between the first gate and the cap layer is an ohmic contact, and the contact between the second gate and the cap layer is a schottky contact.
In an embodiment of the present application, the semiconductor device further includes a dielectric layer between the cap layer and the first drain electrode, between the cap layer and the first source electrode, and between the first gate electrode and the second gate electrode.
In an embodiment of the present application, the second transistor includes a doped region, a gate oxide layer, a second drain, a second source, and a third gate. The doped region is disposed in the second substrate. The gate oxide layer is disposed on the doped region. The second drain electrode is arranged on one side of the doped region. The second source electrode is arranged on the other side of the doped region. The third grid electrode is arranged on the grid electrode oxide layer.
In an embodiment of the present application, the first transistor includes a channel layer, a barrier layer, a cap layer, a first gate, a second gate, a first source, and a first drain. The channel layer is disposed on the first region. The barrier layer is disposed on the channel layer. The cap layer is disposed on the barrier layer. The first grid electrode is arranged on the cap layer. The second grid electrode is arranged on the cap layer and is mutually isolated from the first grid electrode. The first source electrode is arranged on one side of the barrier layer. The first drain electrode is arranged on the other side of the barrier layer.
In an embodiment of the application, the first transistor further includes a buffer layer disposed between the first region and the channel layer.
In an embodiment of the present application, the contact between the first gate and the cap layer is an ohmic contact, and the contact between the second gate and the cap layer is a schottky contact.
In an embodiment of the present application, the semiconductor device further includes a dielectric layer between the cap layer and the first drain electrode, between the cap layer and the first source electrode, and between the first gate electrode and the second gate electrode.
In an embodiment of the present application, the second transistor includes a doped region, a gate oxide layer, a second drain, a second source, and a third gate. The doped region is disposed on the second region. The gate oxide layer is disposed on the doped region. The second drain electrode is arranged on one side of the doped region. The second source electrode is arranged on the other side of the doped region. The third grid electrode is arranged on the grid electrode oxide layer.
In an embodiment of the present application, the second transistor further includes a fourth substrate disposed between the doped region and the second region.
In an embodiment of the present application, the crystalline phase structure of silicon of the third substrate is different from that of the fourth substrate.
In an embodiment of the application, the first transistor is an enhancement transistor and the second transistor is a depletion transistor.
In an embodiment of the present application, the threshold voltage of the semiconductor device is adjusted according to the threshold voltage of the second transistor and the threshold voltage of the first transistor.
In the embodiment of the application, the number of the first grid electrodes is a plurality of the second grid electrodes, the first grid electrodes are electrically connected with each other, the second grid electrodes are electrically connected with each other, and the first grid electrodes and the second grid electrodes are isolated from each other.
In an embodiment of the present application, when the gate voltage of the semiconductor structure is less than the threshold voltage of the second transistor, the first transistor is turned off and the second transistor is turned on.
In an embodiment of the present application, when the gate voltage of the semiconductor structure is greater than the threshold voltage of the second transistor and less than the sum of the threshold voltages of the first transistor and the second transistor, the first transistor is turned off and the second transistor is turned off.
In an embodiment of the present application, when the gate voltage of the semiconductor structure is greater than the sum of the threshold voltages of the first transistor and the second transistor, the first transistor is turned on and the second transistor is turned off. In an embodiment of the present application, the second drain is connected to the first source through the first metal line, the third gate is connected to the second gate through the second metal line, and the second source is connected to the first gate through the third metal line.
In summary, the semiconductor device of the present application has the following advantages: (1) When the first transistor is turned on, through the arrangement of the first grid electrode and the second grid electrode of the first transistor and the connection of the first grid electrode and the second source electrode of the second transistor, the floating of the grid electrode of the first transistor is eliminated, so that the threshold voltage of the first transistor is stabilized, and meanwhile, the false start of the first transistor is effectively prevented, and the increase of channel resistance and grid current is not caused. (2) The threshold voltage of the overall semiconductor device may be adjusted by adjusting the threshold voltage of the second transistor.
The foregoing description is only an overview of the technical solution of the present application, and in order to make the technical means of the present application more clearly understood, the present application can be implemented according to the content of the specification, and the following detailed description of the preferred embodiments of the present application will be given with reference to the accompanying drawings.
Drawings
Fig. 1A is a schematic diagram illustrating a semiconductor device according to an embodiment of the application.
Fig. 1B is an equivalent circuit diagram of a semiconductor device according to an embodiment of the application.
Fig. 2 is a schematic diagram illustrating a semiconductor device according to another embodiment of the present application.
Fig. 3 is a schematic view illustrating a semiconductor device according to another embodiment of the present application.
Fig. 4 is a schematic view illustrating a semiconductor device according to still another embodiment of the present application.
Fig. 5 is a schematic diagram illustrating a semiconductor device according to still another embodiment of the present application.
Reference numerals illustrate:
10A: a first substrate
10B: a second substrate
10C: third substrate
10D: fourth substrate
20: channel layer
30: barrier layer
40: cap layer
50: gate oxide layer
60: dielectric layer
BF1: buffer layer
DR1: doped region
D1: first drain electrode
D2: second drain electrode
G1: first grid electrode
And G2: second grid electrode
And G3: third grid electrode
S1: first source electrode
S2: second source electrode
T1: first transistor
T2: second transistor
V D : drain voltage
V G : gate voltage
V S : source voltage
Detailed Description
Further advantages and effects of the present application will become apparent to those skilled in the art from the disclosure of the present application, which is described in the following specific examples.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments. In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, shall fall within the scope of the application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 1A and 1B, schematic diagrams of a semiconductor device according to an embodiment of the application and equivalent circuit diagrams of the semiconductor device according to an embodiment of the application are shown. As shown in fig. 1A and 1B, the semiconductor device of the present application includes a first transistor T1 and a second transistor T2. The first transistor T1 is disposed on the first substrate 10A and is a gallium nitride transistor, and the first transistor T1 includes a first gate G1, a second gate G2, a first drain D1, and a first source S1. The second transistor T2 is disposed on the second substrate 10B and includes a second drain D2, a third gate G3, and a second source S2, wherein the third gate G3 is located between the second drain D2 and the second source S2, and the second drain D2 is electrically connected to the first source S1 and is used as a source of the semiconductor device; the third gate G3 is electrically connected with the second gate G2 and serves as a gate of the semiconductor device; the second source electrode S2 is electrically connected with the first grid electrode G1; the first drain D1 serves as the drain of the semiconductor device.
Further, the second drain D2 is connected to the first source S1 through the first metal line M1, the third gate G3 is connected to the second gate G2 through the second metal line M2, and the second source S2 is connected to the first gate G1 through the third metal line M3.
In this embodiment, the first transistor has a first substrate 10A, the second transistor has a second substrate 10B, and the first substrate 10A and the second substrate 10B are provided independently of each other; in other words, the first transistor T1 and the second transistor T2 are two discrete devices. The first substrate 10A may be a silicon substrate, a sapphire (sapphire) substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a Silicon On Insulator (SOI) substrate, and the second substrate 10B may be a silicon or SiC or SOI substrate.
In the present embodiment, the first transistor T1 is an enhancement transistor and is of a first conductivity type (i.e., N-type); the second transistor T2 is a depletion transistor and is of a second conductivity type (i.e., P-type), and the second transistor T2 is a silicon (Si) transistor or a silicon carbide (SiC) transistor.
As for the first transistor T1, the first transistor T1 includes a channel layer 20, a barrier layer 30, and a cap layer 40. The channel layer 20 is disposed on the first substrate 10A, and a material of the channel layer 20 includes gallium nitride (GaN). The barrier layer 30 is disposed on the channel layer 20, and a material of the barrier layer 30 includes aluminum gallium nitride (AlGaN). The cap layer 40 is disposed on the barrier layer 30. The first gate G1 is disposed on the cap layer 40. The second gate G2 is disposed on the cap layer 40 and isolated from the first gate G1. The first drain electrode D1 is disposed on one side of the barrier layer 30 and on one side of the cap layer 40. The first source S1 is disposed on the other side of the barrier layer 30 and on the other side of the cap layer 40.
In this embodiment, the first transistor T1 further includes a buffer layer BF1. The buffer layer BF1 is disposed between the first substrate 10A and the channel layer 20 to reduce the degree of lattice mismatch of the first substrate 10A. In other words, the channel layer 20 is disposed on the buffer layer BF1.
Specifically, the channel layer 20 provides electrons, the barrier layer 30 covers the entire channel layer 20, and the energy gap of the barrier layer 30 is higher than that of the channel layer 20, so that a heterostructure is formed at the interface of the barrier layer 30 and the channel layer 20. The cap layer 40 partially covers the barrier layer 30 and may be a P-type gallium nitride layer or a semiconductor layer, the cap layer 40 being located between the first gate G1 and the barrier layer 30 and also between the second gate G2 and the barrier layer 30; the threshold voltage of the first transistor T1 is increased by the configuration of the cap layer 40. The first gate G1 is spaced apart from the second gate G2 by a distance, the first gate G1 is in ohmic contact with the cap layer 40, and the second gate G2 is in schottky contact with the cap layer 40. The first drain D1 contacts the barrier layer 30 and is located at one side (e.g., right side) of the cap layer 40 at a first distance from the cap layer 40. The first source S1 contacts the barrier layer 30 and is located at the other side (e.g., left side) of the cap layer 40 and is spaced apart from the cap layer 40 by a second distance, and the value of the first distance may be the same as or different from the value of the second distance. In other words, the first drain electrode D1 and the first source electrode S1 are located at opposite sides of the cap layer 40.
For the second transistor T2, taking a silicon (Si) transistor as an example, the second transistor includes a doped region DR1, a gate oxide 50, a second drain D2, a second source S2, and a third gate G3. The doped region DR1 is disposed in the second substrate 10B. The gate oxide layer 50 is disposed on the doped region DR 1. The second drain D2 is disposed on one side of the doped region DR 1. The second source S2 is disposed on the other side of the doped region DR 1. The third gate G3 is disposed on the gate oxide layer 50.
The doped region DR1 is formed in the second substrate 10B, and the conductivity type of the doped region DR1 is the second conductivity type. The third gate G3 is disposed on the second substrate 10B, and a gate oxide layer 50 is disposed between the third gate G3 and the second substrate 10B. The second drain electrode D2 is located at one side (e.g., left side) of the third gate electrode G3 and on the second substrate 10B, and the second source electrode S2 is located at the other side (e.g., right side) of the third gate electrode G3 and on the second substrate 10B; in other words, the second drain D2 and the second source S2 are disposed on opposite sides of the third gate G3.
The material of the semiconductor layer may include N-type gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or a combination thereof. The materials of the first gate G1, the second gate G2, the first drain D1, the first source S1, the second drain D2, the third gate G3, the second source S2, the first metal line M1, the second metal line M2 and the third metal line M3 may include titanium nitride (TiN), nitrogenTantalum (TaN), aluminum (Al), titanium aluminide (TiAL), indium (In), tin (Sn), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), gold beryllide (AuBe), germanium beryllide (BeGe), nickel (Ni), lead tin (PbSn), chromium (Cr), gold zinc (AuZn), titanium (Ti), tungsten (W), titanium Tungsten (TiW), or alloys thereof. The material of the gate oxide layer 50 may include silicon oxide (SiO x ) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), aluminum oxide (AlO) x ) Hafnium oxide (HfO) 2 ) Silicon oxynitride (SiOCN), yttrium oxide (Y) 2 O 3 ) Titanium yttrium pentoxide (Y) 2 TiO 5 ) Ytterbium trioxide (Yb) 2 O 3 ) Zirconium dioxide (ZrO) 2 ) Titanium dioxide (TiO) 2 ) Tantalum pentoxide (Ta) 2 O 5 ) Or a combination thereof. The materials of the semiconductor layer, the first gate electrode G1, the second gate electrode G2, the first drain electrode D1, the first source electrode S1, the second drain electrode D2, the third gate electrode G3, the second source electrode S2, the first metal line M1, the second metal line M2, and the third metal line M3 are only examples, and are not intended to limit the present application.
The first drain D1 receives a drain voltage V D The first source S1 and the second drain D2 receive a source voltage V S The first gate G1 is connected to the second source S2, and the second gate G2 and the third gate G3 receive the gate voltage V G . Through the connection between the first gate G1 and the second source S2, the floating gate of the first transistor T1 is eliminated, so as to stabilize the threshold voltage of the first transistor T1. Although ohmic contact is formed between the first gate electrode G1 and the cap layer 40, the first gate electrode G1 and the second source electrode S2 are connected without an increase in gate current.
When the gate voltage V G When the threshold voltage of the second transistor T2 is smaller than the threshold voltage of the first transistor T1, the second transistor T2 is turned off, and the first gate G1 is connected with the second source S2 due to the connection of the first gate G1 and the second source S2, so that the first transistor T1 is prevented from being turned on by mistake. At this time, the ohmic contact between the first gate electrode G1 and the cap layer 40 and the connection between the first gate electrode G1 and the second source electrode S2 equalize the voltage of the cap layer 40 and the voltage of the second source electrode S2, thereby eliminating the floating of the cap layer 40, and thus improving the first crystalStability of threshold voltage of the tube T1.
When the gate voltage V G When the threshold voltage of the second transistor T2 is larger than the sum of the threshold voltages of the first transistor T1 and the second transistor T2, the first transistor T1 is turned off, the second transistor T2 is turned off, and the gate voltage V is smaller than the sum of the threshold voltages of the first transistor T1 and the second transistor T2 G Received by the second gate G2. The voltage of the second gate G2 follows the gate voltage V G And thus causes the voltage of the cap layer 40 to rise. Since the ohmic contact of the first gate electrode G1 and the cap layer 40, that is, the voltage of the first gate electrode G1 is equal to the voltage of the cap layer 40, the voltage of the first gate electrode G1 also rises.
When the gate voltage V G When the threshold voltage of the first transistor T1 and the threshold voltage of the second transistor T2 are larger than the sum, the first transistor T1 is turned on, the second transistor T2 is turned off, and the gate voltage V G Can be used to regulate the voltage of cap layer 40, the voltage of cap layer 40 follows the voltage V of the gate G Is increased by the increase of the number of the barrier layers 30, and the channel layer 20, two-dimensional electron gas (two-dimensional electron gas,2 DEG) is generated at the boundary thereof. Due to partial gate voltage V G For turning off the second transistor T2, the threshold voltage of the first transistor T1 can be expressed as: v (V) th ＝V th(p-FET) +V th,p-GaN Wherein V is th Is the threshold voltage of the semiconductor device, V th(p-FET) Is the threshold voltage of the second transistor T2, V th,p-GaN Is the threshold voltage of the first transistor T1. In other words, the threshold voltage of the semiconductor device is the sum of the threshold voltage of the first transistor T1 and the threshold voltage of the second transistor T2, and thus the threshold voltage of the semiconductor device is adjusted according to the threshold voltage of the second transistor T2 and the threshold voltage of the first transistor T1. Further, when the threshold voltage of the first transistor T1 is a fixed value, the threshold voltage of the entire semiconductor device is adjusted according to the threshold voltage of the second transistor T2, i.e. the threshold voltage of the semiconductor device can be adjusted by adjusting the threshold voltage of the second transistor T2.
In addition, the semiconductor device shown in fig. 1A is packaged to become a complete power device, and the power amplifier circuit, the voltage stabilizer, the charger and the like can be applied.
Referring to fig. 2, a schematic diagram of a semiconductor device according to another embodiment of the application is shown. As shown in fig. 2, the semiconductor device of the present application includes the first transistor T1 and the second transistor T2, and the configuration relationship of the first transistor T1 and the second transistor T2 is described in the embodiment shown in fig. 1A and 1B, but the embodiment shown in fig. 2 still has differences from the embodiment shown in fig. 1: the first transistor T1 and the second transistor T2 further comprise a dielectric layer 60.
The dielectric layer 60 is disposed between the cap layer 40 and the first drain D1, between the cap layer 40 and the first source S1, and between the first gate G1 and the second gate G2, so that the first drain D1, the first source S1, the first gate G1, and the second gate G2 are electrically isolated from each other. The dielectric layer 60 is also disposed between the third gate electrode G3 and the second drain electrode D2, between the third gate electrode G3 and the second source electrode S2, and on the second substrate 10B, so that the second drain electrode D2, the second source electrode S2, and the third gate electrode G3 are electrically isolated from each other.
The material of dielectric layer 60 may include silicon oxide (SiO) x ) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), aluminum oxide (AlOx), hafnium oxide (HfO) 2 ) Silicon nitride (SiN) x ) Silicon carbonitride boride (SiBN), silicon carbonitride (SiCN), silicon carbonitride oxide (SiOCN), yttrium oxide (Y) 2 O 3 ) Titanium yttrium pentoxide (Y) 2 TiO 5 ) Ytterbium trioxide (Yb) 2 O 3 ) Zirconium dioxide (ZrO) 2 ) Titanium dioxide (TiO) 2 ) Tantalum pentoxide (Ta) 2 O 5 ) Or a combination thereof. The materials of the dielectric layer 60 are only exemplified and are not intended to limit the present application.
Referring to fig. 3, a schematic diagram of a semiconductor device according to another embodiment of the application is shown. As shown in fig. 3, the semiconductor device of the present application includes the first transistor T1 and the second transistor T2, and the configuration relationship of the first transistor T1 and the second transistor T2 is described in the embodiment shown in fig. 1A and 1B, but the embodiment shown in fig. 3 still has differences from the embodiment shown in fig. 1: the number of the first gates G1 is plural, and the number of the second gates G2 is plural. The first gates G1 are electrically connected to each other, the second gates G2 are electrically connected to each other, and the first gates G1 are isolated from the second gates G2.
For example, the number of the first gates G1 is two, and the number of the second gates G2 is two. The single first gate G1 and the single second gate G2 are spaced apart from each other by a space, and the single first gate G1 is located between the two second gates G2, i.e., the single second gate G2 is located between the two first gates G1. The two first gates G1 are connected to the second source S2, and the two second gates G2 are connected to the third gate G3. Further, the two first gates G1 are connected to each other first and then to the second source S2, and the two second gates G2 are connected to each other first and then to the third gate G3. G1 and G2 are arranged along the gate width direction without increasing the length of the cap layer 40, so that the channel resistance of the semiconductor device is not increased. The number and configuration of the first gate G1 and the second gate G2 are merely illustrative, and are not intended to limit the present application.
Referring to fig. 4, a schematic diagram of a semiconductor device according to still another embodiment of the application is shown. As shown in fig. 4, the semiconductor device of the present application includes the first transistor T1 and the second transistor T2, and the configuration relationship of the first transistor T1 and the second transistor T2 is described in the embodiment shown in fig. 1A and 1B, but the embodiment shown in fig. 4 still has differences from the embodiment shown in fig. 1: the first transistor T1 and the second transistor T2 have a common third substrate 10C.
The third substrate 10C includes a first region in which the first transistor T1 is located and a second region in which the second transistor T2 is located, and the first region and the second region may be adjacent to each other or disposed at a distance from each other. Accordingly, the buffer layer BF1 of the first transistor T1 is disposed on the first region, and the doped region DR1 of the second transistor T2 is disposed on the second region. The third substrate 10C may be a silicon or SiC or SOI substrate.
Referring to fig. 5, a schematic diagram of a semiconductor device according to still another embodiment of the application is shown. As shown in fig. 5, the semiconductor device of the present application includes the first transistor T1 and the second transistor T2, and the configuration relationship of the first transistor T1 and the second transistor T2 has been described in the embodiment shown in fig. 4, but the embodiment shown in fig. 5 still has differences from the embodiment shown in fig. 4: the first transistor T1 and the second transistor T2 further comprise a dielectric layer 60, and the second transistor T2 further comprises a fourth substrate 10D.
The dielectric layer 60 is disposed between the cap layer 40 and the first drain D1, between the cap layer 40 and the first source S1, and between the first gate G1 and the second gate G2, so that the first drain D1, the first source S1, the first gate G1, and the second gate G2 are electrically isolated from each other. The dielectric layer 60 is also disposed between the third gate electrode G3 and the second drain electrode D2, between the third gate electrode G3 and the second source electrode S2, and on the fourth substrate 10D, so that the second drain electrode D2, the second source electrode S2, and the third gate electrode G3 are electrically isolated from each other.
The fourth substrate 10D is disposed between the doped region DR1 and the second region, and the doped region DR1 is disposed in the fourth substrate 10D. For example, the third substrate 10C and the fourth substrate 10D are both silicon substrates, and the silicon crystal phase structure (e.g., silicon (111)) of the third substrate 10C is different from the silicon crystal phase structure (e.g., silicon (100)) of the fourth substrate.
In summary, the semiconductor device of the present application has the following advantages: (1) When the first transistor is turned on, through the arrangement of the first grid electrode and the second grid electrode of the first transistor and the connection of the first grid electrode and the second source electrode of the second transistor, the floating of the grid electrode of the first transistor is eliminated, so that the threshold voltage of the first transistor is stabilized, and meanwhile, the first transistor is effectively prevented from being turned on by mistake and the increase of the overall resistance and the grid current is avoided. (2) The threshold voltage of the overall semiconductor device may be adjusted by adjusting the threshold voltage of the second transistor.
Claims (22)
1. A semiconductor device, comprising:
a first transistor including a first gate, a second gate, a first drain, and a first source; and
a second transistor including a second drain, a third gate and a second source, the third gate being located between the second drain and the second source;
the second drain electrode is electrically connected with the first source electrode and serves as a source electrode of the semiconductor device, the third gate electrode is electrically connected with the second gate electrode and serves as a gate electrode of the semiconductor device, the second source electrode is electrically connected with the first gate electrode, and the first drain electrode serves as a drain electrode of the semiconductor device.
2. The semiconductor device according to claim 1, wherein the first transistor has a first substrate, wherein the second transistor has a second substrate, and wherein the first substrate and the second substrate are provided independently of each other.
3. The semiconductor device according to claim 1, wherein the first transistor and the second transistor have a common third substrate, the third substrate including a first region in which the first transistor is located and a second region in which the second transistor is located.
4. The semiconductor device according to claim 2, wherein the first transistor includes:
a channel layer disposed on the first substrate;
a barrier layer disposed on the channel layer;
a cap layer disposed on the barrier layer;
the first grid electrode is arranged on the cap layer;
the second grid electrode is arranged on the cap layer and is isolated from the first grid electrode;
a first source electrode arranged on one side of the barrier layer; and
and the first drain electrode is arranged on the other side of the barrier layer.
5. The semiconductor device according to claim 4, wherein the first transistor further comprises:
and the buffer layer is arranged between the first substrate and the channel layer.
6. The semiconductor device according to claim 4 or 5, wherein the first gate is in ohmic contact with the cap layer and the second gate is in schottky contact with the cap layer.
7. The semiconductor device according to claim 4 or 5, further comprising a dielectric layer between the cap layer and the first drain, between the cap layer and the first source, and between the first gate and the second gate.
8. The semiconductor device according to claim 2, wherein the second transistor includes:
the doped region is arranged in the second substrate;
the grid electrode oxide layer is arranged on the doped region;
the second drain electrode is arranged on one side of the doped region;
the second source electrode is arranged on the other side of the doped region; and
and the third grid electrode is arranged on the grid electrode oxide layer.
9. The semiconductor device according to claim 3, wherein the first transistor comprises:
a channel layer disposed on the first region;
a barrier layer disposed on the channel layer;
a cap layer disposed on the barrier layer;
the first grid electrode is arranged on the cap layer;
the second grid electrode is arranged on the cap layer and is isolated from the first grid electrode;
a first source electrode arranged on one side of the barrier layer; and
and the first drain electrode is arranged on the other side of the barrier layer.
10. The semiconductor device according to claim 9, wherein the first transistor further comprises:
and the buffer layer is arranged between the first region and the channel layer.
11. The semiconductor device of claim 9 or 10, wherein the first gate is in ohmic contact with the cap layer and the second gate is in schottky contact with the cap layer.
12. The semiconductor device according to claim 9 or 10, further comprising a dielectric layer between the cap layer and the first drain, between the cap layer and the first source, and between the first gate and the second gate.
13. The semiconductor device according to claim 3, wherein the second transistor comprises:
the doped region is arranged on the second region;
the grid electrode oxide layer is arranged on the doped region;
the second drain electrode is arranged on one side of the doped region;
the second source electrode is arranged on the other side of the doped region; and
and the third grid electrode is arranged on the grid electrode oxide layer.
14. The semiconductor device according to claim 13, wherein the second transistor further comprises:
and the fourth substrate is arranged between the doped region and the second region.
15. The semiconductor device according to claim 14, wherein a crystal phase structure of silicon of the third substrate is different from that of the fourth substrate.
16. The semiconductor device according to claim 1, wherein the first transistor is an enhancement transistor and the second transistor is a depletion transistor.
17. The semiconductor device according to claim 1, wherein a threshold voltage of the semiconductor device is adjusted according to a threshold voltage of the second transistor and a threshold voltage of the first transistor.
18. The semiconductor device according to claim 1, wherein the number of the first gates is plural, the number of the second gates is plural, the plural first gates are electrically connected to each other, the plural second gates are electrically connected to each other, and the plural first gates and the plural second gates are isolated from each other.
19. The semiconductor device of claim 1, wherein the first transistor is turned off and the second transistor is turned on when a gate voltage of the semiconductor structure is less than a threshold voltage of the second transistor.
20. The semiconductor device of claim 1, wherein the first transistor is turned off and the second transistor is turned off when a gate voltage of the semiconductor structure is greater than a threshold voltage of the second transistor and less than a sum of a first transistor and a second transistor threshold voltage.
21. The semiconductor device of claim 1, wherein the first transistor is turned on and the second transistor is turned off when a gate voltage of the semiconductor structure is greater than a sum of first transistor and second transistor threshold voltages.
22. The semiconductor device according to claim 1, wherein the second drain is connected to the first source via a first metal line, the third gate is connected to the second gate via a second metal line, and the second source is connected to the first gate via a third metal line.
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