JP5369434B2 - Bidirectional switch - Google Patents

Bidirectional switch Download PDF

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JP5369434B2
JP5369434B2 JP2007330690A JP2007330690A JP5369434B2 JP 5369434 B2 JP5369434 B2 JP 5369434B2 JP 2007330690 A JP2007330690 A JP 2007330690A JP 2007330690 A JP2007330690 A JP 2007330690A JP 5369434 B2 JP5369434 B2 JP 5369434B2
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bidirectional switch
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JP2009152479A (en
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修 町田
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Sanken Electric Co Ltd
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    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
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Description

本発明は、マトリックスコンバータ、交流電源回路等の電気回路に使用するための交流スイッチ即ち双方向スイッチに関する。 The present invention relates to an AC switch, that is, a bidirectional switch, for use in an electric circuit such as a matrix converter or an AC power supply circuit.

交流電流をオン・オフすることができる双方向スイッチ（交流スイッチ）としてトライアック即ち双方向性３端子サイリスタが知られている。しかし、トライアックは、ここに流れる電流が保持電流以下になるまでオン状態を継続する特性を有しているので、任意の時点でオフにできない。従って、任意の時点で電流をオフにすることが要求される時には、例えば、図１に示すように第１及び第２の主端子１、２間に互いに逆の方向性を有して直列に接続された第１及び第２のＩＧＢＴ即ち絶縁ゲート・バイポーラ・トランジスタＱ1、Ｑ2と、第１及び第２の絶縁ゲート・バイポーラ・トランジスタＱ1、Ｑ2に対して逆の方向性を有して並列接続された第１及び第２のダイオードＤ1、Ｄ2との組み合わせによって双方向スイッチ回路（双方向スイッチ）を構成した。なお、図１の第１及び第２の絶縁ゲート・バイポーラ・トランジスタＱ1、Ｑ2を、絶縁ゲート型又は接合型電界効果トランジスタ、又はバイポーラ・トランジスタに置き換えて双方向スイッチを構成すること、又は２つの絶縁ゲート・バイポーラ・トランジスタ（ＩＧＢＴ）を互いに逆の方向性を有して並列接続して双方向スイッチを構成することもできる。図１及びこれに類似の双方向スイッチはノーマリオフ型の複数の半導体スイッチング素子を使用して構成される。図１のように複数の半導体スイッチング素子を組み合せた双方向スイッチは、回路構成が複雑になり、且つオン電圧及びオン抵抗が比較的高くなるという欠点を有する。また、図１及びこれに類似の双方向スイッチは、バンドギャップが比較的小さいシリコン半導体で形成されているので、高耐圧化が困難であるという欠点を有する。 A triac or bidirectional three-terminal thyristor is known as a bidirectional switch (AC switch) capable of turning on and off an alternating current. However, since the triac has a characteristic of continuing the on state until the current flowing here becomes equal to or lower than the holding current, it cannot be turned off at any time. Therefore, when it is required to turn off the current at an arbitrary time, for example, as shown in FIG. 1, the first and second main terminals 1 and 2 are connected in series with opposite directions. The connected first and second IGBTs or insulated gate bipolar transistors Q1, Q2 and the first and second insulated gate bipolar transistors Q1, Q2 are connected in parallel with opposite directions. A bidirectional switch circuit (bidirectional switch) was configured by a combination of the first and second diodes D1 and D2. It should be noted that the first and second insulated gate bipolar transistors Q1 and Q2 in FIG. 1 may be replaced with insulated gate or junction field effect transistors or bipolar transistors to form a bidirectional switch, or two It is also possible to configure a bidirectional switch by connecting insulated gate bipolar transistors (IGBTs) in parallel with opposite directions. The bidirectional switch similar to FIG. 1 is configured using a plurality of normally-off type semiconductor switching elements. The bidirectional switch in which a plurality of semiconductor switching elements are combined as shown in FIG. 1 has the disadvantage that the circuit configuration is complicated and the on-voltage and on-resistance are relatively high. In addition, since the bidirectional switch similar to FIG. 1 is formed of a silicon semiconductor having a relatively small band gap, it has a drawback that it is difficult to increase the breakdown voltage.

図１の双方向スイッチ及びこれに類似の双方向スイッチの問題点を解決するための双方向スイッチがＷＯ２００４／１１４５０８号公報（特許文献１）に開示されている。この特許文献１に従う双方向スイッチＳＷは、図２に示すように第１及び第２の主端子１、２とゲート端子３と、第１及び第２の主端子１、２間に接続された化合物半導体から成るノーマリオン型主半導体スイッチング素子（例えばＨＥＭＴ）Ｑと、第１の主端子１にカソードが接続された第１のダイオードＤ1と、第２の主端子２にカソードが接続された第２のダイオードＤ2と、第１及び第２のダイオードＤ1、Ｄ2のアノードを相互に接続する共通導体４とを有している。この双方向スイッチを使用する時には、例えば、第１及び第２の主端子１、２に例えば交流電源６と負荷７とを含む電気回路５を接続し、ゲート端子３と共通導体４との間にゲート制御回路８を接続する。図２の双方向スイッチＳＷにおいて、第１の主端子１の電位が第２の主端子２の電位よりも高く且つゲート端子３の電位が共通導体４に対して負の時には、ノーマリオン型の主半導体スイッチング素子Ｑがオフになり、双方向スイッチＳＷもオフになる。双方向スイッチＳＷはゲートを中心にして対称的に形成されているので、第２の主端子２の電位が第１の主端子１の電位よりも高く且つゲート端子３の電位が共通導体４に対して負の時にも、主半導体スイッチング素子Ｑがオフになり、双方向スイッチＳＷもオフになる。ゲート端子３の電位を、共通導体４を基準にして主半導体スイッチング素子Ｑのしきい値以上の値（例えば零又は正電位）にした時には、主半導体スイッチング素子Ｑがオンになり、双方向スイッチＳＷもオンになる。 A bidirectional switch for solving the problems of the bidirectional switch of FIG. 1 and a similar bidirectional switch is disclosed in WO 2004/114508 (Patent Document 1). As shown in FIG. 2, the bidirectional switch SW according to Patent Document 1 is connected between the first and second main terminals 1, 2 and the gate terminal 3, and between the first and second main terminals 1, 2. A normally-on main semiconductor switching element (eg, HEMT) Q made of a compound semiconductor, a first diode D1 having a cathode connected to the first main terminal 1, and a first diode having a cathode connected to the second main terminal 2. Two diodes D2 and a common conductor 4 for connecting the anodes of the first and second diodes D1 and D2 to each other. When this bidirectional switch is used, for example, an electric circuit 5 including, for example, an AC power source 6 and a load 7 is connected to the first and second main terminals 1 and 2, and between the gate terminal 3 and the common conductor 4. The gate control circuit 8 is connected to. In the bidirectional switch SW of FIG. 2, when the potential of the first main terminal 1 is higher than the potential of the second main terminal 2 and the potential of the gate terminal 3 is negative with respect to the common conductor 4, the normally-on type The main semiconductor switching element Q is turned off, and the bidirectional switch SW is also turned off. Since the bidirectional switch SW is formed symmetrically around the gate, the potential of the second main terminal 2 is higher than the potential of the first main terminal 1 and the potential of the gate terminal 3 is connected to the common conductor 4. On the other hand, even when negative, the main semiconductor switching element Q is turned off and the bidirectional switch SW is also turned off. When the potential of the gate terminal 3 is set to a value (for example, zero or positive potential) equal to or higher than the threshold value of the main semiconductor switching element Q with respect to the common conductor 4, the main semiconductor switching element Q is turned on, and the bidirectional switch SW also turns on.

図２の双方向スイッチＳＷは少ない部品点数で構成できるという利点、及び主半導体スイッチング素子Ｑを窒化物半導体等の化合物半導体で構成することによって高耐圧化ができるという利点を有する。しかし、図２の双方向スイッチＳＷは主半導体スイッチング素子Ｑと、第１及び第２のダイオードＤ1、Ｄ2とが個別部品として構成されているので、大型且つコスト高になるという欠点、及びゲート端子を制御するための基準電位を簡単な構成で安定的に得ることが困難であるという欠点を有する。
ＷＯ ２００４／１１４５０８公開公報 The bidirectional switch SW of FIG. 2 has an advantage that it can be configured with a small number of parts, and an advantage that a high breakdown voltage can be achieved by configuring the main semiconductor switching element Q with a compound semiconductor such as a nitride semiconductor. However, since the bidirectional switch SW of FIG. 2 includes the main semiconductor switching element Q and the first and second diodes D1 and D2 as separate components, it is disadvantageous in that it is large and expensive, and the gate terminal. It is difficult to stably obtain a reference potential for controlling the above with a simple configuration.
WO 2004/114508 Publication

従って、本発明が解決しようとする課題は、双方向スイッチの小型化及び低コスト化が要求されていることであり、本発明の目的はこの要求に応えることができる双方向スイッチを提供することにある。本発明の別の目的はこの要求に応えることができ且つ基準電位を安定化することができる双方向スイッチを提供することにある。   Accordingly, the problem to be solved by the present invention is that the bidirectional switch is required to be reduced in size and cost, and the object of the present invention is to provide a bidirectional switch that can meet this requirement. It is in. Another object of the present invention is to provide a bidirectional switch capable of meeting this requirement and stabilizing the reference potential.

上記課題を解決するための本発明は、
導電性基板と、
前記導電性基板上に配置され、且つ第１の主面と該第１の主面に対向する第２の主面とを有し、且つ電流通路を形成するための少なくとも１つの半導体層を有し、前記第２の主面が前記導電性基板に電気的に結合されている主半導体領域と、
所定の間隔を有して前記主半導体領域の前記第１の主面上にそれぞれ配置され且つ前記主半導体領域の前記第１の主面にそれぞれオーミック接触している第１及び第２の主電極と、
前記主半導体領域の前記第１及び第２の主電極間部分を流れる電流を制御するために前記主半導体領域の前記第１の主面の前記第１及び第２の主電極の間に配置されたゲート手段（例えばショットキーゲート又は絶縁ゲート又はｐｎ接合ゲート）と、
前記主半導体領域の前記第１の主面の前記第１の主電極を基準にして前記ゲート手段と反対側の位置に配置されており且つダイオードのアノードとしての機能を有している第１のダイオード形成用電極と、
前記主半導体領域の前記第１の主面の前記第２の主電極を基準にして前記ゲート手段と反対側の位置に配置されており且つダイオードのアノードとしての機能を有している第２のダイオード形成用電極と、
前記第１のダイオード形成用電極と前記第２のダイオード形成用電極とを相互に電気的に接続している接続手段と、
を備え、前記導電性基板は前記接続手段に電気的に結合されていることを特徴とする双方向スイッチに係わるものである。
The present invention for solving the above problems is as follows.
A conductive substrate ;
A first main surface and a second main surface opposite to the first main surface are disposed on the conductive substrate and have at least one semiconductor layer for forming a current path. A main semiconductor region in which the second main surface is electrically coupled to the conductive substrate ;
First and second main electrodes arranged on the first main surface of the main semiconductor region with a predetermined interval and in ohmic contact with the first main surface of the main semiconductor region, respectively. When,
Disposed between the first and second main electrodes of the first main surface of the main semiconductor region in order to control a current flowing through the portion between the first and second main electrodes of the main semiconductor region. Gate means (eg, Schottky gate or insulated gate or pn junction gate);
The first semiconductor layer is disposed at a position opposite to the gate means with respect to the first main electrode on the first main surface of the main semiconductor region, and has a function as an anode of a diode . A diode forming electrode;
The second semiconductor element is disposed at a position opposite to the gate means with respect to the second main electrode on the first main surface of the main semiconductor region and has a function as an anode of a diode . A diode forming electrode;
And connection means are electrically connected to each other and said first diode forming electrode and the second diode-forming electrodes,
And the conductive substrate is electrically coupled to the connecting means.

なお、請求項２に示すように、更に、前記ゲート手段と前記接続手段との間に接続されたスイッチ制御回路を備えていることが望ましい。
また、請求項３に示すように、前記主半導体領域は２次元キャリアガス層を生じさせることができる第１及び第２の半導体層を有していることが望ましい。
また、請求項４に示すように、前記主半導体領域は電流通路として機能する第１導電型半導体層を有していることが望ましい。
また、請求項５に示すように、前記ゲート手段は、前記主半導体領域の前記第１の主面にショットキー接触しているゲート電極であることが望ましい。
また、請求項６に示すように、前記ゲート手段は、前記主半導体領域の前記第１の主面上に配置されたゲート絶縁膜と該ゲート絶縁膜上に配置されたゲート電極とから成ることが望ましい。
また、請求項７に示すように、前記第１及び第２のダイオード形成用電極は、前記主半導体領域の前記第１の主面にショットキー接触している電極であることが望ましい。
また、請求項８に示すように、前記主半導体領域は、更にｐｎ接合を得るために前記第１及び第２のダイオード形成用電極と前記第１導電型半導体層との間に第１及び第２の第２導電型半導体層を有し、前記第１及び第２のダイオード形成用電極は前記第１及び第２の第２導電型半導体層にオーミック接触した電極であることが望ましい。
また、請求項９に示すように、前記接続手段は、前記半導体領域の前記第２の主面に電気的及び機械的に結合された一方の主面と該一方の主面に対向する他方の主面とを有する導電性基板と、前記導電性基板の前記他方の主面に形成された補助電極と、前記第１のダイオード形成用電極を前記導電性基板に電気的に接続する導体と、前記第２のダイオード形成用電極を前記導電性基板に電気的に接続する導体とから成ることが望ましい。
According to a second aspect of the present invention, it is preferable that a switch control circuit connected between the gate means and the connection means is further provided.
According to a third aspect of the present invention, the main semiconductor region preferably includes first and second semiconductor layers capable of generating a two-dimensional carrier gas layer.
According to a fourth aspect of the present invention, it is desirable that the main semiconductor region has a first conductivity type semiconductor layer that functions as a current path.
The gate means is preferably a gate electrode in Schottky contact with the first main surface of the main semiconductor region.
The gate means may comprise a gate insulating film disposed on the first main surface of the main semiconductor region and a gate electrode disposed on the gate insulating film. Is desirable.
According to a seventh aspect of the present invention, the first and second diode forming electrodes are preferably electrodes that are in Schottky contact with the first main surface of the main semiconductor region.
In addition, as described in claim 8, the main semiconductor region further includes a first and a second diode between the first and second diode forming electrodes and the first conductivity type semiconductor layer in order to obtain a pn junction. a second conductivity type semiconductor layer 2, the first and second diode-forming electrodes is arbitrary desired that an electrode which is in ohmic contact with the first and second second conductivity type semiconductor layer.
According to a ninth aspect of the present invention, the connecting means includes one main surface electrically and mechanically coupled to the second main surface of the semiconductor region and the other main surface facing the one main surface. A conductive substrate having a main surface; an auxiliary electrode formed on the other main surface of the conductive substrate; a conductor that electrically connects the first diode-forming electrode to the conductive substrate; It is desirable that the second diode forming electrode comprises a conductor that is electrically connected to the conductive substrate.

本発明は次の効果を有する。
（イ）共通の主半導体領域の第１の主面上に、第１及び第２の主電極と、ゲート手段と、第１及び第２のダイオード形成用電極とを設け、第１のダイオード形成用電極と第２のダイオード形成用電極とを相互に接続することによって特許文献１に開示されている双方向スイッチと同様な機能を有する双方向スイッチが構成されている。即ち、第１及び第２の主電極とゲート手段とによって主半導体スイッチング素子（例えばＨＥＭＴ）が構成され、第１及び第２の主電極と第１及び第２のダイオード形成用電極とよって第１及び第２のダイオードが構成されている。従って、第１及び第２のダイオードを個別部品とすることが不要になり、双方向スイッチの小型化及び低コスト化が可能になる。
（ロ）第１及び第２の主電極は、主半導体スイッチング素子（例えばＨＥＭＴ）の主電極（ソース又はドレイン）と第１及び第２のダイオードの電極（例えばカソード）との両方の機能を有するので、双方向スイッチの更なる小型化及び低コスト化が可能になる。また、主半導体スイッチング素子と第１及び第２のダイオードとの相互接続部分の長さを短くすることができる。これにより、相互接続部分の寄生インピーダンスを低減し、双方向スイッチの動作速度を高めることができる。
（ハ）第１及び第２のダイオードには負荷電流が流れないので、第１及び第２のダイオードを設けることによる主半導体領域のサイズの増大は少ない。
（ニ）主半導体領域に電気的及び機械的に結合された導電性基板を前記接続手段に電気的に接続することによって、導電性基板の電位を安定化することができる。即ち、ＨＥＭＴにおいて周知のように、ソース電極を基板に接続し、基板の電位をソース電極の電位にすることが望ましい。しかし、本願の双方向スイッチにおいて、第１及び第２の主電極間に正方向電圧が印加された時には第２の主電極がソース電極として機能し、第１及び第２の主電極間に負方向電圧が印加された時には第１の主電極がソース電極として機能する。従って、第１及び第２の主電極を固定的にソース電極とすることができない。しかし、導電性基板を、接続導体を介して第１及び第２のダイオード形成用電極に接続すると、第１及び第２の主電極間に正方向電圧が印加された時と負方向電圧が印加された時のいずれにおいても、導電性基板がソース電極として機能する第１又は第２の主電極に近い電位になり、導電性基板の電位がソース電極に近い電位に安定化する。これにより、周知のＨＥＭＴにおける、ソース電極を基板に接続して基板の電位を安定化することと同様な効果を得ることができ、ゲート手段による電流制御の動作安定化を図ることができる。
また、請求項９の発明によれば、第１のダイオード形成用電極を導電性基板に電気的に接続する導体と、第２のダイオード形成用電極を導電性基板に電気的に接続する導体とを設けることによって、第１のダイオード形成用電極と第２のダイオード形成用電極との相互接続を容易に達成することができる。 The present invention has the following effects.
(A) On the first main surface of the common main semiconductor region, the first and second main electrodes, the gate means, and the first and second diode forming electrodes are provided to form the first diode. A bidirectional switch having a function similar to that of the bidirectional switch disclosed in Patent Document 1 is configured by connecting the electrode for electrode and the second electrode for forming a diode to each other. That is, the first and second main electrodes and the gate means constitute a main semiconductor switching element (for example, HEMT), and the first and second main electrodes and the first and second diode forming electrodes form the first. And a second diode is configured. Accordingly, it is not necessary to use the first and second diodes as separate parts, and the bidirectional switch can be reduced in size and cost.
(B) The first and second main electrodes function as both the main electrode (source or drain) of the main semiconductor switching element (for example, HEMT) and the electrodes (for example, cathode) of the first and second diodes. As a result, the bidirectional switch can be further reduced in size and cost. In addition, the length of the interconnection portion between the main semiconductor switching element and the first and second diodes can be shortened. Thereby, the parasitic impedance of the interconnection portion can be reduced, and the operation speed of the bidirectional switch can be increased.
(C) Since no load current flows through the first and second diodes, the increase in the size of the main semiconductor region due to the provision of the first and second diodes is small.
(D) The electric potential of the conductive substrate can be stabilized by electrically connecting the conductive substrate electrically and mechanically coupled to the main semiconductor region to the connecting means. That is, as is well known in HEMT, it is desirable to connect the source electrode to the substrate and set the potential of the substrate to the potential of the source electrode. However, in the bidirectional switch of the present application, when a positive voltage is applied between the first and second main electrodes, the second main electrode functions as a source electrode, and a negative voltage is applied between the first and second main electrodes. When the directional voltage is applied, the first main electrode functions as a source electrode. Therefore, the first and second main electrodes cannot be fixedly used as source electrodes. However, when the conductive substrate is connected to the first and second diode forming electrodes via the connection conductor, a negative voltage is applied when a positive voltage is applied between the first and second main electrodes. In any case, the conductive substrate becomes a potential close to the first or second main electrode functioning as the source electrode, and the potential of the conductive substrate is stabilized to a potential close to the source electrode. Thus, in a known HEMT, by connecting the source electrode to the substrate can Rukoto obtain the same effect as to stabilize the potential of the substrate, it is possible to stabilize operation of the current control by the gate means.
According to the invention of claim 9 , the conductor that electrically connects the first diode forming electrode to the conductive substrate, and the conductor that electrically connects the second diode forming electrode to the conductive substrate; By providing this, it is possible to easily achieve the interconnection between the first diode forming electrode and the second diode forming electrode.

次に図面を参照して本発明の実施形態を説明する。   Next, an embodiment of the present invention will be described with reference to the drawings.

図３に示す実施例１に従う交流スイッチ又は双方向スイッチング回路装置と呼ぶこともできる双方向スイッチ１０は、大別して基板１１と、主半導体領域１２と、第１及び第２の主電極１３，１４と、ノーマリオン型ゲート手段としてのゲート電極１５と、第１及び第２のダイオード形成用電極１６，１７と、接続導体１８とから成る。図４に図３の双方向スイッチ１０の等価回路と、双方向ス イッチ１０に接続された交流電源６と負荷７とから成る電気回路５と、及びゲート制御回路19とが示されている。図４において第１の主電極１３は負荷７を介して交流電源６の一端に接続され、第２の主電極１４は交流電源６の他端に接続されている。図４で示すゲート制御回路１９はゲート電極１５と接続導体１８との間に接続されている。図３に示すように双方向スイッチ１０は鎖線で区画して示す電界効果トランジスタの一種である高電子移動度トランジスタ即ちＨＥＭＴ（High Electron Mobility Transistor）と同様な構成の主半導体スイッチング素子２０とショットキーダイオード構成の第１及び第２のダイオード２１，２２とを有する。図４に示すように第１及び第２のダイオード２１，２２は互いに逆の方向を有して直列に接続され、この直列接続回路が主半導体スイッチング素子２０に並列に接続されている。次に図３の各部を詳しく説明する。 A bidirectional switch 10 that can be called an AC switch or a bidirectional switching circuit device according to the first embodiment shown in FIG. 3 is roughly divided into a substrate 11, a main semiconductor region 12, and first and second main electrodes 13 and 14. And a gate electrode 15 as normally-on type gate means, first and second diode forming electrodes 16 and 17, and a connection conductor 18. FIG. 4 shows an equivalent circuit of the bidirectional switch 10 of FIG. 3, an electric circuit 5 composed of an AC power source 6 and a load 7 connected to the bidirectional switch 10, and a gate control circuit 19 . In FIG. 4, the first main electrode 13 is connected to one end of the AC power source 6 through the load 7, and the second main electrode 14 is connected to the other end of the AC power source 6. The gate control circuit 19 shown in FIG. 4 is connected between the gate electrode 15 and the connection conductor 18. As shown in FIG. 3, the bidirectional switch 10 includes a main semiconductor switching element 20 and a Schottky having the same configuration as a high electron mobility transistor (HEMT) which is a kind of field effect transistor shown by a chain line. It has the 1st and 2nd diodes 21 and 22 of a diode structure. As shown in FIG. 4, the first and second diodes 21 and 22 are connected in series with opposite directions, and this series connection circuit is connected in parallel to the main semiconductor switching element 20. Next, each part of FIG. 3 will be described in detail.

基板１１は主半導体領域１２をエピタキシャル成長で形成するための成長基板であって、一方の主面２３と該一方の主面２３に対向する他方の主面２４とを有する。この実施例の基板１１は導電性シリコン単結晶で形成されている。しかし、基板１１をシリコンカーバイト（ＳｉＣ）等の半導体、又はサファイア、セラミック等の絶縁体で形成することもできる。 The substrate 11 is a growth substrate for forming the main semiconductor region 12 by epitaxial growth, and has one main surface 23 and the other main surface 24 opposite to the one main surface 23. The substrate 11 of this embodiment is made of a conductive silicon single crystal. However, the substrate 11 can also be formed of a semiconductor such as silicon carbide (SiC), or an insulator such as sapphire or ceramic.

主半導体領域１２は、基板１１から離れた第１の主面２５と該第１の主面２５に対向し且つ基板１１の一方の主面２３に接している第２の主面２６とを有し、バッファ層２７と電子走行層と呼ぶこともできる第１の半導体層２８と電子供給層と呼ぶこともできる第２の半導体層２９とで構成されている。   The main semiconductor region 12 has a first main surface 25 that is separated from the substrate 11 and a second main surface 26 that faces the first main surface 25 and is in contact with one main surface 23 of the substrate 11. The first semiconductor layer 28 can also be referred to as a buffer layer 27, an electron transit layer, and the second semiconductor layer 29, which can also be referred to as an electron supply layer.

バッファ層２７は、基板１１の一方の主面２３上に窒化物半導体を周知のＭＯＣＶＤ法でエピタキシャル成長させることによって形成されている。図３では、図示を簡略化するためにバッファ層２３が１つの層で示されているが、実際には複数の層で形成されている。即ち、このバッファ層２７はＡＩＮ（窒化アルミニウム）からなる第１のサブレイヤー（第１の副層）とＧａＮ（窒化ガリウム）から成る第２のサブレイヤー（第２の副層）とが交互に積層された多層構造バッファである。なお、このバッファ層２７は主半導体スイッチング素子２０、第１及び第２のダイオード２１，２２の動作に直接関係していないので、これを省くこともできる。また、バッファ層２７の半導体材料をＡｌＮ、ＧａＮ以外の窒化物半導体又は３−５族化合物半導体に置き換えること、又は単層構造のバッファ層にすることもできる。 The buffer layer 27 is formed by epitaxially growing a nitride semiconductor on one main surface 23 of the substrate 11 by a well-known MOCVD method. In FIG. 3, the buffer layer 23 is shown as a single layer for the sake of simplicity, but actually it is formed of a plurality of layers. That is, the buffer layer 27 includes first sublayers (first sublayer) made of AIN (aluminum nitride) and second sublayers (second sublayer) made of GaN (gallium nitride) alternately. It is a laminated multilayer structure buffer. Since the buffer layer 27 is not directly related to the operation of the main semiconductor switching element 20 and the first and second diodes 21 and 22, it can be omitted. Further, the semiconductor material of the buffer layer 27 can be replaced with a nitride semiconductor other than AlN or GaN or a Group 3-5 compound semiconductor, or a buffer layer having a single layer structure can be formed.

第１の半導体層（電子走行層）２８は、この上の電子供給層としての第２の半導体層２９とのヘテロ接合面の近傍に電流通路（チャネル）としての２次元電子ガス層即ち２ＤＥＧ層３０（点線で示す）を得るためのものであって、バッファ層２７上にアンドープの第１の窒化物半導体を周知のＭＯＣＶＤ法で例えば０．３〜１０μｍの厚さにエピタキシャル成長させたものである。この第１の半導体層（電子走行層）２８を形成するための好ましい第１の窒化物半導体は、
ＡｌaＩｎbＧａ1-a-bＮ，
ここで、ａは０≦ａ＜１、ｂは０≦ｂ＜１を満足する数値、
である。しかし、第１の半導体層（電子走行層）２８を第１の窒化物半導体以外の化合物半導体で形成することもできる。 The first semiconductor layer (electron transit layer) 28 is a two-dimensional electron gas layer as a current path (channel), that is, a 2DEG layer, in the vicinity of the heterojunction surface with the second semiconductor layer 29 as the electron supply layer thereon. 30 (indicated by a dotted line), and an undoped first nitride semiconductor is epitaxially grown on the buffer layer 27 to a thickness of, for example, 0.3 to 10 μm by a known MOCVD method. . A preferred first nitride semiconductor for forming the first semiconductor layer (electron transit layer) 28 is:
Al a In b Ga 1-ab N,
Here, a is a numerical value satisfying 0 ≦ a <1, b is 0 ≦ b <1,
It is. However, the first semiconductor layer (electron transit layer) 28 can also be formed of a compound semiconductor other than the first nitride semiconductor.

第２の半導体層２９は、第１の窒化物半導体よりも大きいバンドギャップを有し且つ第１の窒化物半導体よりも小さい格子定数を有する第２の窒化物半導体を第１の半導体層２８の上に好ましくは５〜１００ｎｍの厚みに周知のＭＯＣＶＤ法でエピタキシャル成長させたものから成る。この第２の半導体層２９を形成するための好ましい第２の窒化物半導体は、
ＡｌxＩｎyＧａ1-x-yＮ，
ここで、ｘは０＜ｘ＜１、ｙは０≦ｙ＜１を満足する数値、
である。
この第２の半導体層２９を、アンドープのＡｌxＩｎyＧａ1-x-yＮで形成する代わりに、ｎ型（第１導電型）の不純物を添加したＡｌxＩｎyＧａ1-x-yＮから成る窒化物半導体、又は別の組成の窒化物半導体、又は別の化合物半導体で形成することもできる。 The second semiconductor layer 29 includes a second nitride semiconductor having a larger band gap than the first nitride semiconductor and a lattice constant smaller than that of the first nitride semiconductor. It is preferably formed by epitaxial growth with a known MOCVD method to a thickness of 5 to 100 nm. A preferred second nitride semiconductor for forming the second semiconductor layer 29 is:
Al x In y Ga 1-xy N,
Where x is 0 <x <1, y is a numerical value satisfying 0 ≦ y <1,
It is.
The second semiconductor layer 29, instead of forming in undoped Al x In y Ga 1-xy N, made of Al was doped n-type (first conductivity type) x In y Ga 1-xy N A nitride semiconductor, a nitride semiconductor having another composition, or another compound semiconductor may be used.

第１の主電極１３は主半導体領域１２の主半導体スイッチング素子２０を構成する部分と第１のダイオード２１を構成する部分との境界上に配置され、主半導体スイッチング素子２０の第１の主電極部分（ソース又はドレイン部分）１３ａと第１のダイオード２１のカソード部分１３ｂとを有する。第１の主電極部分（ソース又はドレイン部分）１３ａと第１のダイオード２１のカソード部分１３ｂとを一体に形成することが小型化のために有効であるが、これ等を互いに離間させ、離間した第１の主電極部分（ソース又はドレイン部分）１３ａと第１のダイオード２１のカソード部分１３ｂとを電気的に接続する手段を設けることもできる。例えば、第１の主電極部分（ソース又はドレイン部分）１３ａと第１のダイオード２１のカソード部分１３ｂとの電気的接続を２ＤＥＧ層３０を利用して行うこと、又は別個の導体を用いて行うこともできる。本願では２ＤＥＧ層３０を利用して接続された第１の主電極部分（ソース又はドレイン部分）１３ａと第１のダイオード２１のカソード部分１３ｂとの組み合わせも第１の主電極と呼ぶことにする。第２の主電極１４は主半導体領域１２の主半導体スイッチング素子２０を構成する部分と第２のダイオード２２を構成する部分との境界上に配置され、主半導体スイッチング素子２０の第２の主電極部分（ドレイン又はソース部分）１４ａと第２のダイオード２２のカソード部分１４ｂとを有する。第２の主電極部分（ドレイン又はソース部分）１４ａと第２のダイオード２２のカソード部分１４ｂとを一体に形成することが小型化のために有効であるが、これ等を互いに離間させ、離間した第２の主電極部分（ドレイン又はソース部分）１４ａと第２のダイオード２２のカソード部分１４ｂとを電気的に接続する手段を設けることもできる。例えば、第２の主電極部分（ソース又はドレイン部分）１４ａと第２のダイオード２２のカソード部分１４ｂとの電気的接続を２ＤＥＧ層３０を利用して行うこと、又は別個の導体を用いて行うこともできる。本願では２ＤＥＧ層３０を利用して接続された第２の主電極部分（ソース又はドレイン部分）１４ａと第１のダイオード２１のカソード部分１４ｂとの組み合わせも第２の主電極と呼ぶことにする。第１及び第２の主電極１３、１４は主半導体領域１２の第１の主面２５即ち第２の半導体層２９の表面上にそれぞれオーミック（低抵抗性）接触されている。本実施例の第１及び第２の主電極１３，１４は、チタン（Ｔｉ）とアルミニウム（Ａｌ）との積層体でそれぞれ形成されているが、これ以外の低抵抗性接触（オーミック接触）可能な金属で形成することもできる。なお、第２の半導体層２９は極めて薄いので、この厚み方向の抵抗は無視できるほど小さい。従って、第１及び第２の主電極１３，１４は、２ＤＥＧ層３０に電気的に結合されている。   The first main electrode 13 is arranged on the boundary between the portion constituting the main semiconductor switching element 20 and the portion constituting the first diode 21 in the main semiconductor region 12, and the first main electrode of the main semiconductor switching element 20. A portion (source or drain portion) 13 a and a cathode portion 13 b of the first diode 21 are included. Although it is effective for miniaturization to integrally form the first main electrode portion (source or drain portion) 13a and the cathode portion 13b of the first diode 21, they are separated from each other. Means for electrically connecting the first main electrode portion (source or drain portion) 13a and the cathode portion 13b of the first diode 21 may be provided. For example, electrical connection between the first main electrode portion (source or drain portion) 13a and the cathode portion 13b of the first diode 21 is performed using the 2DEG layer 30, or using a separate conductor. You can also. In the present application, a combination of the first main electrode portion (source or drain portion) 13a connected using the 2DEG layer 30 and the cathode portion 13b of the first diode 21 is also referred to as a first main electrode. The second main electrode 14 is disposed on the boundary between the portion constituting the main semiconductor switching element 20 and the portion constituting the second diode 22 in the main semiconductor region 12, and the second main electrode of the main semiconductor switching element 20. A portion (drain or source portion) 14 a and a cathode portion 14 b of the second diode 22 are included. Although it is effective for miniaturization to integrally form the second main electrode portion (drain or source portion) 14a and the cathode portion 14b of the second diode 22, they are separated from each other. Means for electrically connecting the second main electrode portion (drain or source portion) 14a and the cathode portion 14b of the second diode 22 may be provided. For example, electrical connection between the second main electrode portion (source or drain portion) 14a and the cathode portion 14b of the second diode 22 is performed using the 2DEG layer 30, or using a separate conductor. You can also. In the present application, a combination of the second main electrode portion (source or drain portion) 14a connected using the 2DEG layer 30 and the cathode portion 14b of the first diode 21 is also referred to as a second main electrode. The first and second main electrodes 13 and 14 are in ohmic contact with the first main surface 25 of the main semiconductor region 12, that is, the surface of the second semiconductor layer 29. The first and second main electrodes 13 and 14 of this embodiment are each formed of a laminate of titanium (Ti) and aluminum (Al), but other low-resistance contact (ohmic contact) is possible. It can also be formed of a different metal. Since the second semiconductor layer 29 is extremely thin, the resistance in the thickness direction is negligibly small. Accordingly, the first and second main electrodes 13, 14 are electrically coupled to the 2DEG layer 30.

ゲート電極１５は、第１及び第２の主電極１３，１４間の電流を制御するゲート手段であって、主半導体領域１２の第１の主面２５にショットキー接触している金属電極から成る。この金属電極は、例えば、Ｎｉ（ニッケル）とＡｕ（金）との積層体、又はＰｔ（白金）とＡｕ（金）との積層体で形成される。主半導体スイッチング素子２０の正方向耐圧と逆方向耐圧とを同一にするために、ゲート電極１５を中心にして主半導体スイッチング素子２０を対称的に形成することが望ましい。従って、図３では、ゲート電極１５が第１及び第２の主電極１３、１４の中間に配置され、第１の主電極１３とゲート電極１５との間隔及び第２の主電極１４とゲート電極１５との間隔は実質的に等しい。しかし、主半導体スイッチング素子２０に要求される耐圧を満足することができる範囲でゲート電極１５の位置を第１及び第２の主電極１３，１４の中間位置から少しずらすことができる。例えば、第１の主電極１３とゲート電極１５との間隔を基準にして第２の主電極１４とゲート電極１５との間隔を所定の範囲（例えばー２０％〜＋２０％）で変えることができる。   The gate electrode 15 is a gate means for controlling the current between the first and second main electrodes 13 and 14 and is made of a metal electrode that is in Schottky contact with the first main surface 25 of the main semiconductor region 12. . The metal electrode is formed of, for example, a laminate of Ni (nickel) and Au (gold) or a laminate of Pt (platinum) and Au (gold). In order to make the forward breakdown voltage and the reverse breakdown voltage of the main semiconductor switching element 20 the same, it is desirable to form the main semiconductor switching element 20 symmetrically about the gate electrode 15. Therefore, in FIG. 3, the gate electrode 15 is disposed between the first and second main electrodes 13, 14, and the distance between the first main electrode 13 and the gate electrode 15 and the second main electrode 14 and the gate electrode. The interval with 15 is substantially equal. However, the position of the gate electrode 15 can be slightly shifted from the intermediate position between the first and second main electrodes 13 and 14 within a range in which the breakdown voltage required for the main semiconductor switching element 20 can be satisfied. For example, the interval between the second main electrode 14 and the gate electrode 15 can be changed within a predetermined range (for example, -20% to + 20%) with reference to the interval between the first main electrode 13 and the gate electrode 15. .

図３のＨＥＭＴ構成の主半導体スイッチング素子２０において、第２の半導体層２９が第１の半導体層２８にヘテロ接合されているので、第２の半導体層２９にピエゾ分極が生じる。また、第２の半導体層２９に自発分極も生じる。第２の半導体層２９に分極が生じると、第１及び第２の半導体層２８、２９の界面近傍に周知の２ＤＥＧ層３０が生じる。本実施例の主半導体スイッチング素子２０はノーマリオン型であるので、第１及び第２の主電極１３，１４間に第１の主電極１３の電位が第２の主電極１４の電位よりも高い電圧（正方向電圧）が印加されている時において、ゲート電極１５の電位がソースとして機能する第２の主電極１４の電位を基準にして零の時、又は第１及び第２の主電極１３，１４間に第１の主電極１３の電位が第２の主電極１４の電位よりも低い電圧（負方向電圧）が印加されている時において、ソースとして機能する第１の主電極１３を基準にして零の時であってもゲート電極１５の直下に２ＤＥＧ層３０が生じる。正方向電圧が印加されている主半導体スイッチング素子２０をオフにする時には、ソース電極として機能している第２の主電極１４を基準にしてゲート電極１５の電位を閾値よりも低い負の値（例えばー５Ｖ）にする。また、負方向電圧が印加されている主半導体スイッチング素子２０をオフにする時には、ソース電極として機能している第１の主電極１３を基準にしてゲート電極１５の電位をしきい値より低い負の値（例えばー５Ｖ）にする。ゲート電極１５の電位をソース電極に対して負の値にすると、第１の半導体層２８のゲート電極１５の直下の部分から電子が排除され、２ＤＥＧ層３０の分断が生じ、第１及び第２の主電極１３，１４間の電流が遮断される。   In the main semiconductor switching element 20 having the HEMT configuration in FIG. 3, the second semiconductor layer 29 is heterojunction with the first semiconductor layer 28, so that piezoelectric polarization occurs in the second semiconductor layer 29. In addition, spontaneous polarization also occurs in the second semiconductor layer 29. When polarization occurs in the second semiconductor layer 29, a well-known 2DEG layer 30 is generated in the vicinity of the interface between the first and second semiconductor layers 28 and 29. Since the main semiconductor switching element 20 of the present embodiment is a normally-on type, the potential of the first main electrode 13 is higher than the potential of the second main electrode 14 between the first and second main electrodes 13 and 14. When a voltage (positive voltage) is applied, when the potential of the gate electrode 15 is zero with respect to the potential of the second main electrode 14 functioning as a source, or the first and second main electrodes 13 , 14, the first main electrode 13 functioning as a source is used as a reference when a voltage (negative direction voltage) in which the potential of the first main electrode 13 is lower than the potential of the second main electrode 14 is applied. Even when the time is zero, the 2DEG layer 30 is formed immediately below the gate electrode 15. When the main semiconductor switching element 20 to which a positive direction voltage is applied is turned off, the potential of the gate electrode 15 is set to a negative value lower than a threshold value with respect to the second main electrode 14 functioning as the source electrode ( For example, -5V). Further, when turning off the main semiconductor switching element 20 to which a negative direction voltage is applied, the potential of the gate electrode 15 is set to a negative value lower than the threshold value with respect to the first main electrode 13 functioning as the source electrode. (For example, -5V). When the potential of the gate electrode 15 is set to a negative value with respect to the source electrode, electrons are excluded from a portion of the first semiconductor layer 28 immediately below the gate electrode 15, and the 2DEG layer 30 is divided. The current between the main electrodes 13 and 14 is cut off.

第１のダイオード形成用電極１６は主半導体領域１２の第１の主面２５の第１の主電極１３を基準にしてゲート電極１５と反対側の位置に配置され、主半導体領域１２にショットキー接触している。第２のダイオード形成用電極１７は主半導体領域１２の第１の主面２５の第２の主電極１４を基準にしてゲート電極１５と反対側の位置に配置され、主半導体領域１２にショットキー接触している。第１及び第２のダイオード形成用電極１６、１７はゲート電極１５と同一材料で同時に形成されたものであり、ショットキー接触可能な金属、例えばＮｉ（ニッケル）とＡｕ（金）との積層体、又はＰｔ（白金）とＡｕ（金）との積層体から成る。第１及び第２のダイオード形成用電極１６、１７は第１及び第２のダイオード２１，２２のアノードとして機能する。従って、正方向電圧の印加時において、第１のダイオード２１が逆バイアス状態になり、第２のダイオード２２が順バイアス状態になる。逆に、逆方向電圧の印加時において、第１のダイオード２１が順バイアス状態になり、第２のダイオード２２が逆バイアス状態になる。主半導体スイッチング素子２０がオン状態で第１のダイオード２１が順バイアス状態の時には、第１のダイオード形成用電極１６、第１の半導体層２９、２ＤＥＧ層３０、第１の半導体層２９、及び第１の主電極１３の経路が導通状態になる。主半導体スイッチング素子２０がオン状態で第２のダイオード２２が順バイアス状態の時には、第２のダイオード形成用電極１７、第１の半導体層２９、２ＤＥＧ層３０、第１の半導体層２９、及び第２の主電極１４の経路が導通状態になる。 The first diode forming electrode 16 is disposed at a position opposite to the gate electrode 15 with respect to the first main electrode 13 of the first main surface 25 of the main semiconductor region 12, and is formed in the main semiconductor region 12 with a Schottky. In contact. The second diode-forming electrode 17 is disposed at a position opposite to the gate electrode 15 with respect to the second main electrode 14 of the first main surface 25 of the main semiconductor region 12, and the Schottky is formed on the main semiconductor region 12. In contact. The first and second diode forming electrodes 16 and 17 are formed of the same material as that of the gate electrode 15 at the same time, and are a Schottky contact metal, for example, a laminate of Ni (nickel) and Au (gold). Or a laminate of Pt (platinum) and Au (gold). The first and second diode forming electrodes 16 and 17 function as anodes of the first and second diodes 21 and 22. Therefore, when the forward voltage is applied, the first diode 21 is in the reverse bias state, and the second diode 22 is in the forward bias state. Conversely, when a reverse voltage is applied, the first diode 21 is in a forward bias state, and the second diode 22 is in a reverse bias state. When the main semiconductor switching element 20 is in the on state and the first diode 21 is in the forward bias state, the first diode forming electrode 16, the first semiconductor layer 29, the 2DEG layer 30, the first semiconductor layer 29, and the The path of one main electrode 13 becomes conductive. When the main semiconductor switching element 20 is in the on state and the second diode 22 is in the forward bias state, the second diode forming electrode 17, the first semiconductor layer 29, the 2DEG layer 30, the first semiconductor layer 29, and the The path of the second main electrode 14 becomes conductive.

接続導体１８は、第１及び第２のダイオード形成用電極１６、１７間を電気的に接続している。この実施例では、接続導体１８が、双方向スイッチ１０をより小型化するために主半導体領域１２の第１の主面２５上に配置された絶縁膜（図示せず）の上に形成されている。しかし、接続導体１８を金属ワイヤ等の外部接続部材とすることもできる。 The connection conductor 18 electrically connects the first and second diode forming electrodes 16 and 17. In this embodiment, the connection conductor 18 is formed on an insulating film (not shown) disposed on the first main surface 25 of the main semiconductor region 12 in order to further reduce the size of the bidirectional switch 10. Yes. However, the connection conductor 18 can also be an external connection member such as a metal wire.

次に、図３の双方向スイッチ１０の動作を説明する。この双方向スイッチ１０を使用する時には、図４で示すように、第１及び第２の主電極１３、１４に例えば交流電源６と負荷７とを含む電気回路５を接続し、ゲート電極１５と接続導体１８との間にゲート制御回路１９を接続する。第１の主電極１３の電位が第２の主電極１４の電位よりも高く、且つゲート制御回路１９からゲート電極１５の電位をソースとして機能している第２の主電極１４に対して閾値電圧よりも小さい負の値にする信号が出力されている時には、ノーマリオン型の主半導体スイッチング素子２０がオフになり、双方向スイッチ１０もオフになる。なお、第１の主電極１３の電位が第２の主電極１４の電位よりも高い時には、接続導体は１８と第２の主電極１４との間の電位差は第２のダイオード２２の順バイアス電圧以上となることはなく、せいぜい約０．７Ｖである。従って、接続導体１８の電位をゲートの基準電位と考えることもできる。双方向スイッチ１０はゲートを中心にして対称的に形成されているので、第２の主電極１４の電位が第１の主電極１３の電位よりも高く、且つゲート制御回路１９からゲート電極１５の電位をソースとして機能している第１の主電極１３に対して閾値電圧よりも小さい負の値にする信号が出力されている時にも、主半導体スイッチング素子２０がオフになり、双方向スイッチ１０もオフになる。なお、第２の主電極１４の電位が第１の主電極１３の電位よりも高い時には接続導体１８と第１の主電極１３の電位差が第１のダイオード２１の順バイアス電圧以上となることはなく、せいぜい約０．７Ｖである。ゲート電極１５の電位を、ソースとして機能する第１の主電極１３又は第２の主電極１４を基準にして主半導体スイッチング素子２０の閾値以上の値（例えば零又は正電位）にする信号がゲート制御回路１９から出力されている時には、主半導体スイッチング素子２０がオンになり、双方向スイッチ１０もオンになる。 Next, the operation of the bidirectional switch 10 in FIG. 3 will be described. When the bidirectional switch 10 is used, as shown in FIG. 4, an electric circuit 5 including, for example, an AC power source 6 and a load 7 is connected to the first and second main electrodes 13 and 14, and the gate electrode 15 A gate control circuit 19 is connected to the connection conductor 18. The potential of the first main electrode 13 is higher than the potential of the second main electrode 14, and the threshold voltage is applied to the second main electrode 14 functioning as a source of the potential of the gate electrode 15 from the gate control circuit 19. When a signal having a smaller negative value is output, the normally-on main semiconductor switching element 20 is turned off, and the bidirectional switch 10 is also turned off. When the potential of the first main electrode 13 is higher than the potential of the second main electrode 14, the potential difference between the connection conductor 18 and the second main electrode 14 is the forward bias voltage of the second diode 22. This is not the case, and is at most about 0.7V. Therefore, the potential of the connection conductor 18 can be considered as the reference potential of the gate. Since the bidirectional switch 10 is formed symmetrically about the gate, the potential of the second main electrode 14 is higher than the potential of the first main electrode 13 and the gate control circuit 19 connects the gate electrode 15 to the gate electrode 15. The main semiconductor switching element 20 is also turned off when the signal that makes the potential a negative value smaller than the threshold voltage is output to the first main electrode 13 functioning as a source, and the bidirectional switch 10 Will also turn off. Note that when the potential of the second main electrode 14 is higher than the potential of the first main electrode 13, the potential difference between the connection conductor 18 and the first main electrode 13 is not less than the forward bias voltage of the first diode 21. At most, it is about 0.7V. A signal that sets the potential of the gate electrode 15 to a value (for example, zero or positive potential) equal to or higher than the threshold value of the main semiconductor switching element 20 with the first main electrode 13 or the second main electrode 14 functioning as a source as a reference. When output from the control circuit 19, the main semiconductor switching element 20 is turned on, and the bidirectional switch 10 is also turned on.

本実施例の双方向スイッチ１０は次の効果を有する。
（１） 共通の主半導体領域１２の第１の主面２５上に、第１及び第２の主電極１３，１４と、ゲート手段としてのゲート電極１５と、第１及び第２のダイオード形成用電極１６，１７とを設け、第１のダイオード形成用電極１６と第２のダイオード形成用電極１７とを相互に接続することによって特許文献１に開示されている双方向スイッチと同様に動作する双方向スイッチ１０が構成されている。即ち、主半導体スイッチング素子２０と第１及び第２のダイオード２１，２２が共通の主半導体領域１２を使用して形成されているので、従来の第１及び第２のダイオードを個別部品とする場合に比較して双方向スイッチ１０の小型化及び低コスト化が可能になる。なお、第１及び第２のダイオード２１，２２はゲートの基準電位の決定に寄与するものであり、負荷電流を流すものではない。従って、第１及び第２のダイオード２１，２２を形成するための主半導体領域１２のスペースは、主半導体スイッチング素子２０を形成するための主半導体領域１２のスペースよりも大幅に小さくできる。
（２）主半導体スイッチング素子２０は２ＤＥＧ層３０を使用したＨＥＭＴ構成の電界効果トランジスタであり、且つ第１及び第２のダイオード２１，２２も２ＤＥＧ層３０を使用したショットキーダイオードであるので、高速動作可能であり且つオン状態における抵抗が比較的小さい双方向スイッチ１０を提供できる。
（３）第１及び第２の主電極１３，１４は、主半導体スイッチング素子２０の主電極（ソース電極又はドレイン電極）と第１及び第２のダイオード２１，２２のカソード電極との両方の機能を有するので、双方向スイッチ１０の更なる小型化及び低コスト化が可能になる。また、第１及び第２のダイオード形成用電極１６、１７と第１及び第２の主電極１３，１４との間が外部導体を使用しないで２ＤＥＧ層３０で電気的に接続されているので、寄生インピーダンス成分が小さくなり、双方向スイッチ１０の高速動作が可能になる。
（４）主半導体領域１２が高耐圧化可能な窒化物半導体（窒化物系半導体）から成るので、主半導体スイッチング素子２０及び第１及び第２のダイオード２１，２２の高耐圧化が可能になる。
（５）第１及び第２のダイオード２１，２２のための第１及び第２のダイオード形成用電極１６，１７はゲート電極１５と同一材料で同時に形成されているので、第１及び第２のダイオード２１，２２を形成すための製造工程の増加を抑制できる。 The bidirectional switch 10 of the present embodiment has the following effects.
(1) On the first main surface 25 of the common main semiconductor region 12, the first and second main electrodes 13, 14, the gate electrode 15 as gate means, and the first and second diodes are formed. The electrodes 16 and 17 are provided, and both the first diode forming electrode 16 and the second diode forming electrode 17 are connected to each other to operate similarly to the bidirectional switch disclosed in Patent Document 1. A direction switch 10 is configured. That is, since the main semiconductor switching element 20 and the first and second diodes 21 and 22 are formed using the common main semiconductor region 12, the conventional first and second diodes are used as individual components. Compared to this, the bidirectional switch 10 can be reduced in size and cost. The first and second diodes 21 and 22 contribute to the determination of the gate reference potential, and do not flow a load current. Accordingly, the space of the main semiconductor region 12 for forming the first and second diodes 21 and 22 can be significantly smaller than the space of the main semiconductor region 12 for forming the main semiconductor switching element 20.
(2) Since the main semiconductor switching element 20 is a HEMT field effect transistor using the 2DEG layer 30, and the first and second diodes 21 and 22 are also Schottky diodes using the 2DEG layer 30, A bidirectional switch 10 that is operable and has a relatively low resistance in the on state can be provided.
(3) The first and second main electrodes 13 and 14 function as both the main electrode (source electrode or drain electrode) of the main semiconductor switching element 20 and the cathode electrodes of the first and second diodes 21 and 22. Thus, the bidirectional switch 10 can be further reduced in size and cost. In addition, since the first and second diode forming electrodes 16 and 17 and the first and second main electrodes 13 and 14 are electrically connected by the 2DEG layer 30 without using an external conductor, The parasitic impedance component is reduced, and the bidirectional switch 10 can be operated at high speed.
(4) Since the main semiconductor region 12 is made of a nitride semiconductor (nitride-based semiconductor) capable of increasing the breakdown voltage, the breakdown voltage of the main semiconductor switching element 20 and the first and second diodes 21 and 22 can be increased. .
(5) The first and second diode forming electrodes 16 and 17 for the first and second diodes 21 and 22 are formed of the same material as the gate electrode 15 at the same time. An increase in manufacturing steps for forming the diodes 21 and 22 can be suppressed.

次に、実施例２に従う双方向スイッチ１０ａを図５及び図６を参照して説明する。但し、この実施例２及び後述する別の実施例において図３及び図４と実質的に同一の部分には同一の参照符号を付してその説明を省略する。図５の変形された双方向スイッチ１０ａは、変形された主半導体スイッチング素子２０ａと第１及び第２のダイオード２１ａ，２２ａを除いて図３と同一に構成されている。変形された主半導体スイッチング素子１３ａ、第１及び第２のダイオード２１ａ，２２ａは、図５に示すように背面電極又は補助電極とも呼ぶことができる基板電極３１を導電性を有する基板１１の他方の主面２４に有する他は、図３の主半導体スイッチング素子２０、第１及び第２のダイオード２１，２２と同一に形成されている。基板電極３１は、導体３２によって接続導体１８に接続されている。即ち、基板電極３１は、導体３２と接続導体１８とを介して第１及び第２のダイオード形成用電極１６，１７に接続されている   Next, the bidirectional switch 10a according to the second embodiment will be described with reference to FIGS. However, in the second embodiment and another embodiment to be described later, substantially the same parts as those in FIGS. 3 and 4 are denoted by the same reference numerals, and the description thereof is omitted. The modified bidirectional switch 10a of FIG. 5 has the same configuration as that of FIG. 3 except for the modified main semiconductor switching element 20a and the first and second diodes 21a and 22a. The deformed main semiconductor switching element 13a and the first and second diodes 21a and 22a have a substrate electrode 31 which can also be called a back electrode or an auxiliary electrode as shown in FIG. Other than having the main surface 24, the main semiconductor switching element 20 and the first and second diodes 21 and 22 in FIG. 3 are formed in the same manner. The substrate electrode 31 is connected to the connection conductor 18 by a conductor 32. That is, the substrate electrode 31 is connected to the first and second diode forming electrodes 16 and 17 via the conductor 32 and the connection conductor 18.

図５の双方向スイッチ１０ａの等価回路が図６に示されている。図５及び図６に示す双方向スイッチ１０ａの基本的構成は図３及び図４に示す双方向スイッチ１０と同一であるので、図５及び図６に示す双方向スイッチ１０ａは、図３及び図４に示す双方向スイッチ１０と同一の作用効果を有する。更に、図５及び図６に示す双方向スイッチ１０ａは、基板１１に電気的に接続された基板電極３１を有し、基板電極３１が導体３２と接続導体１８とを介して第１及び第２のダイオード形成用電極１６，１７に接続されている。このため、基板１１の電位を安定化することができる。即ち、ＨＥＭＴにおいて周知のように、ソース電極又はドレイン電極を基板に接続し、基板の電位をソース電極又はドレイン電極の電位にすることが望ましい。しかし、図５の双方向スイッチ１０ａにおいて、第１及び第２の主電極１３，１４間に正方向電圧が印加された時には第２の主電極１４がソース電極として機能し、第１及び第２の主電極１３，１４間に負方向電圧が印加された時には第１の主電極１３がソース電極として機能する。従って、第１及び第２の主電極１３，１４を固定的にソース電極又はドレイン電極とすることができない。もし、基板１１がフローティング状態の時には、基板１１の電位は第１の主電極１３の電位と第２の主電極１４の電位との約中間の値になり、交流電源６の電圧の変化によって基板１１の電位も変化し、基板１１の電位が安定化しない。しかし、図５に示すように基板電極３１を第１及び第２のダイオード形成用電極１６，１７に接続すると、導電性基板１１がソース電極として機能する第１又は第２の主電極１３，１４に近い電位（せいぜい約０．７Ｖ）になり、導電性基板１１の電位がソース電極に近い電位に安定化する。従って、主半導体スイッチング素子２０ａの動作を安定化できる。
なお、基板電極３１を接続導体１８に接続する代りに図５で点線３２ａで示すようにゲート電極１５に接続することもできる。 An equivalent circuit of the bidirectional switch 10a of FIG. 5 is shown in FIG. Since the basic configuration of the bidirectional switch 10a shown in FIGS. 5 and 6 is the same as that of the bidirectional switch 10 shown in FIGS. 3 and 4, the bidirectional switch 10a shown in FIGS. 4 has the same effect as the bidirectional switch 10 shown in FIG. Furthermore, the bidirectional switch 10a shown in FIGS. 5 and 6 has a substrate electrode 31 electrically connected to the substrate 11, and the substrate electrode 31 is connected to the first and second via the conductor 32 and the connection conductor 18. Are connected to the diode forming electrodes 16, 17. For this reason, the potential of the substrate 11 can be stabilized. That is, as is well known in HEMT, it is desirable to connect the source electrode or drain electrode to the substrate and set the potential of the substrate to the potential of the source electrode or drain electrode. However, in the bidirectional switch 10a of FIG. 5, when a positive voltage is applied between the first and second main electrodes 13, 14, the second main electrode 14 functions as a source electrode, and the first and second When a negative voltage is applied between the main electrodes 13 and 14, the first main electrode 13 functions as a source electrode. Therefore, the first and second main electrodes 13 and 14 cannot be fixedly used as a source electrode or a drain electrode. If the substrate 11 is in a floating state, the potential of the substrate 11 becomes an intermediate value between the potential of the first main electrode 13 and the potential of the second main electrode 14. 11 also changes, and the potential of the substrate 11 is not stabilized. However, when the substrate electrode 31 is connected to the first and second diode forming electrodes 16 and 17 as shown in FIG. 5, the first or second main electrode 13 or 14 in which the conductive substrate 11 functions as a source electrode. The potential of the conductive substrate 11 is stabilized at a potential close to the source electrode. Therefore, the operation of the main semiconductor switching element 20a can be stabilized.
Instead of connecting the substrate electrode 31 to the connecting conductor 18, it can be connected to the gate electrode 15 as shown by a dotted line 32a in FIG.

図７に示す実施例３の双方向スイッチ１０ｂは、変形された主半導体スイッチング素子２０ｂと変形された第１及び第２のダイオード２１ｂ，２２ｂと変形された共通接続導体１８ａを除いて図３と同一に構成されている。変形された主半導体スイッチング素子１３ｂ、第１及び第２のダイオード２１ｂ，２２ｂは、図７に示すように背面電極又は補助電極とも呼ぶことができる基板電極３１を、導電性を有するシリコン基板１１ａの他方の主面２４に有する他は、図３の主半導体スイッチング素子２０、第１及び第２のダイオード２１，２２と同一に形成されている。   The bidirectional switch 10b of the third embodiment shown in FIG. 7 is the same as that shown in FIG. 3 except for the deformed main semiconductor switching element 20b, the deformed first and second diodes 21b and 22b, and the deformed common connection conductor 18a. It is configured identically. The deformed main semiconductor switching element 13b and the first and second diodes 21b and 22b are formed on the substrate electrode 31 that can be called a back electrode or an auxiliary electrode as shown in FIG. Other than having it on the other main surface 24, it is formed in the same manner as the main semiconductor switching element 20, the first and second diodes 21 and 22 in FIG.

変形された共通接続導体１８ａは、導電性を有する基板１１ａと第１及び第２の接続導体４１，４３と第１及び第２の接続電極４２，４４とから成る。第１のダイオード形成用電極１６は第１の接続導体４１と第１の接続電極４２とを介して導電性を有する基板１１ａに接続され、第２のダイオード形成用電極１７は第２の接続導体４３と第２の接続電極４４とを介して導電性を有する基板１１ａに接続されている。従って、第１のダイオード形成用電極１６と第２のダイオード形成用電極１７は第１の接続導体４１と第１の接続電極４２と基板１１ａと第２の接続電極４４と第２の接続導体４３とを介して相互に接続されている。なお、第１及び第２のダイオード形成用電極１６、１７を基板電極３１に接続することもできる。ゲート制御回路１９はゲート電極１５と基板電極３１との間に接続されている。 The deformed common connection conductor 18 a includes a conductive substrate 11 a, first and second connection conductors 41 and 43, and first and second connection electrodes 42 and 44. The first diode forming electrode 16 is connected to the conductive substrate 11a via the first connecting conductor 41 and the first connecting electrode 42, and the second diode forming electrode 17 is connected to the second connecting conductor. 43 and the second connection electrode 44 are connected to the conductive substrate 11a. Accordingly, the first diode forming electrode 16 and the second diode forming electrode 17 are composed of the first connecting conductor 41, the first connecting electrode 42, the substrate 11 a, the second connecting electrode 44, and the second connecting conductor 43. And are connected to each other through. The first and second diode forming electrodes 16 and 17 can also be connected to the substrate electrode 31. The gate control circuit 19 is connected between the gate electrode 15 and the substrate electrode 31.

図７に示す実施例３の双方向スイッチ１０ｂの等価回路は、図６に示す実施例２の双方向スイッチ１０ａの等価回路と実質的に同一である。従って、図７に示す実施例３の双方向スイッチ１０ｂは、図５に示す実施例２の双方向スイッチ１０ａと同一の作用効果を有する。更に、図７の第１及び第２のダイオード形成用電極１６、１７は基板１１ａを介して相互に接続されているので、第１及び第２のダイオード形成用電極１６、１７の相互接続のためのスペースが小さくなり、双方向スイッチ１０ｂを更に小型化することができる。また基板１１ａの電位の安定化が良好に達成される。 The equivalent circuit of the bidirectional switch 10b of the third embodiment shown in FIG. 7 is substantially the same as the equivalent circuit of the bidirectional switch 10a of the second embodiment shown in FIG. Therefore, the bidirectional switch 10b of the third embodiment shown in FIG. 7 has the same operation and effect as the bidirectional switch 10a of the second embodiment shown in FIG. Furthermore, since the first and second diode forming electrodes 16 and 17 in FIG. 7 are connected to each other via the substrate 11a, the first and second diode forming electrodes 16 and 17 are connected to each other. , And the bidirectional switch 10b can be further downsized. In addition, stabilization of the potential of the substrate 11a is achieved satisfactorily.

図８に示す実施例４に従う変形された双方向スイッチ１０ｃは、変形された主半導体領域１２ａを除いて図５と同一に構成されている。変形された主半導体領域１２ａは主半導体スイッチング素子２０ｃと第１及び第２のダイオード２１ｃ，２２ｃの全てに含まれている。図８の主半導体領域１２ａは電子走行層としての第１の半導体層２８と電子供給層としての第２の半導体層２９との間に例えばアンドープＡｌＮ又はＡｌＩｎＧａＮから成る周知のスペーサー層５１を配置し、主半導体領域１２ａの最も上に、表面電荷のコントロールのため等の目的で例えばアンドープＡｌＧａＮから成るキャップ層５２を配置し、主半導体領域１２ａにおける第１及び第２の主電極１３，１４の下の部分に斜線を付けて示すｎ型不純物注入領域から成るコンタクト領域５３，５４を設け、この他は図５に示されている実施例２の主半導体領域１２と実質的に同一に形成したものである。スペーサー層５０は２ＤＥＧ層３０における電子の移動度の低下を抑制する機能を有する。コンタクト領域５３，５４は第１及び第２の主電極１３，１４の接触抵抗の低減に寄与する。なお、第１及び第２の主電極１３，１４の下に凹部を設け、凹部の中に第１及び第２の電極１３、１４を設けることもできる。
図８の双方向スイッチ１０ｃは図５の双方向スイッチ１０ａと同様な作用効果も有する。なお、図３及び図７の主半導体領域１２を図８の主半導体領域１２ａに変形することができる。 The modified bidirectional switch 10c according to the fourth embodiment shown in FIG. 8 has the same configuration as that of FIG. 5 except for the modified main semiconductor region 12a. The deformed main semiconductor region 12a is included in all of the main semiconductor switching element 20c and the first and second diodes 21c and 22c. In the main semiconductor region 12a of FIG. 8, a known spacer layer 51 made of, for example, undoped AlN or AlInGaN is disposed between the first semiconductor layer 28 as an electron transit layer and the second semiconductor layer 29 as an electron supply layer. A cap layer 52 made of, for example, undoped AlGaN is disposed on the top of the main semiconductor region 12a for the purpose of controlling surface charge, and below the first and second main electrodes 13 and 14 in the main semiconductor region 12a. 5 are provided with contact regions 53 and 54 each including an n-type impurity implantation region indicated by hatching, and the other portions are formed substantially the same as the main semiconductor region 12 of the second embodiment shown in FIG. It is. The spacer layer 50 has a function of suppressing a decrease in electron mobility in the 2DEG layer 30. The contact regions 53 and 54 contribute to reducing the contact resistance of the first and second main electrodes 13 and 14. In addition, a recessed part can be provided under the 1st and 2nd main electrodes 13 and 14, and the 1st and 2nd electrodes 13 and 14 can also be provided in a recessed part.
The bidirectional switch 10c shown in FIG. 8 has the same effect as the bidirectional switch 10a shown in FIG. Note that the main semiconductor region 12 of FIGS. 3 and 7 can be transformed into the main semiconductor region 12a of FIG.

図９の実施例５に従う双方向スイッチ１０ｄは、変形された主半導体領域１２ｂを除いて図５と同一に構成されている。図９の主半導体領域１２ｂはＭＥＳＦＥＴ（Metal Semiconductor Filed Effect Transistor）構成の主半導体スイッチング素子２０ｄが得られるように、例えばノンドープＧａＮから成る第１の半導体層２８ａと、該第１の半導体層２８ａにｎ型不純物（例えばＳｉ）をイオン注入することによって形成されたｎ型ＧａＮから成る第２の半導体層２９ａとから成る。図９の主半導体スイッチング素子２０ｄ、第１及び第２のダイオード２１ｄ，２２ｄは、主半導体領域１２ｂを除いて図５と同様に構成されている。   The bidirectional switch 10d according to the fifth embodiment of FIG. 9 has the same configuration as that of FIG. 5 except for the deformed main semiconductor region 12b. The main semiconductor region 12b in FIG. 9 includes a first semiconductor layer 28a made of, for example, non-doped GaN, and the first semiconductor layer 28a so as to obtain a main semiconductor switching element 20d having a MESFET (Metal Semiconductor Filed Effect Transistor) structure. and a second semiconductor layer 29a made of n-type GaN formed by ion implantation of an n-type impurity (for example, Si). The main semiconductor switching element 20d and the first and second diodes 21d and 22d in FIG. 9 are configured in the same manner as in FIG. 5 except for the main semiconductor region 12b.

図９の主半導体領域１２ｂにおける第２の半導体層２９ａはチャネル層即ち電流通路として機能する。主半導体スイッチング素子２０ｄを構成するショットキー電極から成るゲート電極１５の電位がソースとして機能する第１の主電極１３又は第２の主電極１４の電位と同一の場合（ノーマリ時）において第２の半導体層２９ｂの電流通路はオン状態に保たれる。ソースとして機能する第１の主電極１３又は第２の主電極１４に対してゲート電極１５が負電位になると、電界効果によって第２の半導体層２９ｂの電流通路がオフになる。従って、図９の主半導体スイッチング素子２０ｄは図３、図５の主半導体スイッチング素子２０，２０ａと同様に使用することができる。第１及び第２のダイオード形成用電極１６，１７は主半導体領域１２ｂにおける第２の半導体層２９ａにショットキー接触し、ショットキーダイオードを形成している。図９の主半導体スイッチング素子２０ｄ、第１及び第２のダイオード２１ｄ，２２ｄは、図５の主半導体スイッチング素子２０ａ、第１及び第２のダイオード２１ａ，２２ａと同様な機能を有するので、図９の双方向スイッチ１０ｄは図５の双方向スイッチ１０ａと同様な効果を有する。なお、図３、図７及び図８の主半導体領域１２，１２ａを図９の主半導体領域１２ｂに変形することができる。   The second semiconductor layer 29a in the main semiconductor region 12b of FIG. 9 functions as a channel layer, that is, a current path. When the potential of the gate electrode 15 composed of a Schottky electrode constituting the main semiconductor switching element 20d is the same as the potential of the first main electrode 13 or the second main electrode 14 functioning as a source (when normally), the second The current path of the semiconductor layer 29b is kept on. When the gate electrode 15 becomes a negative potential with respect to the first main electrode 13 or the second main electrode 14 functioning as a source, the current path of the second semiconductor layer 29b is turned off by the field effect. Accordingly, the main semiconductor switching element 20d of FIG. 9 can be used in the same manner as the main semiconductor switching elements 20 and 20a of FIGS. The first and second diode forming electrodes 16 and 17 are in Schottky contact with the second semiconductor layer 29a in the main semiconductor region 12b to form a Schottky diode. The main semiconductor switching element 20d and the first and second diodes 21d and 22d in FIG. 9 have the same functions as the main semiconductor switching element 20a and the first and second diodes 21a and 22a in FIG. The bidirectional switch 10d has the same effect as the bidirectional switch 10a of FIG. The main semiconductor regions 12 and 12a shown in FIGS. 3, 7, and 8 can be transformed into the main semiconductor region 12b shown in FIG.

図１０の実施例６に従う双方向スイッチ１０ｅは、変形された主半導体領域１２ｃ、ゲート電極１５ａ、第１及び第２のダイオード形成用電極１６ａ，１７ａを除いて図９と同一に構成されている。変形された主半導体領域１２ｃは、ｎ型の第２の半導体層２９ａの上に窒化物半導体（窒化物系半導体）から成る第１、第２及び第３のｐ型半導体層６１、６２，６３を有する。第１のｐ型半導体層６１は、ゲート電極１５ａとｎ型の第２の半導体層２９ａとの間に配置され、ｎ型の第２の半導体層２９ａとの間のｐｎ接合によって接合型電界効果トタンジスタから成る主半導体スイッチング素子20ｅを提供する。第２及び第３のｐ型半導体層６２，６３は第１及び第２のダイオード形成用電極１６ａ、１７ａとｎ型の第２の半導体層２９ａとの間に配置され、ｎ型の第２の半導体層２９ａとの間のｐｎ接合によって第１及び第２のダイオード２１ｅ，２２ｅを提供する。ゲート電極１５ａ、第１及び第２のダイオード形成用電極１６ａ，１７ａはそれぞれ第第１、第2及び第3のｐ型半導体層６１，６２，６３にオーミック接触している。図１０の主半導体スイッチング素子２０ｅのゲート電極15にゲート制御回路8からソースとして機能している第1又は第2の主電極１４、15に対して閾値電圧以上の電圧が印加されると、主半導体スイッチング素子２０ｅはオンとなり、それ以下でオフとなる。図１０の主半導体スイッチング素子２０ｅ、第１及び第２のダイオード２１ｅ，２２ｅは図５の主半導体スイッチング素子２０ａ、第１及び第２のダイオード２１ａ，２２ａと同様に動作するので、図１０の双方向スイッチ１０ｅは図５の双方向スイッチ１０ａと同様な効果を有する。なお、図１０から基板電極３１を省くことができる。また、第１のｐ型半導体層６１のみをゲート電極１５ａの下に配置し、第2及び第3のｐ型半導体層６２，６３を省き、第１及び第２のダイオード形成用電極１６ａ，１７ａをショットキー電極にすることができる。また、第2及び第3のｐ型半導体層６２，６３のみを第１及び第２のダイオード形成用電極１６ａ，１７ａの下に配置し、第１のｐ型半導体層６１を省き、ゲート電極１５ａをショットキー電極又は別のゲート手段にすることができる。   The bidirectional switch 10e according to the sixth embodiment of FIG. 10 has the same configuration as that of FIG. 9 except for the modified main semiconductor region 12c, the gate electrode 15a, and the first and second diode forming electrodes 16a and 17a. . The deformed main semiconductor region 12c includes first, second, and third p-type semiconductor layers 61, 62, 63 made of a nitride semiconductor (nitride-based semiconductor) on the n-type second semiconductor layer 29a. Have The first p-type semiconductor layer 61 is disposed between the gate electrode 15a and the n-type second semiconductor layer 29a, and has a junction field effect by a pn junction between the n-type second semiconductor layer 29a. A main semiconductor switching element 20e comprising a transistor is provided. The second and third p-type semiconductor layers 62 and 63 are disposed between the first and second diode forming electrodes 16a and 17a and the n-type second semiconductor layer 29a, and the n-type second semiconductor layer 29a is provided. The first and second diodes 21e and 22e are provided by a pn junction with the semiconductor layer 29a. The gate electrode 15a and the first and second diode forming electrodes 16a and 17a are in ohmic contact with the first, second and third p-type semiconductor layers 61, 62 and 63, respectively. When a voltage higher than the threshold voltage is applied to the gate electrode 15 of the main semiconductor switching element 20e of FIG. 10 from the gate control circuit 8 to the first or second main electrode 14, 15 functioning as a source, The semiconductor switching element 20e is turned on, and is turned off below that. The main semiconductor switching element 20e and the first and second diodes 21e and 22e in FIG. 10 operate in the same manner as the main semiconductor switching element 20a and the first and second diodes 21a and 22a in FIG. The direction switch 10e has the same effect as the bidirectional switch 10a of FIG. Note that the substrate electrode 31 can be omitted from FIG. Further, only the first p-type semiconductor layer 61 is disposed under the gate electrode 15a, the second and third p-type semiconductor layers 62 and 63 are omitted, and the first and second diode forming electrodes 16a and 17a. Can be used as Schottky electrodes. Further, only the second and third p-type semiconductor layers 62 and 63 are disposed below the first and second diode forming electrodes 16a and 17a, the first p-type semiconductor layer 61 is omitted, and the gate electrode 15a. Can be a Schottky electrode or another gate means.

図１１の実施例７に従う双方向スイッチ１０ｆは、変形された主半導体スイッチング素子２０ｆを除いて図５と同一に構成されている。変形された主半導体スイッチング素子２０ｆは、ゲート電極１５と主半導体領域１２との間に配置されたゲート絶縁膜７０を除いて図５と同一に構成されている。ゲート絶縁膜７０を伴った主半導体スイッチング素子２０ｆは、図５の主半導体スイッチング素子２０ａと同様に動作するので、図１１の実施例７に従う双方向スイッチ１０ｆは図５の双方向スイッチ１０ａと同様な効果を有する。なお、図１１のゲート絶縁膜７０と同様のものを図３、図７、図８、図９のゲート電極１５の下にも配置することができる。   A bidirectional switch 10f according to the seventh embodiment of FIG. 11 has the same configuration as that of FIG. 5 except for the modified main semiconductor switching element 20f. The modified main semiconductor switching element 20f has the same configuration as that of FIG. 5 except for the gate insulating film 70 disposed between the gate electrode 15 and the main semiconductor region 12. Since the main semiconductor switching element 20f with the gate insulating film 70 operates in the same manner as the main semiconductor switching element 20a of FIG. 5, the bidirectional switch 10f according to the seventh embodiment of FIG. 11 is the same as the bidirectional switch 10a of FIG. It has a great effect. Note that the same material as the gate insulating film 70 in FIG. 11 can be disposed under the gate electrode 15 in FIGS. 3, 7, 8, and 9.

本発明は上述の実施例に限定されるものではなく、例えば次の変形が可能なものである。
（１） 主半導体領域１２〜１２ｃをＧａＮ、ＡｌＧａＮ、ＩｎＧａＮ、ＡｌＩｎＧａＮ、ＡｌＮ、ＩｎＡｌＮ等の窒化物半導体又は窒化物系半導体、又はＡｌＰ、ＧａＰ、ＡｌＩｎＰ、ＧａＩｎＰ、ＡｌＧａＰ、ＡｌＧａＡｓ、ＧａＡｓ、ＡｌＡｓ、ＩｎＡｓ、ＩｎＰ、ＩｎＮ、ＧａＡｓＰ等の３−５族化合筒半導体、又はＺｎＯ等の２−６族化合物半導体、又は更に別の化合物半導体で形成することができる。
（２） 主半導体スイッチング素子２０〜２０ｆに周知のフィールドプレートを設けることができる。
（３） 実施例１〜４、及び７のＨＥＭＴ構成の主半導体領域１２、１２ａの第２の半導体層２９をｐ型半導体から成る正孔供給層に置き換えることができる。この場合には、２ＤＥＧ層３０に対応する領域に２次元キャリアガス層として２次元正孔ガス層が生じる。また、図９の実施例５のｎ型の第２の半導体層２９ａをｐ型半導体層に変形することもできる。また、図１０の実施例６のｎ型の第２の半導体層２９ａをｐ型半導体層に変形し、ｐ型半導体層６１，６２，６３をｎ型半導体層に変形することができる。
（４）図３、図５、図７、図８、図１１の実施例において、例えばゲート電極１５の下に対応させて第２の半導体層２９にリセスを形成して、このリセスの上にゲート電極１５を配置すること、又はゲート電極１５と第２の半導体層２９との間にｐ型半導体層を配置すること等によってノーマリオフ型のＨＥＭＴ構成の主半導体スイッチング素子を設けることができる。また、図９、図１０の実施例においても主半導体スイッチング素子２０ｄ，２０ｅをノーマリオフ型に変形することができる。 The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) The main semiconductor regions 12 to 12c are made of nitride semiconductors or nitride semiconductors such as GaN, AlGaN, InGaN, AlInGaN, AlN, InAlN, or AlP, GaP, AlInP, GaInP, AlGaP, AlGaAs, GaAs, AlAs, InAs , InP, InN, GaAsP, or the like, or a group 3-6 compound semiconductor, such as ZnO, or another compound semiconductor.
(2) A well-known field plate can be provided in the main semiconductor switching elements 20 to 20f.
(3) The second semiconductor layer 29 of the main semiconductor regions 12 and 12a having the HEMT configuration of the first to fourth and seventh embodiments can be replaced with a hole supply layer made of a p-type semiconductor. In this case, a two-dimensional hole gas layer is generated as a two-dimensional carrier gas layer in a region corresponding to the 2DEG layer 30. Also, the n-type second semiconductor layer 29a of the fifth embodiment shown in FIG. 9 can be transformed into a p-type semiconductor layer. In addition, the n-type second semiconductor layer 29a of Example 6 in FIG. 10 can be transformed into a p-type semiconductor layer, and the p-type semiconductor layers 61, 62, and 63 can be transformed into an n-type semiconductor layer.
(4) In the embodiments of FIGS. 3, 5, 7, 8, and 11, for example, a recess is formed in the second semiconductor layer 29 so as to correspond to under the gate electrode 15, and the recess is formed on the recess. By arranging the gate electrode 15 or arranging a p-type semiconductor layer between the gate electrode 15 and the second semiconductor layer 29, a main semiconductor switching element having a normally-off HEMT configuration can be provided. 9 and 10 also, the main semiconductor switching elements 20d and 20e can be modified to a normally-off type.

従来の双方向スイッチを示す回路である。It is a circuit which shows the conventional bidirectional switch. 別の従来の双方向スイッチを示す回路図である。It is a circuit diagram which shows another conventional bidirectional | two-way switch. 本発明の実施例１に従うゲート制御回路を伴った双方向スイッチを示す断面図である。It is sectional drawing which shows the bidirectional | two-way switch with the gate control circuit according to Example 1 of this invention. ゲート制御回路と電気回路を伴った図３の双方向スイッチの等価回路図である。FIG. 4 is an equivalent circuit diagram of the bidirectional switch of FIG. 3 with a gate control circuit and an electrical circuit. 本発明の実施例２に従うゲート制御回路を伴った双方向スイッチを示す断面図である。It is sectional drawing which shows the bidirectional | two-way switch with the gate control circuit according to Example 2 of this invention. ゲート制御回路を伴った図５の双方向スイッチの等価回路図である。FIG. 6 is an equivalent circuit diagram of the bidirectional switch of FIG. 5 with a gate control circuit. 本発明の実施例３に従うゲート制御回路を伴った双方向スイッチを示す断面図である。It is sectional drawing which shows the bidirectional | two-way switch with the gate control circuit according to Example 3 of this invention. 本発明の実施例４に従うゲート制御回路を伴った双方向スイッチを示す断面図である。It is sectional drawing which shows the bidirectional | two-way switch with the gate control circuit according to Example 4 of this invention. 本発明の実施例５に従うゲート制御回路を伴った双方向スイッチを示す断面図である。It is sectional drawing which shows the bidirectional | two-way switch with the gate control circuit according to Example 5 of this invention. 本発明の実施例６に従うゲート制御回路を伴った双方向スイッチを示す断面図である。It is sectional drawing which shows the bidirectional | two-way switch with the gate control circuit according to Example 6 of this invention. 本発明の実施例７に従うゲート制御回路を伴った双方向スイッチを示す断面図である。It is sectional drawing which shows the bidirectional | two-way switch with the gate control circuit according to Example 7 of this invention.

符号の説明Explanation of symbols

１０〜１０ｆ 双方向スイッチ
１２〜１２ｃ 主半導体領域
１３，１４ 第１及び第２の主電極
１５ ゲート電極
１６，１７ 第１及び第２のダイオード形成用電極 10 to 10 f Bidirectional switch 12 to 12 c Main semiconductor regions 13 and 14 First and second main electrodes 15 Gate electrodes 16 and 17 First and second diode forming electrodes

Claims (9)

導電性基板と、
前記導電性基板上に配置され、且つ第１の主面と該第１の主面に対向する第２の主面とを有し、且つ電流通路を形成するための少なくとも１つの半導体層を有し、前記第２の主面が前記導電性基板に電気的に結合されている主半導体領域と、
所定の間隔を有して前記主半導体領域の前記第１の主面上にそれぞれ配置され且つ前記主半導体領域の前記第１の主面にそれぞれオーミック接触している第１及び第２の主電極と、
前記主半導体領域の前記第１及び第２の主電極間部分を流れる電流を制御するために前記主半導体領域の前記第１の主面の前記第１及び第２の主電極の間に配置されたゲート手段と、
前記主半導体領域の前記第１の主面の前記第１の主電極を基準にして前記ゲート手段と反対側の位置に配置されており且つダイオードのアノードとしての機能を有している第１のダイオード形成用電極と、
前記主半導体領域の前記第１の主面の前記第２の主電極を基準にして前記ゲート手段と反対側の位置に配置されており且つダイオードのアノードとしての機能を有している第２のダイオード形成用電極と、
前記第１のダイオード形成用電極と前記第２のダイオード形成用電極とを相互に電気的に接続している接続手段と、
を備え、前記導電性基板は前記接続手段に電気的に結合されていることを特徴とする双方向スイッチ。 A conductive substrate ;
A first main surface and a second main surface opposite to the first main surface are disposed on the conductive substrate and have at least one semiconductor layer for forming a current path. A main semiconductor region in which the second main surface is electrically coupled to the conductive substrate ;
First and second main electrodes arranged on the first main surface of the main semiconductor region with a predetermined interval and in ohmic contact with the first main surface of the main semiconductor region, respectively. When,
Disposed between the first and second main electrodes of the first main surface of the main semiconductor region in order to control a current flowing through the portion between the first and second main electrodes of the main semiconductor region. Gate means,
The first semiconductor layer is disposed at a position opposite to the gate means with respect to the first main electrode on the first main surface of the main semiconductor region, and has a function as an anode of a diode . A diode forming electrode;
The second semiconductor element is disposed at a position opposite to the gate means with respect to the second main electrode on the first main surface of the main semiconductor region and has a function as an anode of a diode . A diode forming electrode;
And connection means are electrically connected to each other and said first diode forming electrode and the second diode-forming electrodes,
The bidirectional switch is characterized in that the conductive substrate is electrically coupled to the connection means. 更に、前記ゲート手段と前記接続手段との間に接続されたゲート制御回路を備えていることを特徴とする請求項１記載の双方向スイッチ。   2. The bidirectional switch according to claim 1, further comprising a gate control circuit connected between the gate means and the connection means. 前記主半導体領域は２次元キャリアガス層を生じさせることができる第１及び第２の半導体層を有していることを特徴とする請求項１又は２記載の双方向スイッチ。   The bidirectional switch according to claim 1 or 2, wherein the main semiconductor region has first and second semiconductor layers capable of generating a two-dimensional carrier gas layer. 前記主半導体領域は電流通路として機能する第１導電型半導体層を有していることを特徴とする請求項１又は２記載の双方向スイッチ。   3. The bidirectional switch according to claim 1, wherein the main semiconductor region has a first conductive semiconductor layer functioning as a current path. 前記ゲート手段は、前記主半導体領域の前記第１の主面にショットキー接触しているゲート電極であることを特徴とする請求項１又は２又は３又は４記載の双方向スイッチ。 5. The bidirectional switch according to claim 1, wherein the gate means is a gate electrode in Schottky contact with the first main surface of the main semiconductor region. 前記ゲート手段は、前記主半導体領域の前記第１の主面上に配置されたゲート絶縁膜と該ゲート絶縁膜上に配置されたゲート電極とから成ることを特徴とする請求項１又は２又は３又は４記載の双方向スイッチ。 The gate means comprises a gate insulating film disposed on the first main surface of the main semiconductor region and a gate electrode disposed on the gate insulating film. 3. The bidirectional switch according to 3 or 4. 前記第１及び第２のダイオード形成用電極は、前記主半導体領域の前記第１の主面にショットキー接触している電極であることを特徴とする請求項１又は２又は３又は４又は５記載の双方向スイッチ。 The first and second diode forming electrodes are electrodes that are in Schottky contact with the first main surface of the main semiconductor region, respectively. Bidirectional switch as described. 前記主半導体領域は、更にｐｎ接合を得るために前記第１及び第２のダイオード形成用電極と前記第１導電型半導体層との間に第１及び第２の第２導電型半導体層を有し、
前記第１及び第２のダイオード形成用電極は前記第１及び第２の第２導電型半導体層にオーミック接触した電極であることを特徴とする請求項４記載の双方向スイッチ。 The main semiconductor region further includes first and second second conductive semiconductor layers between the first and second diode forming electrodes and the first conductive semiconductor layer in order to obtain a pn junction. And
5. The bidirectional switch according to claim 4, wherein the first and second diode forming electrodes are electrodes in ohmic contact with the first and second second conductive type semiconductor layers. 電気回路の電流をオン・オフするための双方向スイッチであって、
第１の主面と該第１の主面に対向する第２の主面とを有し且つ電流通路を形成するための少なくとも１つの半導体層を有している主半導体領域と、
所定の間隔を有して前記主半導体領域の前記第１の主面上にそれぞれ配置され且つ前記主半導体領域の前記第１の主面にそれぞれオーミック接触している第１及び第２の主電極と、
前記主半導体領域の前記第１及び第２の主電極間部分を流れる電流を制御するために前記主半導体領域の前記第１の主面の前記第１及び第２の主電極の間に配置されたゲート手段と、
前記主半導体領域の前記第１の主面の前記第１の主電極を基準にして前記ゲート手段と反対側の位置に配置された第１のダイオード形成用電極と、
前記主半導体領域の前記第１の主面の前記第２の主電極を基準にして前記ゲート手段と反対側の位置に配置された第２のダイオード形成用電極と、
前記第１のダイオード形成用電極と前記第２のダイオード形成用電極とを相互に接続している接続手段と
を備え、前記接続手段は、前記主半導体領域の前記第２の主面に電気的及び機械的に結合された一方の主面と該一方の主面に対向する他方の主面とを有する導電性基板と、前記導電性基板の前記他方の主面に形成された補助電極と、前記第１のダイオード形成用電極を前記導電性基板に電気的に接続する導体と、前記第２のダイオード形成用電極を前記導電性基板に電気的に接続する導体とから成ることを特徴とする双方向スイッチ。 A bidirectional switch for turning on and off the current of an electric circuit ,
A main semiconductor region having a first main surface and a second main surface opposite to the first main surface and having at least one semiconductor layer for forming a current path ;
First and second main electrodes arranged on the first main surface of the main semiconductor region with a predetermined interval and in ohmic contact with the first main surface of the main semiconductor region, respectively. And
Disposed between the first and second main electrodes of the first main surface of the main semiconductor region in order to control a current flowing through the portion between the first and second main electrodes of the main semiconductor region. Gate means ,
A first diode forming electrode disposed at a position opposite to the gate means with respect to the first main electrode of the first main surface of the main semiconductor region ;
A second diode-forming electrode disposed at a position opposite to the gate means with respect to the second main electrode of the first main surface of the main semiconductor region ;
Connection means for connecting the first diode forming electrode and the second diode forming electrode to each other;
And the connecting means includes a first main surface electrically and mechanically coupled to the second main surface of the main semiconductor region, and a conductive surface having the other main surface facing the one main surface. A conductive substrate, an auxiliary electrode formed on the other main surface of the conductive substrate, a conductor for electrically connecting the first diode forming electrode to the conductive substrate, and the second diode formation A bidirectional switch comprising a conductor for electrically connecting a working electrode to the conductive substrate.
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5552230B2 (en) * 2006-11-20 2014-07-16 パナソニック株式会社 Semiconductor device and driving method thereof
DE112009005412B4 (en) * 2009-12-03 2021-09-16 Snaptrack, Inc. Side emitter and collector transistor and manufacturing process
JP4968322B2 (en) * 2009-12-28 2012-07-04 サンケン電気株式会社 AC-DC converter
JP5845568B2 (en) * 2010-11-02 2016-01-20 富士通株式会社 Semiconductor device and manufacturing method thereof
US9673285B2 (en) 2011-11-21 2017-06-06 Sensor Electronic Technology, Inc. Semiconductor device with low-conducting buried and/or surface layers
US9647076B2 (en) 2011-11-21 2017-05-09 Sensor Electronic Technology, Inc. Circuit including semiconductor device with multiple individually biased space-charge control electrodes
JP5659182B2 (en) 2012-03-23 2015-01-28 株式会社東芝 Nitride semiconductor device
FR2998713B1 (en) 2012-11-26 2015-01-16 Commissariat Energie Atomique BIDIRECTIONAL CURRENT TRANSISTOR WITH HIGH ELECTRONIC MOBILITY OPTIMIZED
WO2016100805A1 (en) * 2014-12-19 2016-06-23 Sensor Electronic Technology, Inc. Semiconductor device with multiple space-charge control electrodes
CN107395195B (en) * 2016-05-16 2020-11-13 上海瀚薪科技有限公司 Wide-energy-gap semiconductor element with adjustable voltage level
EP3605594B1 (en) * 2017-03-31 2024-05-29 Panasonic Holdings Corporation Bidirectional switch and bidirectional switch device comprising same
US10276576B2 (en) * 2017-07-05 2019-04-30 Micron Technology, Inc. Gated diode memory cells
US11477889B2 (en) 2018-06-28 2022-10-18 Black & Decker Inc. Electronic switch module with an integrated flyback diode
CN115548014B (en) * 2021-05-25 2023-12-29 英诺赛科(苏州)科技有限公司 Nitride-based bidirectional switching device and method of manufacturing the same
EP4364205A1 (en) 2021-06-28 2024-05-08 Enphase Energy, Inc. Gallium nitride bi-directional high electron mobility transistor substrate voltage management circuit
CN114284355A (en) * 2021-12-27 2022-04-05 西交利物浦大学 Dual-gate MIS-HEMT device, bidirectional switch device and preparation method thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791072A (en) * 1984-06-15 1988-12-13 American Telephone And Telegraph Company, At&T Bell Laboratories Method for making a complementary device containing MODFET
US5536977A (en) * 1993-11-30 1996-07-16 Siliconix Incorporated Bidirectional current blocking MOSFET for battery disconnect switching
US6252258B1 (en) * 1999-08-10 2001-06-26 Rockwell Science Center Llc High power rectifier
JP4177048B2 (en) * 2001-11-27 2008-11-05 古河電気工業株式会社 Power converter and GaN-based semiconductor device used therefor
JP4748498B2 (en) * 2002-12-05 2011-08-17 古河電気工業株式会社 GaN-based semiconductor device with current breaker
JP4089419B2 (en) * 2002-12-19 2008-05-28 株式会社村田製作所 Semiconductor device and manufacturing method thereof
EP1630872B1 (en) * 2003-06-05 2016-12-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and its manufacturing method
JP4123274B2 (en) * 2003-06-23 2008-07-23 サンケン電気株式会社 AC switch
JP4530171B2 (en) * 2003-08-08 2010-08-25 サンケン電気株式会社 Semiconductor device
JP4810072B2 (en) * 2004-06-15 2011-11-09 株式会社東芝 Nitrogen compound-containing semiconductor devices
US7135740B2 (en) * 2004-09-27 2006-11-14 Teledyne Licensing, Llc High voltage FET switch with conductivity modulation
JP5055773B2 (en) * 2006-02-02 2012-10-24 サンケン電気株式会社 Semiconductor element
US8823057B2 (en) * 2006-11-06 2014-09-02 Cree, Inc. Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
JP5439725B2 (en) * 2008-02-20 2014-03-12 サンケン電気株式会社 Semiconductor switching device

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