CN116860068A - Clock positioning method, circuit and device - Google Patents

Clock positioning method, circuit and device Download PDF

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Publication number
CN116860068A
CN116860068A CN202310815100.9A CN202310815100A CN116860068A CN 116860068 A CN116860068 A CN 116860068A CN 202310815100 A CN202310815100 A CN 202310815100A CN 116860068 A CN116860068 A CN 116860068A
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China
Prior art keywords
clock
signal
module
tested
detection module
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CN202310815100.9A
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郑杰鸣
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Unisoc Chongqing Technology Co Ltd
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Unisoc Chongqing Technology Co Ltd
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Priority to CN202310815100.9A priority Critical patent/CN116860068A/en
Publication of CN116860068A publication Critical patent/CN116860068A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The present application relates to the field of chip clocks, and in particular, to a clock positioning method, circuit and device. A clock positioning method applied to a control register, the method comprising: sequentially sending each level of selection signals to a debugging bus, wherein the selection signals are used for determining clock signals to be detected of each level in the debugging bus, and the clock signals to be detected are sent to a clock detection module by the debugging bus; and receiving the clock frequency sent by the clock detection module, determining a target clock signal according to the clock frequency, and determining the clock frequency by the clock detection module according to the clock signal to be detected.

Description

Clock positioning method, circuit and device
[ field of technology ]
The present application relates to the field of chip clocks, and in particular, to a clock positioning method, circuit and device.
[ background Art ]
When the integrated circuit chip works, the operation of all subsystems in the chip and the like need to be controlled by a clock. If the clock is out of order, the chip will not work properly. The chip clock problem is often very difficult to locate, and the circuit design is complex and the cost is high. In the related art, accurate, effective and low-cost positioning cannot be achieved for the problem clock.
[ application ]
The embodiment of the application provides a clock positioning method, a clock positioning circuit and a clock positioning device, which are used for solving the problem that clocks cannot be accurately positioned in the prior art.
In a first aspect, an embodiment of the present application provides a clock positioning method, where the method is applied to a control register, and the method includes:
sequentially sending each level of selection signals to a debugging bus, wherein the selection signals are used for determining clock signals to be detected of each level in the debugging bus, and the clock signals to be detected are sent to a clock detection module by the debugging bus;
and receiving the clock frequency sent by the clock detection module, determining a target clock signal according to the clock frequency, and determining the clock frequency by the clock detection module according to the clock signal to be detected.
Optionally, the selecting signal is used for determining clock signals to be tested of each stage in the debug bus, including:
when the selection signal is a first-stage selection signal, determining all first-stage clock signals in the debug bus as the clock signals to be tested;
and when the selection signal is a non-first-stage selection signal, determining the clock signal to be tested of the stage in the debugging bus according to the signal frequency of the upper-stage clock to be tested sent by the clock detection module.
Optionally, the determining, in the debug bus, the clock signal to be tested of the present stage according to the signal frequency of the upper stage clock to be tested sent by the clock detection module includes:
responding to the clock frequency of the upper-level clock signal to be detected sent by the clock detection module, and determining an error clock signal with an error occurring in the clock frequency according to the corresponding standard clock frequency;
and determining all clock signals of the next stage in the error clock signals as clock signals to be detected of the stage.
Optionally, determining the target clock signal according to the clock frequency includes:
and determining the target clock signal according to the clock frequency of the final stage clock signal to be tested when the clock frequency is the clock frequency of the final stage clock signal to be tested.
Optionally, before the receiving the clock frequency sent by the clock detection module, the method further includes:
and sending a start signal to the clock detection module, wherein the start signal is used for indicating the clock detection module to start calculating the clock frequency of the clock signal to be detected.
In a second aspect, an embodiment of the present application provides a clock positioning method, where the method is applied to a clock detection module, and the method includes:
receiving all levels of clock signals to be tested sent by a debugging bus, and calculating the clock frequency of the all levels of clock signals to be tested;
outputting the clock frequency of each stage of clock signals to be tested to a control register, and determining a target clock signal by the control register;
the clock signal to be tested is sent by the debugging bus according to the selection signal sent by the control register.
Optionally, the calculating the clock frequency of the clock signal to be measured at each stage includes:
responding to a starting signal, respectively controlling a reference clock module and a clock module to be detected to perform counting, wherein the reference clock module is used for counting rising edges of a reference clock signal, and the clock module to be detected is used for counting rising edges of the clock signal to be detected;
when the clock module to be tested stops counting, outputting clock frequency according to the counting result of the clock module to be tested;
and sending a stop signal to the clock module to be tested when the count of the reference clock module reaches a preset threshold, wherein the stop signal is used for indicating the clock module to be tested to stop counting.
In a third aspect, an embodiment of the present application provides a clock positioning circuit, including:
the output end of the control register is connected with the debugging bus and the input end of the clock detection module, the input end of the control register is connected with the output end of the clock detection module and is used for sending each level of selection signals to the debugging bus and determining a target clock signal according to the clock signal to be detected sent by the clock detection module;
the output end of the debugging bus is connected with the clock detection module and is used for sequentially screening clock signals to be detected in each stage of clock signals according to the selection signals sent by the control register and outputting the clock signals to the clock detection module;
the clock detection module is used for calculating the clock frequency of each stage of clock signals to be detected, which are sent by the debug bus, and outputting the clock frequency to the control register.
Optionally, the clock detection module further includes:
the output end of the reference clock module is connected with the clock module to be tested and is used for executing counting according to the reference clock signal, and when the reference clock signal count reaches a preset threshold value, a stop signal is sent to the clock module to be tested;
and the clock module to be tested is used for counting the clock to be tested, stopping counting and outputting the clock frequency when receiving the stop signal sent by the reference clock module.
Optionally, the clock detection module further includes:
and the output end of the reference clock generation module is connected with the reference clock module and is used for outputting a reference clock signal to the reference clock module.
Optionally, the clock positioning circuit further includes:
the input end of the reference clock module and the input end of the clock module to be tested are respectively connected with the control register and used for executing counting after receiving a start signal sent by the control register.
In a fourth aspect, an embodiment of the present application provides an electronic device, including:
at least one processor; and
at least one memory communicatively coupled to the processor, wherein:
the memory stores program instructions executable by the processor, the processor invoking the program instructions to be able to perform the method according to any of the first or second aspects.
In a fifth aspect, an embodiment of the present application provides a storage medium, where the storage medium includes a stored program, where the program, when executed, controls a device in which the storage medium is located to perform a method according to any one of the first aspect or the second aspect.
By the method, clock signals in the chip are gated step by step, and clock frequencies of clock signals to be measured of all stages are sequentially measured through the clock detection module, so that high-precision positioning of target clock signals is realized. Meanwhile, the circuit is simple and low in cost.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a clock positioning circuit according to an embodiment of the present application;
FIG. 2 is a flowchart of a clock positioning method according to an embodiment of the present application;
FIG. 3 is a flowchart of another clock positioning method according to an embodiment of the present application;
FIG. 4 is a schematic diagram of another clock positioning circuit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
[ detailed description ] of the application
For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, a schematic diagram of a clock positioning circuit according to an embodiment of the present application is provided. As shown in fig. 1, the clock positioning circuit includes a control register 110, a debug bus 120, and a clock detection module 130. The clock detection module 130 further includes a reference clock module 131 and a clock module to be tested 132.
The output end of the control register 110 is connected with the input end of the debug bus, and is used for sending the selection signals of each stage to the debug bus so as to gate out the clock signals in the chip step by step according to the actual requirements. The input end of the control register is connected with the clock detection module, the clock frequency of the clock signal to be detected sent by the clock detection module is received, and the control register can determine the selection signal or the target clock signal according to the received clock frequency.
An output of the debug bus 120 is connected to a clock detection module. All clock signals inside the chip are stored in the debug bus, and the clock signals are divided into different levels. The debug bus is used for screening out a target clock signal of a corresponding level from clock signals stored in the debug bus according to the selection signals sent by the control register, and sending the target clock signal to the clock detection module to perform clock detection.
The output end of the clock detection module 130 is connected with the control register, and is used for receiving the clock signal to be detected output by the debug bus, measuring the clock frequency of the clock signal to be detected, and outputting the measurement result to the control register.
The clock detection module is used for controlling the register to determine the selection signal for screening the next stage clock signal to be detected or directly determine the target clock signal after measuring the clock signal to be detected.
Specifically, after receiving the clock frequency sent by the clock detection module, the control register determines an error clock signal with possible error of the clock frequency in the stage clock signal. If the error clock signal is the last stage clock signal, the error clock signal can be directly determined as a target clock signal; if the error clock signal is not the last-stage clock signal, the error clock signal is further provided with one or more stages and a plurality of items of clock signals, the next stage of clock signal in the error clock signal is determined as a target clock signal by continuously sending a selection signal to the debug bus, the clock signal is screened to a clock detection module to measure the clock frequency, and the steps are repeated for a plurality of times until the error signal is the last-stage clock signal, and the last-stage clock signal is determined as the target clock signal.
In order to perform clock measurement, the clock detection module 130 further includes a reference clock module 131 and a clock module to be measured 132.
The input end of the reference clock module is connected with the reference clock generation module, and the output end of the reference clock module is connected with the clock module to be tested. The output end of the clock module to be tested is connected with the control register. The reference clock module and the clock module to be tested are also connected with the input end of the control register.
The reference clock module receives the reference clock sent by the reference clock generating module through the input end. The clock module to be tested receives the clock signal to be tested input by the debug bus through the input end.
When specifically performing clock detection, the control register may send a start signal to a reference clock module and a clock module to be detected in the clock detection module. The reference clock module counts rising edges of the reference clock in response to the start signal. The clock module to be measured responds to the starting signal, and the rising edge of the clock signal to be measured starts to be counted. And when the count of the reference clock module reaches a preset threshold, sending a stop signal to the clock module to be tested. And the clock module to be tested stops counting the clock signal to be tested after receiving the stop signal, and determines the clock frequency of the clock signal to be tested according to the completed counting result and outputs the clock frequency to the control register.
As shown in fig. 2, a clock positioning method according to an embodiment of the present application is applied to a control register, and includes the following specific steps:
s201, sequentially sending each stage of selection signals to the debug bus.
Specifically, the selection signal is used for determining clock signals to be detected of each stage in the debug bus, and the clock signals to be detected are sent to the clock detection module by the debug bus.
All clock signals inside the chip are pre-pulled into the debug bus. The clock signal in the debug bus is divided into several levels. The control register determines the clock signals to be tested of the corresponding level in the clock signals of the level corresponding to the debug bus by sending selection signals of different levels.
When the selection signal is the first-stage selection signal, that is, when the highest-stage clock signal to be tested is screened in the debug bus, the first-stage selection signal determines all first-stage clock signals in the debug bus as the clock signals to be tested. And the debug bus can send all first-stage clock signals to the clock detection module to execute frequency measurement as clock signals to be tested according to the first-stage selection signals.
When the selection signal is a non-first-stage selection signal, the signal frequency of the upper-stage clock to be detected, which is sent by the clock detection module, is needed to be determined in advance. For example, when the selection signal is a three-level selection signal, the signal frequency of the two-level clock signal to be measured sent by the clock detection module is required to determine the three-level selection signal.
And determining a clock signal to be tested in a corresponding level according to the non-first layer selection signal by the debug bus, and sending the clock signal to be tested to the clock detection module to execute frequency measurement.
Optionally, since the bit width of each level is generally 32 bits, that is, the clock signals in each level include 32 bits, the control register may further gate the determined clock signals to be tested to the clock detection module one by sending a bit level selection signal to the debug bus to perform clock measurement until the measurement of all the clock signals to be tested is completed.
S202, receiving the clock frequency sent by the clock detection module, and determining a target clock signal according to the clock frequency.
Specifically, after executing S201 to sequentially send each level of selection signals to the debug bus, the debug bus will send the corresponding clock signal to be tested to the clock detection module. The clock detection module measures the clock signal to be detected, and the clock frequency of the clock signal to be detected is obtained and sent back to the control register.
The control register receives the clock frequency transmitted by the clock detection module, determines the target clock frequency according to the clock frequency, or determines the selection signal of the next stage according to the clock frequency as described in S201.
When the clock frequency is the clock frequency of the final stage clock signal to be measured, determining a target clock signal according to the clock frequency of the final stage clock signal to be measured; when the clock frequency is not the clock frequency of the clock signal to be measured of the final stage, determining the selection signal of the next stage according to the clock frequency.
For example, when the clock signal is divided into three stages, when the received clock frequency is the clock frequency of the second-stage clock signal to be detected, determining a third-stage selection signal according to the clock frequency, and screening the third-stage clock signal to be detected; when the received clock frequency is the clock frequency of the three-stage clock signal to be detected, the target clock signal is determined directly according to the clock.
Specifically, in response to the clock frequency of the clock signal to be detected sent by the clock detection module, the clock signal with the clock frequency error is determined from the clock frequency in combination with the standard clock frequency stored in the control register. If the clock signal to be measured which is measured at this time is already the last stage clock signal to be measured, directly determining the clock signal with error as a target clock signal; if the clock signal to be measured which is measured at this time is not the last stage clock signal, all clock signals of the next stage in the clock signals with errors are determined as the clock signals to be measured, and the measurement is continuously carried out through selection signal screening.
As shown in fig. 3, a clock positioning method according to an embodiment of the present application is applied to a clock detection module, and the specific steps of the method include: reference clock module and clock module to be tested
S301, receiving clock signals to be detected sent by a debugging bus at all levels, and calculating the clock frequency of the clock signals to be detected at all levels.
Specifically, the reference clock module receives a reference clock signal, and the clock module to be tested receives a clock signal to be tested sent by the debug bus.
The reference clock module counts rising edges of the reference clock in response to the start signal. The clock module to be measured responds to the starting signal, and the rising edge of the clock signal to be measured starts to be counted. And when the count of the reference clock module reaches a preset threshold, sending a stop signal to the clock module to be tested. And the clock module to be tested stops counting the clock signal to be tested after receiving the stop signal, and determines the clock frequency of the clock signal to be tested according to the completed counting result.
S302, outputting the clock frequency of the clock signals to be tested at each stage to a control register, and determining a target clock signal by the control register.
Specifically, the clock detection module outputs the calculated clock frequency to the control register. When the clock frequency is the frequency of the final stage clock signal to be measured, the clock frequency is used for directly determining the target clock signal; when the clock frequency is not the frequency of the clock signal to be measured of the final stage, the clock frequency is used for determining the selection signal and determining the clock signal to be measured of the next stage.
According to the embodiment of the application, the clock signals in the chip are gated step by step, and the clock frequency of the clock signals to be detected of each stage is sequentially measured through the clock detection module, so that the high-precision positioning of the target clock signals is realized. Meanwhile, the circuit is simple and low in cost.
As shown in fig. 4, a schematic diagram of a specific clock positioning circuit according to the present application is provided. Referring to fig. 4, the clock signals stored in the debug bus are divided into three levels, namely a system level clock signal (dbg_bus_sys_array), a module level clock signal (dbg_bus_mod_array), and a signal level clock signal (dbg_bus_sig_array). Wherein the first stage is a system stage, the second stage is a module stage, and the last stage is a signal stage. The control register pulls the clock signal under test of the corresponding level in the debug bus by sending three levels of select signals (sys_sel, mod_sel, sig_sel) respectively.
The bit width of each level is 32 bits, that is, the clock signals in each level contain 32 bits, so the control register also sequentially outputs the screened clock signals to be tested to the clock detection module by sending a bit level selection signal (bit_sel).
Specifically, the control register first sends a system level select signal and a bit level select signal to the debug bus. The debug bus determines all the system-level clock signals, determines the system-level clock signals as system-level clock signals to be tested, and sequentially outputs the system-level clock signals to be tested to the clock detection module to execute clock frequency measurement according to the bit-level selection signals.
The clock detection module receives a start signal (start) sent by the control register, sequentially performs clock frequency measurement on clock signals to be detected of each system level, and outputs the measured clock frequency to the control register.
After receiving the clock frequency output by the clock detection module aiming at each system level clock signal to be detected, the control register determines the system level clock signal with the frequency error, and further detects all module level clock signals in the system level clock signal with the frequency error as the module level clock signal to be detected by sending a module level selection signal and a bit level clock signal to the debug bus.
For example, after the control register receives the clock frequencies measured by the clock detection module on the 32 system level clock signals, if it determines that there is an abnormality in the 20 th system level clock signal, that is, dbg_bus_sys_array [20], it needs to issue a module level selection signal to the debug bus, and all module level clock signals (dbg_bus_mod_array [1] -dbg_bus_mod_array [32 ]) in the 20 th system level clock signal are taken as clock signals to be tested, and are selected from the debug bus.
After receiving the module level selection signals sent by the control register, the debug bus sequentially sends all module level clock signals in the corresponding system level clock signals to the clock detection module to execute frequency detection through the bit level selection signals.
The clock detection module sequentially calculates the clock frequency of the module-level clock signals to be detected after receiving the clock signals to be detected in the module-level clock signals sent by the debug bus, and outputs the calculated clock frequency to the control register.
After receiving the clock frequency output by the clock detection module aiming at the clock signals to be detected of each module stage, the control register determines the module stage clock signal with errors, and sends a signal stage selection signal and a bit stage clock signal to the debug bus to execute further detection on all signal stage clock signals under the abnormal module stage clock signal as the signal stage clock signal to be detected.
After receiving the signal level selection signals sent by the control register, the debug bus sequentially sends all signal level clock signals in the corresponding module level clock signals to the clock detection module to execute frequency detection through the bit level selection signals.
The clock detection module sequentially calculates the clock frequency of each signal level clock signal after receiving the clock signal to be detected, namely, the signal level clock signal sent by the debug bus, and outputs the calculated clock frequency to the control register.
After receiving the clock frequency output by the clock detection module for each signal level clock signal to be detected, the control register determines the signal level clock signal with error, for example, dbg_bus_sig_array [5]. Because the signal level clock signal is the last-stage clock signal, the signal level clock signal can be directly determined as a target clock signal, and the accurate positioning of the problem clock is completed.
Fig. 5 is a schematic structural view of an embodiment of the electronic device of the present specification. The electronic device may be implemented as the terminal device described above. As shown in fig. 5, the electronic device may include at least one processor; and at least one memory communicatively coupled to the processing unit, wherein: the memory stores program instructions executable by the processing unit, and the processor invokes the program instructions to perform the clock positioning method provided in this embodiment.
The electronic device may be a device capable of performing an intelligent dialogue with a user, for example: the cloud server, the embodiment of the present disclosure does not limit the specific form of the electronic device. It is understood that the electronic device herein is the machine mentioned in the method embodiment.
Fig. 5 shows a block diagram of an exemplary electronic device suitable for use in implementing embodiments of the present description. The electronic device shown in fig. 5 is only an example and should not be construed as limiting the functionality and scope of use of the embodiments herein.
As shown in fig. 5, the electronic device is in the form of a general purpose computing device. Components of an electronic device may include, but are not limited to: one or more processors 510, a communication interface 520, a memory 530, and a communication bus 540 connecting the different system components (including the memory 530, the communication interface 520, and the processor 510).
Communication bus 540 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include industry Standard architecture (Industry Standard Architecture; hereinafter ISA) bus, micro channel architecture (Micro Channel Architecture; hereinafter MAC) bus, enhanced ISA bus, video electronics standards Association (Video Electronics Standards Association; hereinafter VESA) local bus, and peripheral component interconnect (Peripheral Component Interconnection; hereinafter PCI) bus.
Electronic devices typically include a variety of computer system readable media. Such media can be any available media that can be accessed by the electronic device and includes both volatile and nonvolatile media, removable and non-removable media.
Memory 530 may include computer system readable media in the form of volatile memory, such as random access memory (Random Access Memory; hereinafter: RAM) and/or cache memory. The electronic device may further include other removable/non-removable, volatile/nonvolatile computer system storage media. Memory 530 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the present description.
A program/utility having a set (at least one) of program modules may be stored in the memory 530, such program modules include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules typically carry out the functions and/or methods of the embodiments described herein.
The processor 510 executes various functional applications and data processing by running programs stored in the memory 530, for example, implementing the clock positioning method provided in the embodiment shown in the present specification.
Embodiments of the present specification provide a non-transitory computer readable storage medium storing computer instructions that cause a computer to perform the clock positioning method provided by the embodiments of the present specification.
The non-transitory computer readable storage media described above may employ any combination of one or more computer readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory; EPROM) or flash Memory, an optical fiber, a portable compact disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for the present specification may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (Local Area Network; hereinafter: LAN) or a wide area network (Wide Area Network; hereinafter: WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present specification, the meaning of "plurality" means at least two, for example, two, three, etc., unless explicitly defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present specification in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present specification.
Depending on the context, the word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection". Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.
It should be noted that, the terminals in the embodiments of the present disclosure may include, but are not limited to, a personal Computer (Personal Computer; hereinafter referred to as a PC), a personal digital assistant (Personal Digital Assistant; hereinafter referred to as a PDA), a wireless handheld device, a Tablet Computer (Tablet Computer), a mobile phone, an MP3 player, an MP4 player, and the like.
In the embodiments provided in the present specification, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
In addition, each functional unit in each embodiment of the present specification may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a Processor (Processor) to perform part of the steps of the methods described in the embodiments of the present specification.
The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims (13)

1. A clock positioning method, the method being applied to a control register, the method comprising:
sequentially sending each level of selection signals to a debugging bus, wherein the selection signals are used for determining clock signals to be detected of each level in the debugging bus, and the clock signals to be detected are sent to a clock detection module by the debugging bus;
and receiving the clock frequency sent by the clock detection module, determining a target clock signal according to the clock frequency, and determining the clock frequency by the clock detection module according to the clock signal to be detected.
2. The method of claim 1, wherein the selecting signal for asserting a clock signal under test for each stage in the debug bus comprises:
when the selection signal is a first-stage selection signal, determining all first-stage clock signals in the debug bus as the clock signals to be tested;
and when the selection signal is a non-first-stage selection signal, determining the clock signal to be tested of the stage in the debugging bus according to the signal frequency of the upper-stage clock to be tested sent by the clock detection module.
3. The method according to claim 2, wherein determining the current level of the clock signal to be tested in the debug bus according to the signal frequency of the upper level of the clock to be tested sent by the clock detection module includes:
responding to the clock frequency of the upper-level clock signal to be detected sent by the clock detection module, and determining an error clock signal with an error occurring in the clock frequency according to the corresponding standard clock frequency;
and determining all clock signals of the next stage in the error clock signals as clock signals to be detected of the stage.
4. The method of claim 1, wherein determining the target clock signal based on the clock frequency comprises:
and determining the target clock signal according to the clock frequency of the final stage clock signal to be tested when the clock frequency is the clock frequency of the final stage clock signal to be tested.
5. The method of claim 1, wherein prior to receiving the clock frequency transmitted by the clock detection module, the method further comprises:
and sending a start signal to the clock detection module, wherein the start signal is used for indicating the clock detection module to start calculating the clock frequency of the clock signal to be detected.
6. A clock positioning method, wherein the method is applied to a clock detection module, the method comprising:
receiving all levels of clock signals to be tested sent by a debugging bus, and calculating the clock frequency of the all levels of clock signals to be tested;
outputting the clock frequency of each stage of clock signals to be tested to a control register, and determining a target clock signal by the control register;
the clock signal to be tested is sent by the debugging bus according to the selection signal sent by the control register.
7. The method of claim 6, wherein said calculating the clock frequency of each stage of said clock signal under test comprises:
responding to a starting signal, respectively controlling a reference clock module and a clock module to be detected to perform counting, wherein the reference clock module is used for counting rising edges of a reference clock signal, and the clock module to be detected is used for counting rising edges of the clock signal to be detected;
when the clock module to be tested stops counting, outputting clock frequency according to the counting result of the clock module to be tested;
and sending a stop signal to the clock module to be tested when the count of the reference clock module reaches a preset threshold, wherein the stop signal is used for indicating the clock module to be tested to stop counting.
8. A clock positioning circuit, comprising:
the output end of the control register is connected with the debugging bus and the input end of the clock detection module, the input end of the control register is connected with the output end of the clock detection module and is used for sending each level of selection signals to the debugging bus and determining a target clock signal according to the clock signal to be detected sent by the clock detection module;
the output end of the debugging bus is connected with the clock detection module and is used for sequentially screening clock signals to be detected in each stage of clock signals according to the selection signals sent by the control register and outputting the clock signals to the clock detection module;
the clock detection module is used for calculating the clock frequency of each stage of clock signals to be detected, which are sent by the debug bus, and outputting the clock frequency to the control register.
9. The circuit of claim 8, wherein the clock detection module further comprises:
the output end of the reference clock module is connected with the clock module to be tested and is used for executing counting according to the reference clock signal, and when the reference clock signal count reaches a preset threshold value, a stop signal is sent to the clock module to be tested;
and the clock module to be tested is used for counting the clock to be tested, stopping counting and outputting the clock frequency when receiving the stop signal sent by the reference clock module.
10. The circuit of claim 9, wherein the clock detection module further comprises:
and the output end of the reference clock generation module is connected with the reference clock module and is used for outputting a reference clock signal to the reference clock module.
11. The circuit of claim 9, wherein the clock positioning circuit comprises:
the input end of the reference clock module and the input end of the clock module to be tested are respectively connected with the control register and used for executing counting after receiving a start signal sent by the control register.
12. An electronic device, comprising:
at least one processor; and
at least one memory communicatively coupled to the processor, wherein:
the memory stores program instructions executable by the processor, the processor invoking the program instructions capable of performing the method of any of claims 1-5 or claims 6-7.
13. A storage medium comprising a stored program, wherein the program, when run, controls a device in which the storage medium is located to perform the method of any one of claims 1 to 5 or claims 6 to 7.
CN202310815100.9A 2023-07-04 2023-07-04 Clock positioning method, circuit and device Pending CN116860068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310815100.9A CN116860068A (en) 2023-07-04 2023-07-04 Clock positioning method, circuit and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310815100.9A CN116860068A (en) 2023-07-04 2023-07-04 Clock positioning method, circuit and device

Publications (1)

Publication Number Publication Date
CN116860068A true CN116860068A (en) 2023-10-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310815100.9A Pending CN116860068A (en) 2023-07-04 2023-07-04 Clock positioning method, circuit and device

Country Status (1)

Country Link
CN (1) CN116860068A (en)

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