CN116847651A - Stacked gate flash memory array structure sharing word line and layout thereof - Google Patents

Stacked gate flash memory array structure sharing word line and layout thereof Download PDF

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Publication number
CN116847651A
CN116847651A CN202310944136.7A CN202310944136A CN116847651A CN 116847651 A CN116847651 A CN 116847651A CN 202310944136 A CN202310944136 A CN 202310944136A CN 116847651 A CN116847651 A CN 116847651A
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metal
row
metal layer
shared
layer
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王卉
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a stacked gate flash memory array structure sharing word lines and a layout thereof. Specifically, terminals for connecting the back-end metal routing of the word line layer and the control gate layer are all arranged in the edge area of the array area of the layout, then, the connection between the metal layers is achieved by using the irregular routing on the metal layers in the edge area in a mode that the fourth metal layer, the fifth metal layer and the sixth metal layer in the edge area are connected with the first metal layer, the second metal layer and the third metal layer in the array area, and then, half of the row control gate lines and the row word lines are arranged on the metal layers which are fixed at one interval and regularly distributed, and the other half of the row control gate lines are arranged on the metal layers which are fixed at the other interval and regularly distributed, so that the wiring of the metal layers is optimized, the area of each double-storage-bit memory cell is reduced while the wiring of the metal layers is more uniform and reasonable.

Description

Stacked gate flash memory array structure sharing word line and layout thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a stacked gate flash memory array structure sharing word lines and a layout thereof.
Background
Currently, in stacked gate flash memory cells sharing word lines, each of the stacked gate flash memory cells is composed of floating gates and control gates of two stacked gate structures sharing word lines, wherein the floating gates and the control gates are two bit lines which are source and drain and are used for selecting flash memory cells and reading cell currents.
Obviously, in each memory cell in the existing stacked gate flash memory array sharing a word line, the number of metal strips connected with the control gate is twice that of the metal strips connected with the shared word line. Based on this, in the prior art, layout wiring of the control gate line and the shared word line is generally formed by using two different metal layers, so in the existing stacked gate flash memory array of the shared word line, the density of the metal lines in the metal layer where the control gate line is located is twice that of the metal lines in the metal layer where the shared word line is located, which will cause that the minimum pitch between the two metal lines belonging to the two control gate lines in the same metal layer for connecting each memory cell determines the area of each memory cell in the stacked gate flash memory array structure of the shared word line.
Disclosure of Invention
The invention aims to provide a stacked gate flash memory array structure of shared word lines and a layout thereof, wherein rear-section metal wires for connecting word line layers and control gate layers in the layout of the stacked gate flash memory array structure of the shared word lines are arranged in an edge area of an array area of the layout so as to optimize wiring of metal layers to be more uniform and reasonable, half of row control gate lines and row word lines are arranged on metal layers with fixed intervals and regular distribution, and the other half of row control gate lines and row word lines are arranged on metal layers with fixed intervals and regular distribution, so that the area of each double-storage-bit storage unit is further reduced in a mode of halving the metal wires on each metal layer provided with the row control gate lines.
In order to solve the above technical problems, the present invention provides a stacked gate flash memory array structure layout sharing word lines, including an array region and an edge region located at an outer edge of the array region, where the edge region at least includes:
a word line layer including a plurality of row word line patterns arranged at intervals in a column direction;
the control grid layer comprises a plurality of row control grid line patterns which are arranged at intervals along the column direction, wherein two sides of one row word line pattern are respectively provided with one row control grid line pattern, and the row control grid line patterns are used for forming word lines and control grids of a plurality of double-storage-bit storage units which are positioned in the same row and share the stacked grid flash memory array structure of the word line;
a via layer on the word line layer and the control gate layer and including a plurality of via patterns;
the three metal layers are positioned on the through hole layer, and each metal layer comprises a plurality of metal wire patterns which are distributed at irregular intervals;
two metal plug layers are respectively positioned between two adjacent metal layers, and each metal plug layer comprises a plurality of metal plug patterns;
and the other half of the row control grid line patterns and the other half of the row word line patterns are respectively provided with a third metal line pattern contained on a third metal layer.
Further, the via layer, the first metal layer and the first metal plug layer may be sequentially disposed between half of the row control gate line patterns and the row word line patterns and the second metal layer, and the via layer, the first metal plug layer, the second metal layer and the second metal plug layer may be sequentially disposed between the other half of the row control gate line patterns and the row word line patterns and the third metal layer.
Further, the pattern shape of the metal line pattern provided on the row control gate line pattern and the row word line pattern is different for each of the metal layers.
Further, the shapes of the plurality of metal line patterns included in each metal layer may be different, and the metal line patterns may include at least a first line pattern and a second polygonal island pattern.
Further, the array area may specifically include:
the active layer comprises a plurality of active area patterns which are arranged in parallel at intervals along the row direction, wherein the active area patterns are separated from each other in two columns and are grouped to form a plurality of active area pattern groups, and the row direction and the column direction are mutually perpendicular;
The floating gate layer comprises a plurality of floating gate patterns which are arranged at intervals along the column direction;
three metal layers, wherein each metal layer comprises a plurality of metal line patterns which are fixed at intervals and regularly arranged;
and the bit line layer comprises a plurality of non-sharing bit line patterns and a plurality of sharing bit line patterns which are arranged at intervals along the row direction, two non-sharing bit line patterns and one sharing bit line pattern arranged between the two non-sharing bit line patterns are arranged in each active area pattern group, and the sharing bit line patterns are aligned to the interval area between the two active area patterns in each active area pattern group.
Further, the three metal layers included in the array region may be a fourth metal layer, a fifth metal layer, and a sixth metal layer, respectively; and the second metal plug patterns covered on the half number of row word line patterns are partially overlapped with the metal line patterns in the fifth metal layer in the array region, so that the row word line patterns are connected with the fifth metal layer in the array region through the second metal plug patterns.
Further, the second metal line pattern covered on the half number of the row control gate line patterns partially coincides with the metal line pattern in the fifth metal layer in the array region, and the remaining half number of each row control gate line pattern and the third metal line pattern covered on each row word line pattern partially coincides with one metal line pattern in the sixth metal layer in the array region, respectively, so that the other half number of the row control gate line patterns and the row word line patterns are connected to the sixth metal layer in the array region through the third metal plug pattern.
Further, each metal layer corresponds to a distance parameter Pmn, where Pmn is a line width of a metal line pattern included in one metal layer and a distance between two adjacent metal line patterns on the metal layer; the second distance parameter Pm2 corresponding to the second metal layer and the third distance parameter Pm3 corresponding to the third metal layer have the same value, and three times of the distance parameter Pm2 or Pm3 is equal to two times of the distance parameter between the two adjacent floating gate patterns.
In a second aspect, based on the layout of the stacked gate flash memory array structure of the shared word line, the present invention further provides a stacked gate flash memory array structure of the shared word line, which specifically may include:
the semiconductor device comprises a semiconductor substrate, a plurality of memory cells, a plurality of storage units and a plurality of storage units, wherein the memory cells are arranged on the semiconductor substrate in an array manner along a row direction and a column direction, the memory cells are separated and grouped in two columns, each memory cell comprises two memory bits and source drain regions positioned at two sides of each memory bit, and the row direction and the column direction are mutually perpendicular;
a word line group including a plurality of word lines, two memory bits in each of the memory cells sharing one word line, and word lines of a plurality of memory cells in the same row being connected together to form a plurality of row word lines WLn arranged in the column direction;
The bit line group comprises a plurality of non-shared bit lines and a plurality of shared bit lines, non-adjacent source-drain regions of non-adjacent memory bits of two memory cells positioned in the same row in each memory cell group are respectively connected with one non-shared bit line, all non-shared bit lines positioned in the same column in the same memory cell group are connected together along the column direction to form a plurality of column non-shared bit lines BLan arranged along the row direction, adjacent source-drain regions of adjacent memory bits of two memory cells positioned in the same row in each memory cell group share one shared bit line, and all shared bit lines in the same memory cell group are connected together along the column direction to form a plurality of column shared bit lines BLbn arranged along the row direction.
Further, each memory bit includes a control gate, and the control gates corresponding to the memory bits located in the odd rows in the memory cells located in the same row are connected together, and the control gates corresponding to the memory bits located in the even rows in the memory cells located in the same row are connected together, so as to form a plurality of row control gate lines arranged along the column direction, and the total number of the row control gate lines in the stacked flash memory array structure of the shared word line is twice the total number of the row word lines WLn along the row direction.
Further, the stacked gate flash memory array structure of the shared word line may further include a plurality of metal layers, where the plurality of metal layers at least includes a first metal layer, a second metal layer, and a third metal layer sequentially disposed from bottom to top along a direction parallel to the semiconductor substrate;
the memory cell array structure comprises a first metal layer, a second metal layer, a plurality of columns of non-shared bit lines, a plurality of rows of stacked gate flash memory array structures of shared word lines, a plurality of rows of memory cells, a plurality of storage units and a plurality of rows of word lines, wherein the non-shared bit lines and the shared bit lines of the plurality of columns are all arranged on the first metal layer, one half of the total number of row control gate lines and row word lines WLn corresponding to two adjacent rows of the stacked gate flash memory array structures of the shared word lines is arranged on the second metal layer, and the other half of the row control gate lines and row word lines WLn are all arranged on the third metal layer.
Further, each metal layer may include a plurality of metal lines, and each metal layer corresponds to a distance parameter Pmn, where the distance parameter is a line width of a metal line included in one metal layer and a distance between two adjacent metal lines on the metal layer; wherein, the second distance parameter Pm2 corresponding to the second metal layer is the same as the third distance parameter Pm3 corresponding to the third metal layer.
Further, the range of the distance parameter may specifically be: 0.08 μm to 0.4 μm.
Further, the area of one storage bit in each storage unit may specifically be:
S 1bit ＝1.15×Pm1×Pm2
wherein, the liquid crystal display device comprises a liquid crystal display device,S 1bit for the area of a memory bit in each memory cell, pm1 is a distance parameter corresponding to the first metal layer, and Pm2 is a distance parameter corresponding to the second metal layer.
Further, each memory cell is formed on an active region corresponding to the semiconductor substrate, and adjacent active regions are divided by a device isolation structure formed in a space region therebetween; the stacked gate flash memory array structure of the shared word line further comprises a plurality of shared metal plugs, wherein the shared metal plugs are positioned on the device isolation structure between two adjacent active regions and are used for electrically connecting the adjacent source drain regions of two adjacent memory cells belonging to the same row with the corresponding shared bit lines;
the width of each shared metal plug is larger than the width of the device isolation structure in the row direction, and projections of the shared metal plugs and the corresponding active areas of the two adjacent memory cells connected with the shared metal plugs in the direction perpendicular to the semiconductor substrate are overlapped partially.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
in the layout of the stacked gate flash memory array structure of the shared word line, the rear section metal routing (the wiring terminal between the second metal layer and the third metal layer) for connecting the word line layer and the control gate layer is arranged in the edge area of the array area of the layout (the wiring terminal between the second metal layer and the third metal layer is not arranged in the array area), then the connection between the metal layers is realized by using the irregular routing on the metal layers in the edge area in a mode of correspondingly connecting the fourth metal layer, the fifth metal layer and the sixth metal layer in the edge area with the first metal layer, the second metal layer and the third metal layer in the array area, and further, the other half of the row control gate lines and the row word lines are arranged on the metal layers which are fixed at one interval and are regularly distributed, and the other half of the row control gate lines are arranged on the metal layers which are fixed at the other interval and are regularly distributed, so that the layout of the metal layers is optimized, and the area of each double memory cell is more uniform and reasonable is reduced.
In addition, in the stacked gate flash memory array structure of the shared word line formed by the stacked gate flash memory array structure layout of the shared word line, firstly, through separating and grouping a plurality of memory cells in two columns and two columns, in order to realize that the area of each double-memory-bit memory cell in the flash memory array is only determined by the minimum spacing of metal lines on a first metal layer where 1.5 column sharing bit lines are positioned in the row direction by adopting a mode that the two columns of memory cells share one column sharing bit line, and further realize that the width of the area corresponding to the memory cells is reduced in the row direction. Then, by separating and grouping two rows and two rows of multiple double-memory-bit memory cells, in a manner that half of 4 row control grid lines and 2 row word lines corresponding to the two rows are arranged on the second metal layer, and the other half of the control grid lines and the 2 row word lines are arranged on the third metal layer, the area of each memory cell in the flash memory array is determined only by the minimum spacing of the metal lines on the second metal layer or the third metal layer in the column direction, and the length of the area corresponding to the memory cell in the column direction is further reduced.
Drawings
Fig. 1 is a schematic layout diagram of a floating gate layer, a word line layer, a control gate layer, a via layer, a first metal layer, and a first metal plug layer included in an edge region in a stacked gate flash memory array structure layout of a shared word line according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a layout structure covering a second metal layer and a second metal plug layer on the basis of the layout structure corresponding to the row control gate line patterns located in even rows and the row word line patterns located in even rows in the schematic diagram of the layout structure shown in fig. 1 according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a layout for covering a third metal layer on the basis of the layout structure corresponding to the row control gate line patterns located in the odd rows and the row word line patterns located in the odd rows in the schematic diagram of the layout structure shown in fig. 1 according to an embodiment of the present invention.
Fig. 4 is a schematic layout diagram of a part of the structure layout included in the array area corresponding to the stacked gate flash memory array structure layout of the shared word line corresponding to fig. 1 according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a stacked gate flash memory array structure sharing word lines according to an embodiment of the present invention.
Detailed Description
In order to make the technical scheme and advantages of the embodiments of the present invention more clear, the technical scheme of the present invention will be further described in detail below with reference to the accompanying drawings and the embodiments. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. It is to be understood that the meanings of "on … …", "over … …" and "over … …" in the present invention are to be interpreted in the broadest sense so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.
Further, spatially relative terms such as "on … …," "above … …," "above … …," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In embodiments of the present invention, the term "substrate" or "semiconductor substrate" refers to a material to which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate or on top of the semiconductor substrate may be patterned or may remain unpatterned.
In embodiments of the present invention, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
In embodiments of the present invention, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. The technical schemes described in the embodiments of the present invention may be arbitrarily combined without any collision.
In the embodiment of the present invention, the inventive concept of the researchers of the present invention is as follows: the back-end metal wires (terminals between the second metal layer and the third metal layer) for connecting the word line layers and the control gate layer are arranged in the edge area of the array area (terminals between the second metal layer and the third metal layer are not arranged in the array area) of the layout, then, by correspondingly connecting the fourth metal layer, the fifth metal layer and the sixth metal layer in the edge area with the first metal layer, the second metal layer and the third metal layer in the array area, the connection between the metal layers is realized by using irregular wires on the metal layers in the edge area, and then, by using a mode that half of the row control gate lines and the row word lines are arranged on the metal layers which are fixed at a certain interval and are regularly distributed, and the other half of the row control gate lines and the row word lines are arranged on the metal layers which are fixed at a certain interval and are regularly distributed, for example, the wiring of the metal layers is optimized, namely, half (3) of the 6 row control gate lines and 2 row word lines corresponding to the adjacent two rows of storage units are arranged on one metal line layer, and the other 3 row control gate lines are arranged on the other metal line layer, so that the 6 row control gate lines are not arranged on the metal layers, and the metal layers are not arranged on the first metal layer and the second metal layer is the first metal layer, and the second metal layer is the embodiment of the metal layer, and the metal layer is the half of the metal layer, and the metal layer is the metal layer, and the layer is the metal layer.
The following first describes a layout of a stacked gate flash memory array structure sharing word lines in detail. Referring to fig. 1 to 3, fig. 1 is a schematic diagram of a layout including a floating gate layer, a word line layer, a control gate layer, a via layer, a first metal layer, and a first metal plug layer in an edge region in a stacked gate flash memory array structure layout of a shared word line according to an embodiment of the present invention, fig. 2 is a schematic diagram of a layout including a second metal layer and a fifth metal plug layer on the basis of the layout corresponding to a row control gate pattern and a row word line pattern in an odd row in the layout structure schematic diagram shown in fig. 1 according to an embodiment of the present invention, and fig. 3 is a schematic diagram of a layout including a third metal layer on the basis of the layout corresponding to a row control gate pattern and a row word line pattern in an odd row in the layout structure schematic diagram shown in an embodiment of the present invention.
It will be understood that, in the stacked gate flash memory array structure and the layout thereof for sharing word lines provided in the embodiments of the present invention, in order to highlight the innovation points of the embodiments of the present invention, in fig. 1 to fig. 3, the edge regions 22 are placed in the middle position region of the drawing, and only the layout of part of the array regions is represented in the edge regions on both sides thereof, and the active layer, the floating gate layer, the control gate layer, and the word line layer are substantially distributed in the array regions and the edge regions at the same time, whereas in order to highlight the innovation points of the layout of the embodiments of the present invention in the layout, in the edge regions in fig. 1 to fig. 3 provided in the embodiments of the present invention, only characters wl1 to wln are used to correspond to a plurality of row word line patterns respectively representing the row word line patterns arranged at intervals along the column direction, without drawing the bar patterns specifically.
Therefore, in order to specifically show the difference between the provided layout and the existing layout, fig. 1 to fig. 3 only show part of the layout structure, but not all the layout structures in each figure, and the two sides of the edge area shown in fig. 1 to fig. 3 correspond to the partial schematic diagrams of the layout structures contained in the array area of the stacked gate flash memory array structure layout of the shared word line, which are only used for showing the correspondence between the three metal layers in the edge area and the three metal layers in the array area.
Referring to fig. 1 in combination with fig. 2 and 3, the layout of the stacked gate flash memory array structure for sharing word lines provided in the embodiment of the present invention includes an array region 11 and an edge region 22 located at an outer edge of the array region 11; wherein at least the edge region 22 comprises:
the floating gate layer comprises a plurality of floating gate patterns FG which are arranged at intervals along the column direction;
a word line layer including a plurality of row word line patterns wl1 to wln arranged at intervals in the column direction;
the control grid layer comprises a plurality of row control grid line patterns cg 1-cg 2n which are arranged at intervals along the direction of the columns, wherein two sides of one row word line pattern wl 1-wln are respectively provided with one row control grid line pattern for forming word lines and control grids of a plurality of double-storage-bit storage units positioned in the same row of the stacked grid flash memory array structure of the shared word line;
A via layer located on the word line layers wl1 to wln and the control gate layers cg1 to cg2n and including a plurality of via patterns ct;
three metal layers (a first metal layer, a second metal layer and a third metal layer) which are positioned on the through hole layer, wherein each metal layer comprises a plurality of metal line patterns Mn which are distributed at irregular intervals;
two metal plug layers (a first metal plug layer and a second metal plug layer) are respectively positioned between two adjacent metal layers, and each metal plug layer comprises a plurality of metal plug patterns MVn;
wherein the row control gate line patterns cg2, cg4, cg2n and/or the row word line patterns wl2, wl4, wln/2 in even rows are provided with a second metal line pattern M2 included on the second metal layer, respectively, and the remaining row control gate line patterns cg1, cg3, wl3, cgn and/or the row word line patterns wl1, wl3, wl nn in odd rows are provided with a third metal line pattern M3 included on the third metal layer.
In this embodiment, in order to accommodate the wiring of the patterns with different shapes in the edge region 22, the shapes of all the patterns in the corresponding first to third metal layers and the floating gate layer may be different and arranged at irregular intervals, and the fourth to sixth metal layers respectively corresponding to the first to third metal layers in the array region 11 are all running lines with fixed intervals and regularly arranged metal line patterns.
As an example, in the edge region 22, the shapes of the plurality of metal line patterns included in each metal layer are different, and the metal line patterns may include at least a first line pattern and a second polygonal island pattern, and the pattern shapes of the metal line patterns disposed on the row control gate line pattern and the row word line pattern may also be different for each metal layer.
Specifically, in the edge region 22, the word line layer and the control gate layer are covered with the via layer, and the via layer is covered with the first metal layer, so that word lines (or shared word lines) of a plurality of dual memory bit memory cells located in the same row and formed by the row word line pattern are connected with a first metal line in the first metal layer having a first shape (e.g., a twisted polygonal shape) through a via hole of the via layer, and row control gate lines formed by using the row control gate line pattern are connected with a first metal line in the first metal layer having a second polygonal island shape through the via hole. Then, a first metal plug pattern MV1 is respectively covered on each of the first metal line patterns M1.
Then, referring to fig. 2, the first metal line pattern M1 and the second metal plug pattern MV1 in the second polygonal island shape overlaid on the control gate line patterns cg2, cg4, and cg2n in fig. 1 are overlaid with a second metal line pattern M2 in the first line shape (e.g., a twisted polygonal line shape), and the first metal plug pattern MV1 in the even line in fig. 1 is directly overlaid with the fifth metal line pattern M5 in the fifth metal layer as the second metal layer in the array region 11, i.e., the first metal plug pattern M1 overlaid on the even line and cg2n is partially overlapped with the fifth metal line pattern M5 in the fifth metal layer in the array region 11, so that the even line and cg2 are connected to each other by the fifth metal plug pattern cg2, cg2 n.
Next, referring to fig. 3, for the row control gate line patterns cg1, cg3, & gt, cgn and/or the row word line patterns wl1, wl3, wl2 in the odd rows shown in fig. 1, the surface of the row control gate line patterns is covered with a third metal line pattern M3 included in a third metal layer in addition to the second metal line pattern M2 and the second metal plug pattern MV2 in sequence, so as to achieve the purpose of reducing the area of each dual-memory-bit memory cell in the stacked gate flash memory array structure of the shared word line formed by using the layout diagrams shown in fig. 1 to 4.
Then, the row control gate line patterns cg1, cg3, and cgn of the odd-numbered rows and the row word line patterns wl1, wl3 of the odd-numbered rows are partially overlapped with a sixth metal line pattern M6 in the sixth metal layer of the array region 11, which is the third metal layout layer thereof, respectively, so that the row control gate line patterns of the odd-numbered rows and the row word line patterns of the odd-numbered rows are connected to the sixth metal layer in the array region through the second metal plug patterns MV 2.
Obviously, in the layout of the stacked gate flash memory array structure sharing the word lines, the rear-section metal wires (the terminals between the second metal layer and the third metal layer) for connecting the word line layers and the control gate layers are arranged in the edge area of the array area of the layout (the terminals between the second metal layer and the third metal layer are not arranged in the array area), and then the wiring of the metal layers is optimized in a way that the fourth metal layer, the fifth metal layer and the sixth metal layer in the edge area are correspondingly connected with the first metal layer, the second metal layer and the third metal layer in the array area, so that the layout is more uniform and reasonable.
Referring to fig. 4, in the array area 11, it may specifically include:
The active layer comprises a plurality of active region patterns Act 1-Actn which are arranged in parallel at intervals along the row direction, wherein the active region patterns Act 1-Actn are separated from each other in two rows and are grouped to form a plurality of active region pattern groups (1 st group-n group), and the row direction and the column direction are mutually perpendicular;
the floating gate layer comprises a plurality of floating gate patterns FG which are arranged at intervals along the column direction;
three metal layers (fourth to sixth metal layers), each of which includes a plurality of metal line patterns M4 to M6 arranged at regular intervals;
the bit line layer comprises a plurality of non-sharing bit line patterns bla 1-bla 2n and a plurality of sharing bit line patterns blb 1-blbn which are arranged at intervals along the row direction, two non-sharing bit line patterns and one sharing bit line pattern arranged between the two non-sharing bit line patterns are arranged in each active area pattern group, and the sharing bit line patterns are aligned to the interval area between the two active area patterns in each active area pattern group.
Each metal layer corresponds to a distance parameter Pmn, wherein the distance parameter is the line width of a metal line pattern contained in one metal layer and the distance between two adjacent metal line patterns on the metal layer; the second distance parameter Pm2 corresponding to the second metal layer and the third distance parameter Pm3 corresponding to the third metal layer have the same value, and three times of the distance parameter Pm2 or Pm3 is equal to two times of the distance parameter between the two adjacent floating gate patterns.
Further, based on the layout of the stacked gate flash memory array structure of the shared word line shown in fig. 1 to 4, the embodiment of the present invention further provides a stacked gate flash memory array structure of the shared word line prepared by using the layout of the stacked gate flash memory array structure of the shared word line, specifically referring to fig. 5, as shown in fig. 5, the stacked gate flash memory array structure of the shared word line provided in the embodiment of the present invention may include the following structures:
a plurality of memory cells a arranged on the semiconductor substrate in an array in a row direction (indicated by X in fig. 5) and a column direction (indicated by Y in fig. 5), the plurality of memory cells a being separated and grouped in two columns and two rows to form a plurality of memory cell groups (1 st to n-th groups); each storage unit A comprises two storage bits and source and drain regions positioned at two sides of each storage bit, wherein the source and drain regions are connected by bit lines, namely the source and drain regions are the bit lines.
The word line group comprises a plurality of word lines, wherein two storage bits in each storage unit A share one word line, and the word lines of the storage units A in the same row are connected together to form a plurality of row word lines WL 1-WLn which are arranged along the column direction;
A bit line group including a plurality of non-shared bit lines and a plurality of shared bit lines, non-adjacent source and drain regions of non-adjacent memory bits of two memory cells a located in the same row in each memory cell group (1 st to nth group) being connected to one of the non-shared bit lines, respectively, and all the non-shared bit lines located in the same column in the same memory cell group (1 st to nth group) being connected together in the column direction to form a plurality of columns of non-shared bit lines BLa1 to BLa2n arranged in the row direction, while adjacent source and drain regions of adjacent memory bits of two memory cells a located in the same row in each memory cell group share one of the shared bit lines, and all the shared bit lines in the same memory cell group (1 st to nth group) being connected together in the column direction to form a plurality of columns of shared bit lines BLb1 to bn arranged in the row direction;
and the multi-layer Metal at least comprises a first Metal layer Metal1, a second Metal layer Metal 2 and a third Metal layer Metal3 which are sequentially arranged from bottom to top along a direction parallel to the semiconductor substrate.
The memory cell array structure comprises a first metal layer, a second metal layer, a plurality of columns of non-shared bit lines, a plurality of rows of stacked gate flash memory array structures of shared word lines, a plurality of rows of memory cells, a plurality of storage units and a plurality of rows of word lines, wherein the non-shared bit lines and the shared bit lines of the plurality of columns are all arranged on the first metal layer, one half of the total number of row control gate lines and row word lines WLn corresponding to two adjacent rows of the stacked gate flash memory array structures of the shared word lines is arranged on the second metal layer, and the other half of the row control gate lines and row word lines WLn are all arranged on the third metal layer.
In the embodiment of the present invention, the shared word line for two memory bits in each memory cell a is referred to as a word line, and then, the word line after connection of all the memory cells a in the same row is referred to as a row word line; similarly, the non-shared bit lines, column non-shared bit lines, column shared bit lines, control gates, and row control gate lines are named using the same naming method.
Specifically, in the embodiment of the present invention, control gates corresponding to a plurality of storage bits located in an odd row in a plurality of storage units a in the same row are connected together, and control gates corresponding to a plurality of storage bits located in an even row in a plurality of storage units a in the same row are connected together, so as to form a plurality of row control gate lines CG1 to CG2n arranged along the column direction.
In this embodiment, first, a plurality of memory cells having dual memory bits with shared word lines are separated and grouped in two columns along a row direction to form a1 st to nth group (memory cell group) arranged along the row direction, then bit lines corresponding to adjacent two memory bits in 4 memory bits in two memory cells a in each of the 1 st to nth groups are shared, and then all the shared bit lines in the same memory cell group are connected together along the column direction, i.e., the plurality of column shared bit lines BLb1 to BLbn arranged along the row direction are formed, for example, BLb1 is a column shared bit line corresponding to the 1 st memory cell group. Similarly, the plurality of column unshared bit lines BLa1 to BLa2n arranged in the row direction are formed by the same method.
Further, each metal layer metal n comprises a plurality of metal lines, and each metal layer metal n corresponds to a distance parameter Pmn, wherein the distance parameter is the line width of the metal line contained in one metal layer metal n and the distance between two adjacent metal lines on the metal layer; the second distance parameter Pm2 corresponding to the second Metal layer Metal2 and the third distance parameter Pm3 corresponding to the third Metal layer Metal3 have the same value, and the first distance parameter Pm1 corresponding to the first Metal layer Metal1 is different from both. As an example, the range of values of the distance parameters Pm1 to Pm3 is: 0.08 μm to 0.4 μm, i.e., the distance parameters Pm1 to Pm3 correspond to the minimum dimensions Pitch of each metal layer, respectively.
It is obvious that, in the stacked gate flash memory array structure with shared word lines provided in the embodiment of the present invention, half of the row control gate lines and the row word lines WLn are disposed on one metal layer (the second metal layer) and the other half of the row control gate lines and the row word lines WLn are disposed on the other metal layer (the third metal layer), that is, in the embodiment of the present invention, the area of each memory cell is determined only by the minimum pitch of the metal lines on the first metal layer where 1.5 column sharing bit lines are located in the row direction, and the area of each memory cell is determined only by the minimum pitch of the metal lines on the second metal layer or the third metal layer in the column direction, so that the area of one memory bit1 or bit2 in each of the memory cells a in the embodiment of the present invention is specifically:
S 1bit ＝1.15×Pm1×Pm2
Wherein S is 1bit For the area of a memory bit1 or bit2 in each memory cell a, pm1 is a distance parameter corresponding to the first Metal layer Metal1, and Pm2 is a distance parameter corresponding to the second Metal layer Metal 2.
That is, compared with the prior art in which 1.5×pm1×pm2 is reduced to 1.15×pm1×pm2, the area of each memory cell in the stacked gate flash memory array structure of the shared word line provided in the embodiment of the present invention is reduced by 25% under the same process node, and the area of each memory cell in the stacked gate flash memory array structure of the shared word line is effectively reduced.
Further, each memory cell a is formed on an active region corresponding to the semiconductor substrate, and adjacent active regions are separated by a device isolation structure; the stacked gate flash memory array structure of the shared word line may further specifically include a plurality of shared metal plugs, where the shared metal plugs are located on the device isolation structure between two adjacent active regions, so as to electrically connect the adjacent source and drain regions of two adjacent memory cells belonging to the same row with the corresponding shared bit line;
The width of each shared metal plug is larger than the width of the device isolation structure in the row direction along the direction parallel to the row direction, and projections of active areas corresponding to the shared metal plug and the adjacent two storage units connected with the shared metal plug are partially overlapped along the direction perpendicular to the semiconductor substrate.
In the embodiment of the present invention, in order to correspond to and illustrate the memory cell a shown in fig. 5, the layout structure corresponding to the memory cell a in fig. 4 also identifies the layout position corresponding to the memory cell a.
In summary, in the layout of the stacked gate flash memory array structure with shared word lines according to the present invention, the back-end metal traces (terminals between the second metal layer and the third metal layer) for connecting the word line layers and the control gate layer are all disposed in the edge region of the array region of the layout (terminals between the second metal layer and the third metal layer are not disposed in the array region), and then, by correspondingly connecting the fourth metal layer, the fifth metal layer and the sixth metal layer in the edge region with the first metal layer, the second metal layer and the third metal layer in the array region, the connection between the metal layers is realized by using irregular traces on the metal layers in the edge region, and then, by using a manner that half of the row control gate lines and the row word lines are disposed on the metal layers with a fixed and regular distribution at a fixed pitch and the other half of the row control gate lines are disposed on the metal layers with a fixed and regular distribution at another pitch, the layout of the array region is not disposed.
In addition, in the stacked gate flash memory array structure of the shared word line formed by the stacked gate flash memory array structure layout of the shared word line, firstly, through separating and grouping a plurality of memory cells in two columns and two columns, in order to realize that the area of each double-memory-bit memory cell in the flash memory array is only determined by the minimum spacing of metal lines on a first metal layer where 1.5 column sharing bit lines are positioned in the row direction by adopting a mode that the two columns of memory cells share one column sharing bit line, and further realize that the width of the area corresponding to the memory cells is reduced in the row direction. Then, by separating and grouping two rows and two rows of multiple double-memory-bit memory cells, in a manner that half of 4 row control grid lines and 2 row word lines corresponding to the two rows are arranged on the second metal layer, and the other half of the control grid lines and the 2 row word lines are arranged on the third metal layer, the area of each memory cell in the flash memory array is determined only by the minimum spacing of the metal lines on the second metal layer or the third metal layer in the column direction, and the length of the area corresponding to the memory cell in the column direction is further reduced.
Therefore, the foregoing is only a preferred embodiment of the present invention and is not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
It should be noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.
It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims (15)

1. The stacked gate flash memory array structure layout sharing the word lines is characterized by comprising an array area and an edge area positioned at the outer side edge of the array area, wherein the edge area at least comprises:
a word line layer including a plurality of row word line patterns arranged at intervals in a column direction;
The control grid layer comprises a plurality of row control grid line patterns which are arranged at intervals along the column direction, wherein two sides of one row word line pattern are respectively provided with one row control grid line pattern, and the row control grid line patterns are used for forming word lines and control grids of a plurality of double-storage-bit storage units which are positioned in the same row and share the stacked grid flash memory array structure of the word line;
a via layer on the word line layer and the control gate layer and including a plurality of via patterns;
the three metal layers are positioned on the through hole layer, and each metal layer comprises a plurality of metal wire patterns which are distributed at irregular intervals;
two metal plug layers are respectively positioned between two adjacent metal layers, and each metal plug layer comprises a plurality of metal plug patterns;
and the other half of the row control grid line patterns and the other half of the row word line patterns are respectively provided with a third metal line pattern contained on a third metal layer.
2. The shared word line stacked flash memory array structure layout of claim 1, wherein said via layer, first metal layer and first metal plug layer are further disposed in sequence between half of said row control gate line patterns and row word line patterns and said second metal layer, and said via layer, first metal plug layer, second metal layer and second metal plug layer are further disposed in sequence between the other half of said row control gate line patterns and said row word line patterns and said third metal layer.
3. The word line shared stacked flash memory array structure layout of claim 2, wherein a pattern shape of a metal line pattern disposed on the row control gate line pattern and the row word line pattern may be different for each of the metal layers.
4. A word line sharing stacked gate flash memory array structure layout as claimed in claim 3, wherein the shape of a plurality of said metal line patterns contained in each of said metal layers may be different, and said metal line patterns comprise at least a first line pattern and a second polygonal island pattern.
5. The word line shared stacked flash memory array structure layout of claim 4, wherein said array region comprises:
the active layer comprises a plurality of active area patterns which are arranged in parallel at intervals along the row direction, wherein the active area patterns are separated from each other in two columns and are grouped to form a plurality of active area pattern groups, and the row direction and the column direction are mutually perpendicular;
the floating gate layer comprises a plurality of floating gate patterns which are arranged at intervals along the column direction;
three metal layers, wherein each metal layer comprises a plurality of metal line patterns which are fixed at intervals and regularly arranged;
and the bit line layer comprises a plurality of non-sharing bit line patterns and a plurality of sharing bit line patterns which are arranged at intervals along the row direction, two non-sharing bit line patterns and one sharing bit line pattern arranged between the two non-sharing bit line patterns are arranged in each active area pattern group, and the sharing bit line patterns are aligned to the interval area between the two active area patterns in each active area pattern group.
6. The layout of a shared word line stacked flash memory array structure of claim 5, wherein the three metal layers included in the array region are a fourth metal layer, a fifth metal layer, and a sixth metal layer, respectively; and the second metal plug patterns covered on the half number of row word line patterns are partially overlapped with the metal line patterns in the fifth metal layer in the array region, so that the row word line patterns are connected with the fifth metal layer in the array region through the second metal plug patterns.
7. The shared word line stacked flash memory array structure layout of claim 6, wherein the second metal line pattern covered on the half of the row control gate line patterns partially coincides with the metal line pattern in the fifth metal layer in the array region, and the remaining half of each row control gate line pattern and the third metal line pattern covered on each row word line pattern partially coincides with one metal line pattern in the sixth metal layer in the array region, respectively, such that the half of the row control gate line patterns and row word line patterns are connected to the sixth metal layer in the array region through the third metal plug patterns.
8. The layout of a shared word line stacked flash memory array as recited in claim 7, wherein each of said metal layers corresponds to a distance parameter Pmn, said distance parameter Pmn being a line width of a metal line pattern included in one of said metal layers and a distance between two adjacent metal line patterns on said metal layer; the second distance parameter Pm2 corresponding to the second metal layer and the third distance parameter Pm3 corresponding to the third metal layer have the same value, and three times of the distance parameter Pm2 or Pm3 is equal to two times of the distance parameter between the two adjacent floating gate patterns.
9. A stacked gate flash memory array structure sharing word lines, comprising:
the semiconductor device comprises a semiconductor substrate, a plurality of memory cells, a plurality of storage units and a plurality of storage units, wherein the memory cells are arranged on the semiconductor substrate in an array manner along a row direction and a column direction, the memory cells are separated and grouped in two columns, each memory cell comprises two memory bits and source drain regions positioned at two sides of each memory bit, and the row direction and the column direction are mutually perpendicular;
a word line group including a plurality of word lines, two memory bits in each of the memory cells sharing one word line, and word lines of a plurality of memory cells in the same row being connected together to form a plurality of row word lines WLn arranged in the column direction;
The bit line group comprises a plurality of non-shared bit lines and a plurality of shared bit lines, non-adjacent source-drain regions of non-adjacent memory bits of two memory cells positioned in the same row in each memory cell group are respectively connected with one non-shared bit line, all non-shared bit lines positioned in the same column in the same memory cell group are connected together along the column direction to form a plurality of column non-shared bit lines BLan arranged along the row direction, adjacent source-drain regions of adjacent memory bits of two memory cells positioned in the same row in each memory cell group share one shared bit line, and all shared bit lines in the same memory cell group are connected together along the column direction to form a plurality of column shared bit lines BLbn arranged along the row direction.
10. The stacked-gate flash memory array structure of claim 9, wherein each of the memory bits includes a control gate, and control gates corresponding to a plurality of memory bits located in odd rows among a plurality of memory cells in a same row are connected together, and control gates corresponding to a plurality of memory bits located in even rows among a plurality of memory cells in the same row are connected together, so as to form a plurality of row control gate lines arranged along the column direction, and so that a total number of the row control gate lines in the stacked-gate flash memory array structure of the shared word line is twice a total number of the row word lines WLn along the row direction.
11. The shared word line stacked gate flash memory array structure of claim 10, further comprising a plurality of metal layers including at least a first metal layer, a second metal layer, and a third metal layer disposed in sequence from bottom to top in a direction parallel to the semiconductor substrate;
the memory cell array structure comprises a first metal layer, a second metal layer, a plurality of columns of non-shared bit lines, a plurality of rows of stacked gate flash memory array structures of shared word lines, a plurality of rows of memory cells, a plurality of storage units and a plurality of rows of word lines, wherein the non-shared bit lines and the shared bit lines of the plurality of columns are all arranged on the first metal layer, one half of the total number of row control gate lines and row word lines WLn corresponding to two adjacent rows of the stacked gate flash memory array structures of the shared word lines is arranged on the second metal layer, and the other half of the row control gate lines and row word lines WLn are all arranged on the third metal layer.
12. The stacked-gate flash memory array structure of claim 11, wherein each of said metal layers comprises a plurality of metal lines, and each of said metal layers corresponds to a distance parameter Pmn, said distance parameter being a line width of a metal line comprised by one of said metal layers and a distance between two adjacent metal lines on said metal layer; wherein, the second distance parameter Pm2 corresponding to the second metal layer is the same as the third distance parameter Pm3 corresponding to the third metal layer.
13. The stacked gate flash memory array structure of claim 12, wherein the range of values of the distance parameter is: 0.08 μm to 0.4 μm.
14. The shared word line stacked flash memory array structure of claim 13, wherein an area of one memory bit in each of said memory cells is:
S 1bit ＝1.15×Pm1×Pm2
wherein S is 1bit For the area of a memory bit in each memory cell, pm1 is the distance parameter corresponding to the first metal layer, and Pm2 is the second metal layerDistance parameters corresponding to the metal layer.
15. The stacked-gate flash memory array structure of claim 9, wherein each of said memory cells is formed on a corresponding one of said semiconductor substrates, adjacent ones of said active regions being separated by a device isolation structure formed in a spaced-apart region therebetween; the stacked gate flash memory array structure of the shared word line further comprises a plurality of shared metal plugs, wherein the shared metal plugs are positioned on the device isolation structure between two adjacent active regions and are used for electrically connecting the adjacent source drain regions of two adjacent memory cells belonging to the same row with the corresponding shared bit lines;
The width of each shared metal plug is larger than the width of the device isolation structure in the row direction, and projections of the shared metal plugs and the corresponding active areas of the two adjacent memory cells connected with the shared metal plugs in the direction perpendicular to the semiconductor substrate are overlapped partially.
CN202310944136.7A 2023-07-28 2023-07-28 Stacked gate flash memory array structure sharing word line and layout thereof Pending CN116847651A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117556778A (en) * 2024-01-11 2024-02-13 杭州广立微电子股份有限公司 E-fuse unit and winding method of E-fuse test array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117556778A (en) * 2024-01-11 2024-02-13 杭州广立微电子股份有限公司 E-fuse unit and winding method of E-fuse test array
CN117556778B (en) * 2024-01-11 2024-05-14 杭州广立微电子股份有限公司 E-fuse unit and winding method of E-fuse test array

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