CN118119188A - Semiconductor structure and memory - Google Patents

Abstract

The embodiment of the disclosure discloses a semiconductor structure and a memory, wherein the semiconductor structure comprises: a plurality of memory structures, a plurality of word lines, and a plurality of bit lines; each storage structure comprises a plurality of grid structures, a plurality of storage elements and a plurality of semiconductor channels; each gate structure at least partially surrounds a side of a corresponding semiconductor channel; each word line is correspondingly connected with each grid structure; the first end of each storage element is correspondingly connected with a bit line; the second end of each storage element is correspondingly connected with the end part of the semiconductor channel; each word line and each bit line extend along different directions respectively, and the number of the bit lines is greater than or equal to that of the word lines; the memory structure is connected with a plurality of bit lines. The embodiment of the disclosure can realize the operation mode of the 1T1MTJ, and simultaneously can reduce the chip area and improve the integration level.

Description

Semiconductor structure and memory

Technical Field

The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor structure and a memory.

Background

Most Magnetic Random Access Memories (MRAM) employ drive transistors that are planar transistors. The size of the planar transistor is large, limiting the increase in magnetic random access memory density. Therefore, further optimization of the structure of the magnetic random access memory is required to improve the integration level.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a semiconductor structure and a memory, which can reduce the area of a chip and improve the integration level; meanwhile, the operation mode of the 1T1MTJ can be realized.

The technical scheme of the embodiment of the disclosure is realized as follows:

Embodiments of the present disclosure provide a semiconductor structure, the semiconductor structure comprising: a plurality of memory structures, a plurality of word lines, and a plurality of bit lines; each storage structure comprises a plurality of grid structures, a plurality of storage elements and a plurality of semiconductor channels; each gate structure at least partially surrounds a side of a corresponding semiconductor channel; each word line is correspondingly connected with each grid structure; the first end of each storage element is correspondingly connected with a bit line; the second end of each storage element is correspondingly connected with the end part of the semiconductor channel; each word line and each bit line extend along different directions respectively, and the number of the bit lines is greater than or equal to that of the word lines; wherein each memory structure is connected to a plurality of bit lines.

In the above scheme, in each storage structure, each gate structure extends along a vertical direction, and a plurality of semiconductor channels are stacked at intervals along the vertical direction to form a step shape, wherein the number of bit lines is the same as the number of semiconductor channels.

In the above solution, each storage structure further includes: a source structure; each memory structure comprises two gate structures; the source electrode structure extends along the vertical direction; the source structure is located between the two gate structures.

In the above aspect, each semiconductor channel extends in the first direction; the bit lines extend along a first direction, and the word lines extend along a second direction; the second direction intersects the first direction.

In the scheme, the plurality of storage structures form an array of P rows and Q columns, and P and Q are both more than or equal to 2; wherein each row of storage structures is arranged along the second direction, and each column of storage structures is arranged along the first direction; for each row of memory structures, memory elements corresponding to semiconductor channels located at the same layer are connected to the same bit line.

In the above scheme, along the second direction, the bit lines are alternately arranged at the first height or the second height; the bit lines at the first height are linear, and the bit lines at the second height are zigzag.

In the scheme, a plurality of bit lines are all arranged at the same height and are all zigzag.

In the above scheme, the number of bit lines is the same as the number of semiconductor channel layers for each row of memory structures.

In the above aspect, each semiconductor channel extends in the first direction; the bit lines extend along the third direction, and the word lines extend along the fourth direction; the third direction and the fourth direction both intersect in the first direction.

In the scheme, a plurality of storage structures are arranged in a staggered manner to form an array of N rows and M columns, wherein N and M are both greater than or equal to 2; wherein each column of storage structures is arranged along a first direction, and each row of storage structures is arranged along a third direction; for each column of memory structures, memory elements located on the same side of the source structure and connected to the same layer of semiconductor channels are connected to the same bit line.

In the above scheme, every two bit lines are alternately arranged at the first height or the second height along the first direction; wherein the bit line at the first level is disposed directly above the bit line at the second level.

In the above scheme, the number of bit lines is twice the number of semiconductor channel layers for each column of memory structure.

In the above scheme, two gate structures included in each memory structure are correspondingly connected to two adjacent word lines; each word line is connected to one gate structure on the memory structure that intersects it.

In the above scheme, the two gate structures included in each storage structure are a first gate structure and a second gate structure respectively; for each column of storage structures, the first grid structure of the n-1 storage structure and the second grid structure of the n storage structure are connected to the same word line; the second grid structure of the n-1 storage structure and the first grid structure of the n-2 storage structure are connected to the same word line; n is 2 or more.

The embodiment of the disclosure also provides a memory, which comprises the semiconductor structure in the scheme.

In the above scheme, the memory is a magnetic random access memory MRAM.

It can be seen that the embodiments of the present disclosure provide a semiconductor structure and a memory, wherein the semiconductor structure includes: a plurality of memory structures, a plurality of word lines, and a plurality of bit lines; each storage structure comprises a plurality of grid structures, a plurality of storage elements and a plurality of semiconductor channels; each gate structure at least partially surrounds a side of a corresponding semiconductor channel; each word line is correspondingly connected with each grid structure; the first end of each storage element is correspondingly connected with a bit line; the second end of each storage element is correspondingly connected with the end part of the semiconductor channel; each word line and each bit line extend along different directions respectively, and the number of the bit lines is greater than or equal to that of the word lines; the memory structure is connected with a plurality of bit lines. Thus, when each gate structure is activated, only one bit line connected with the corresponding storage element is opened, so that only the data of one storage element is read or written, that is, the operation mode of the 1T1MTJ is realized. Thus, the read and write operations of the bit lines can be resolved, namely: only the data in one storage element may be operated on.

Drawings

Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;

Fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;

Fig. 3 is a schematic structural diagram III of a semiconductor structure according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;

fig. 5 is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure;

fig. 6 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;

fig. 7 is a schematic structural diagram seven of a semiconductor structure according to an embodiment of the disclosure;

Fig. 8 is a schematic structural diagram eight of a semiconductor structure according to an embodiment of the disclosure;

fig. 9 is a schematic structural diagram nine of a semiconductor structure provided in an embodiment of the disclosure;

fig. 10 is a schematic structural view of a semiconductor structure according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram eleven of a structure of a semiconductor structure according to an embodiment of the disclosure;

fig. 12 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;

Fig. 13 is a schematic structural view of a semiconductor structure according to an embodiment of the present disclosure;

Fig. 14 is a schematic structural view fourteen of a semiconductor structure according to an embodiment of the present disclosure;

fig. 15 is a schematic structural view fifteen of a semiconductor structure according to an embodiment of the present disclosure;

fig. 16 is a schematic structural diagram of a memory according to an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that "first/second/third" may, where allowed, interchange a specific order or precedence, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

Fig. 1 is an alternative schematic diagram of a semiconductor structure provided in an embodiment of the disclosure, and fig. 2 and fig. 3 are schematic perspective views of a semiconductor structure 100 in fig. 1, where fig. 2 illustrates a connection structure of a word line 20 and a memory structure 10, and fig. 3 illustrates a connection structure of a bit line 30 and the memory structure 10.

Referring to fig. 1,2 and 3, a semiconductor structure 100 includes: a number of memory structures 10, a number of word lines 20, and a number of bit lines 30. Each memory structure 10 includes a number of gate structures 110, a number of memory elements 140, and a number of semiconductor channels 120. Each gate structure 110 at least partially surrounds a side of a corresponding semiconductor channel 120, and each word line 20 is correspondingly connected to each gate structure 110. A first end of each memory element 140 is correspondingly connected to the bit line 30; the second end of each memory element 140 is correspondingly connected to an end of the semiconductor channel 120. Each word line 20 and each bit line 30 extend in different directions, respectively.

It should be noted that, the number of layers of the semiconductor channels 120 shown in fig. 1,2, and 3 may be 1 or more, and the number of gate structures 110 may be 1 or more; the number of gate structures 110 is exemplified by 2 for the number of layers of semiconductor channels 120.

It should be further noted that, the plurality of memory structures 10 form an array of P rows and Q columns, where P and Q are both greater than or equal to 2. Fig. 1,2 and 3 illustrate only row 1, row 2 and row P memory structures 10, and other portions of semiconductor structure 100 may be understood with reference to the illustrated portions. For example, the connection relationship between the memory elements 140 and the bit lines 30 included in the 3 rd to Q-1 st column memory structures 10 can be understood with reference to the 1 st to 2 nd column memory structures 10 in fig. 3; the connection relationship between the gate structures 110 and the word lines 20 included in the 3 rd to P-1 st row memory structures 10 can be understood with reference to the 1 st to 2 nd row memory structures 10 in fig. 2.

It should be further noted that the first direction X and the second direction Y shown in fig. 1, 2 and 3 are perpendicular to the vertical direction Z. The substrate is not shown in fig. 1, 2 and 3. The vertical direction Z may be perpendicular to the substrate. The first direction X and the second direction Y may be perpendicular to each other, or may be any included angle, and the second direction Y is perpendicular to the first direction X.

In embodiments of the present disclosure, the substrate may include at least one of semiconductor materials, for example, group IV elements such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or group III-V compounds such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), and the like.

In the embodiment of the present disclosure, the semiconductor channel 120 may have a doping element therein to improve the conductivity of the semiconductor channel 120. The doping element may be a P-type doping element or an N-type doping element, the N-type doping element may be at least one of arsenic (As) element, phosphorus (P) element or antimony (Sb) element, and the P-type doping element may be at least one of boron (B) element, indium (In) element or gallium (Ga) element.

In the disclosed embodiment, the gate structure 110 includes a dielectric layer surrounding the semiconductor channel 120 and a conductive layer surrounding the dielectric layer. The material of the conductive layer may be titanium nitride (TiN), or at least one of conductive materials such as tantalum nitride (TaN), copper (Cu), or tungsten (W), and the material of the dielectric layer may be silicon oxide (SiO).

In the disclosed embodiment, with reference to fig. 1 and 3, a number of memory structures 10 form an array of P rows and Q columns; each row of memory structures 10 is arranged along the second direction Y, and each column of memory structures 10 is arranged along the first direction X. Each memory structure 10 includes two semiconductor channels 120, a first semiconductor channel 121 and a second semiconductor channel 122, respectively. Each memory structure 10 includes 4 memory elements 140, and 4 memory elements 140 are connected to the ends of two semiconductor channels 120 in a one-to-one correspondence. Each row of memory structures 10 includes two bit lines 30, both bit lines 30 extending along a first direction X.

For row 1 memory structure 10, the first ends of memory elements 140 are each connected to bit line 30 by a contact structure, and the second ends of memory elements 140 are each connected to an end of semiconductor channel 120 by a contact structure. The memory element 140 to which each memory structure 10 is connected to two bit lines 30, wherein the memory element 140 to which the first semiconductor channel 121 is connected to one bit line 30 and the memory element 140 to which the second semiconductor channel 122 is connected to the other bit line 30. Accordingly, the memory elements 140 included in the 2 nd to P th row memory structures 10 are connected to the corresponding bit lines 30.

That is, the first end of each memory element 140 is correspondingly connected to the bit line 30; a second end of each memory element 140 is correspondingly connected to an end of the semiconductor channel 120; each memory structure 10 is connected to a plurality of bit lines 30; the bit lines 30 each extend along a first direction X.

In the disclosed embodiment, referring to fig. 1 and 2, each column of memory structures 10 includes two word lines 20, and each of the two word lines 20 extends along the second direction Y. For the 1 st column of memory structures 10, the gate structures 110 located on the same side of the source structures 130 are connected to the same word line 20, and thus, the gate structures 110 included in the 1 st column of memory structures 10 are correspondingly connected to two word lines 20. Accordingly, the gate structures 110 in the 2 nd to Q th column memory structures 10 are connected to the corresponding word lines 20. That is, each word line 20 is correspondingly connected to each gate structure 110; the word lines 20 each extend in the second direction Y.

In the disclosed embodiment, referring to fig. 1, 2 and 3, each gate structure 110 at least partially encloses at least one side of two semiconductor channels 120, and the two semiconductor channels 120 are correspondingly connected to 2 memory elements, so that each gate structure 110 corresponds to two memory elements 140. The two memory elements 140 are connected to the two bit lines 30 in a one-to-one correspondence. The number of word lines 20 and bit lines 30 to which each memory structure 10 is connected is equal. Further, when the number of rows and columns of the semiconductor structure 100 are equal, the number of bit lines 30 and the number of word lines 20 included in the semiconductor structure 100 are equal.

Accordingly, when the number of semiconductor channels 120 included in each memory structure 10 is greater than two, the gate structure 110 at least partially surrounds the plurality of semiconductor channels 120 and is correspondingly connected to one word line 20. The plurality of semiconductor channels 120 surrounded by each gate structure 110 are correspondingly connected to a plurality of memory elements 140, and the plurality of memory elements 140 are correspondingly connected to the plurality of bit lines 30 one by one. The number of bit lines 30 to which each memory structure 10 is connected is greater than the number of word lines 20. Thus, when the number of rows and columns of semiconductor structure 100 are equal, semiconductor structure 100 includes a greater number of bit lines 30 than it includes word lines 20. That is, the number of bit lines 30 is greater than or equal to the number of word lines 20.

Fig. 4 is an alternative schematic view of a semiconductor structure provided by an embodiment of the present disclosure, and fig. 4 shows semiconductor structure 10 of fig. 1. In the embodiments of the present disclosure, referring to fig. 1 and 4, in each memory structure 10, channels formed by a plurality of semiconductor channels 120 extend along a first direction X. In the region of the channel of each semiconductor channel 120, the two gate structures 110 at least partially surround the corresponding semiconductor channel 120, such that a gate is formed on the region of each semiconductor channel 120 surrounded by the gate structures 110; other regions on both sides of the gate corresponding to each semiconductor channel 120 respectively form a source or a drain. That is, each gate structure 110 at least partially surrounds a side of a corresponding semiconductor channel 120, forming a plurality of vertical fully-Around gate transistors (VGAA, vertical Gate All Around). Each VGAA transistor and its corresponding memory element 140 form a memory Cell (Cell).

It is understood that each gate structure at least partially surrounds a side of a corresponding semiconductor channel, and that each word line is correspondingly connected to each gate structure. The first end of each storage element is correspondingly connected with a bit line; the second end of each memory element is correspondingly connected with the end of the semiconductor channel. Each word line and each bit line extend in different directions, and each memory structure is connected with a plurality of bit lines. Thus, each memory structure comprises a plurality of memory cells, and the memory cells connected to the same gate structure are connected with a plurality of bit lines in a one-to-one correspondence manner, so that when each gate structure is activated, one bit line can only read the data of one memory element corresponding to the gate structure. Thus, when each gate structure is activated, only one bit line connected with the corresponding storage element is opened, so that only the data of one storage element is read or written, that is, the operation mode of the 1T1MTJ is realized. Thus, the read and write operations of the bit lines can be resolved, namely: only the data in one storage element may be operated on.

In some embodiments of the present disclosure, in each memory structure, each gate structure extends in a vertical direction, and a number of semiconductor channels are stacked in a stepped shape at intervals in the vertical direction, wherein the number of bit lines is the same as the number of semiconductor channels.

In the presently disclosed embodiment, with continued reference to fig. 4, each gate structure 110 extends in a vertical direction Z to encompass the sides of each semiconductor channel 120, such that the corresponding gates of each gate structure 110 are connected in series with one another. The plurality of semiconductor channels 120 are stacked in a stepped shape at intervals along the vertical direction Z, and thus, a plurality of VGAA transistors formed by the semiconductor channels 120 and the gate structure 110 are stacked along the vertical direction Z.

It should be noted that the memory structure 10 illustrated in fig. 2,3 and 4 is only for illustrative purposes, and the semiconductor channels 120 may be stacked in any direction. For example, a plurality of semiconductor channels 120 may be stacked in the first direction X, and at this time, the word line 20 may extend in the second direction Y, and the bit line 30 may extend in the vertical direction Z.

It will be appreciated that in each memory structure, several semiconductor channels are stacked in a stepped manner at intervals in the vertical direction. Thus, the plurality of VGAA transistors included in each memory structure are stacked together, so that the area of a chip can be reduced, and the integration level can be improved.

Meanwhile, a plurality of grids contained in each grid structure are connected in series, so that the embodiment of the disclosure can simultaneously select multi-bit data; thus, the number of gating bits is increased.

In some embodiments of the present disclosure, each storage structure further comprises: a source structure; each memory structure comprises two gate structures; the source electrode structure extends along the vertical direction; the source structure is located between the two gate structures.

In the disclosed embodiment, with continued reference to fig. 4, each memory structure 10 includes one source structure 130, and each memory structure 10 includes two gate structures 110. The source structure 130 extends in a vertical direction. The two gate structures 110 and the first semiconductor channel 121 together constitute a first VGAA transistor and a second VGAA transistor. The source of the first VGAA transistor and the source of the second VGAA transistor are both disposed on the first semiconductor channel 121; and, the source of the first VGAA transistor and the source of the second VGAA transistor are both located between the two gate structures 110. That is, the first VGAA transistor and the second VGAA transistor share a source. Accordingly, the second semiconductor channel 122 forms two corresponding VGAA transistors, and the two VGAA transistors corresponding to the second semiconductor channel 122 share the source.

In the embodiment of the disclosure, referring to fig. 1 and 4, the VGAA transistor corresponding to each semiconductor channel 120 shares a source. For each memory structure 10, the sources of the plurality of VGAA transistors are all connected to the same source structure 130.

Fig. 5 is an alternative schematic diagram of a semiconductor structure provided in an embodiment of the disclosure, fig. 5 is a perspective view of the semiconductor structure in fig. 1, and fig. 5 illustrates a connection relationship between a source wire and a memory structure.

In the embodiment of the present disclosure, referring to fig. 1, 4 and 5, the first semiconductor channel 121 and the second semiconductor channel 122 are connected to the source structure 130. The source structures 130 included in each column of memory structures 10 are connected to the same source line 40. The source wires 40 extend along the second direction Y.

It should be noted that the arrangement of the source wires 40 in fig. 5 is only for example, and the source wires 40 may also extend along the first direction X to connect the source structures 130 of each row of the memory structures 10. The substrate, bit lines, and word lines are not shown in fig. 5.

It will be appreciated that each storage structure further comprises: a source structure; each memory structure comprises two gate structures; the source electrode structure extends along the vertical direction; a source structure is located between two of the gate structures. Thus, the two VGAA transistors corresponding to each semiconductor channel share the source electrode, so that the chip area can be further reduced, and the integration level can be improved.

In some embodiments of the present disclosure, each semiconductor channel extends along a first direction; the bit lines extend along a first direction, and the word lines extend along a second direction; the second direction intersects the first direction.

In the disclosed embodiment, referring to fig. 1, each semiconductor channel 120 extends along a first direction X, a plurality of bit lines 30 each extend along the first direction, and a plurality of word lines 20 each extend along a second direction.

It should be noted that the semiconductor structure illustrated in fig. 1 is only for illustration, and the bit line 30 and the word line 20 may extend in any two intersecting directions, respectively. For example, when the word lines 20 each extend in the first direction X, the bit lines 30 may extend in the second direction Y.

In some embodiments of the present disclosure, several storage structures form an array of P rows and Q columns; wherein each row of storage structures is arranged along the second direction, and each column of storage structures is arranged along the first direction; for each row of memory structures, memory elements corresponding to semiconductor channels located at the same layer are connected to the same bit line.

In the disclosed embodiment, with reference to fig. 1 and 2, a number of memory structures 10 form an array of P rows and Q columns; wherein each row of memory structures 10 is arranged along the second direction Y and each column of memory structures is arranged along the first direction X of 10. For each row of memory structures 10, the first semiconductor channels 121 of the memory structures 10 are located in the same semiconductor channel layer, and the memory elements 140 to which the first semiconductor channels 121 are connected to the same bit line 30. The second semiconductor channel 122 of the memory structure 10 is located in the same semiconductor channel layer, and the memory element 140 to which the second semiconductor channel 122 is connected to the same bit line 30. That is, for each row of memory structures 10, the memory elements 140 corresponding to the semiconductor channels 120 located at the same layer are connected to the same bit line 30.

In some embodiments of the present disclosure, the bit lines are all disposed at the same height and are all meandering.

In the embodiment of the present disclosure, referring to fig. 1, 2 and 3, several bit lines 30 are all disposed at the same height and are all zigzag. For each bit line 30, the section disposed directly above the semiconductor channel 120 is used to connect the memory element 140, thereby avoiding the effect on the word line 20 and the source line 40. For two bit lines 30 of each column of memory structures 10, the sections for connecting the memory elements 140 are alternately arranged in the first direction X.

In some embodiments of the present disclosure, the plurality of bit lines are alternately disposed at the first height or the second height along the second direction; the bit lines at the first height are linear, and the bit lines at the second height are zigzag.

Fig. 6 is an alternative schematic diagram of a semiconductor structure provided in an embodiment of the disclosure, and fig. 6 illustrates another connection relationship between a bit line and a memory structure. Fig. 7 and 8 are top views of fig. 6, in which fig. 7 illustrates a connection of a bit line of a first height to a memory structure and fig. 8 illustrates a connection of a bit line of a second height to a memory structure.

In the disclosed embodiment, referring to fig. 6 and 8, each column of memory structures 10 includes two bit lines 30, one bit line 30 being disposed at a second height; the bit line 30 is zigzag, and a portion of the bit line for connecting the memory element 140 is located directly above the semiconductor channel 120, and the rest is far away from the area directly above the semiconductor channel 120, so as to avoid interference to the linear bit line 30 and the corresponding contact structure of the linear bit line 30.

In the disclosed embodiment, with reference to fig. 6 and 7, another bit line 30 of each column of memory structures 10 is disposed at a first height; the bit line 30 is linear and is located directly above the semiconductor channel 120; the second height is less than the first height.

That is, the two bit lines 30 of each column of the memory structure 10 are respectively disposed at a first height and a second height, wherein the bit lines 30 at the first height are linear and are located directly above the semiconductor channel 120; the bit line 30 at the second height is meandering and the second height is smaller than the first height. In the second direction Y, the bit lines 30 are alternately arranged at the first height or the second height.

It is understood that the bit lines are alternately arranged at the first height or the second height along the second direction; the bit lines at the first height are linear, and the bit lines at the second height are zigzag. Like this, compare in the mode that all bit lines all set up at same height, adopt this disclosed embodiment to set up a plurality of bit lines at a plurality of wire layers, increased the interval between the bit line to, reduced the electric leakage risk of semiconductor structure.

In some embodiments of the present disclosure, the number of bit lines and the number of semiconductor channel layers are equal for each row of memory structures.

In the embodiment of the disclosure, with continued reference to fig. 1, the number of semiconductor channels 120 of each memory structure 10 is 2, and in order to ensure that the memory elements 140 corresponding to each gate structure 110 are connected to the bit lines 30 in a one-to-one correspondence, the number of bit lines 30 included in each corresponding row of memory structures 10 is 2. That is, the number of bit lines 30 and the number of semiconductor channels 120 are equal for each row of memory structures 10.

In other embodiments of the present disclosure, each semiconductor channel extends along a first direction; the bit lines extend along the third direction, and the word lines extend along the fourth direction; the third direction and the fourth direction both intersect in the first direction.

Fig. 9 is another optional schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure, and it should be noted that, the number of layers of the semiconductor channel 120 shown in fig. 9 may be 1 or more, and the number of gate structures 110 may be 1 or more; the number of gate structures 110 is exemplified by 2 for the number of layers of semiconductor channels 120.

It should be further noted that fig. 9 only illustrates the 1 st to 5 th column memory structures 10, and the M-1 st to M-th column memory structures 10. Other portions of semiconductor structure 100 may be understood with reference to the illustrated portions. For example, the arrangement of the memory structures 10 of the 5 th to M-2 th column memory structures 10 can be understood with reference to the 1 st to 5 th column memory structures 10 in FIG. 9. The substrate, word lines, and bit lines are not illustrated in fig. 9.

In the embodiment of the present disclosure, with reference to fig. 4 and fig. 9, a plurality of storage structures 10 are arranged in a staggered manner, so as to form an array of N rows and M columns, where N and M are both greater than or equal to 2. Each column of memory structures 10 is arranged along a first direction X, and each row of memory structures 10 is arranged along a third direction U. In each memory structure 10, channels formed by the plurality of semiconductor channels 120 extend along the first direction X. In the region of the channel of each semiconductor channel 120, the two gate structures 110 at least partially surround the corresponding semiconductor channel 120, such that a gate is formed on the region of each semiconductor channel 120 surrounded by the gate structures 110; other regions on both sides of the gate corresponding to each semiconductor channel 120 respectively form a source or a drain. That is, each gate structure 110 at least partially surrounds a side of a corresponding semiconductor channel 120, forming a plurality of VGAA transistors. Each VGAA transistor and its corresponding memory cell 140.

It should be noted that, in fig. 9, the first direction X and the third direction U are perpendicular to the vertical direction Z, the third direction U intersects the first direction X, and the first direction X and the third direction U may be any included angle, and then an exemplary description is performed with the included angle between the first direction X and the third direction U being 120 degrees.

Fig. 10 illustrates the connection of the memory structure 10 and the word line 20 in fig. 9, and the connection of the memory structure 10 and the bit line 30. It should be noted that, the fourth direction V shown in fig. 10 is perpendicular to the vertical direction Z, the fourth direction V intersects the first direction X, the third direction U and the fourth direction V may be any included angle, and the subsequent exemplary description is performed with the included angle between the third direction U and the fourth direction V being 60 degrees.

It should be further noted that fig. 10 only illustrates the memory structures 10 of columns 1 to 3 in fig. 9, and the connection relationship between the rest of the memory structures 10 and the bit lines 30 in the array in fig. 9 can be understood by referring to fig. 10, and the connection relationship between the rest of the memory structures 10 and the word lines 20 in the array in fig. 9 can be understood by referring to fig. 10. Fig. 10 does not illustrate a substrate.

Fig. 11 and 12 illustrate a portion of the structure of fig. 10, wherein fig. 11 illustrates a connection of a bit line 30 of a first height to the memory structure 10, and fig. 12 illustrates a connection of a bit line 30 of a second height to the memory structure 10.

In the embodiment of the present disclosure, referring to fig. 11, the 1 st column of memory structures 10 includes 2 bit lines 30 located at a first height, and both the bit lines 30 extend along a third direction U. Referring to fig. 12, the 1 st column of memory structures 10 includes two bit lines 30 at a second height, and the two bit lines 30 extend along a third direction U. That is, referring to fig. 11 and 12, the memory element 140 included in the column 1 memory structure 10 is connected to 4 bit lines, and the 4 bit lines extend along the third direction U. The memory elements 140 connected to the first semiconductor channel 121 are correspondingly connected to the two bit lines 30, wherein the memory elements 140 located on the same side of the source structure 130 are connected to the same bit line 30. The memory element 140 connected to the second semiconductor channel 122 is connected to two other bit lines 30, wherein the memory elements 140 located on the same side of the source structure 130 are connected to the same bit line 30.

Accordingly, in connection with fig. 9, 11 and 12, 4 bit lines 30 are connected to each of the memory structures 10 of the 2 nd to M th columns of memory structures 10. That is, the bit lines 30 extend along the third direction U, and the memory cells included in each memory structure 10 are connected to the bit lines 30 in a one-to-one correspondence.

In the embodiment of the disclosure, referring to fig. 9 and 10, for the 1 st column of memory structures 10, the 1 st memory structure 10 intersects the 1 st word line 20 and the 2 nd word line 20, and two gate structures 110 included in the 1 st memory structure 10 are connected to the 1 st word line 20 and the 2 nd word line 20, respectively. The 2 nd memory structure 10 intersects the 2 nd and 3 rd word lines 20 and 20, and two gate structures 110 of the 2 nd memory structure 10 are connected to the 2 nd and 3 rd word lines 20 and 20, respectively. The 1 st word line 20, the 2 nd word line 20, and the 3 rd word line 20 all extend in the fourth direction V.

That is, the plurality of word lines 20 extend along the fourth direction V, each memory structure 10 intersects with two word lines 20, and two gate structures 110 included in each memory structure 10 are connected to two word lines 20 in a one-to-one correspondence, that is: each memory structure 10 includes memory cells that are correspondingly connected to two word lines 20.

It is understood that the bit lines extend in the third direction and the word lines extend in the fourth direction. Thus, each word line and each bit line extend in different directions, respectively, wherein each word line is correspondingly connected to each gate structure, and each gate structure at least partially surrounds a side surface of a corresponding semiconductor channel. Each memory structure is connected with a plurality of bit lines; the first end of each memory element is correspondingly connected with a bit line, and the second end of each memory element is correspondingly connected with the end part of the semiconductor channel. Thus, the memory cells corresponding to each gate structure are connected with a plurality of bit lines in a one-to-one correspondence. That is, the plurality of memory cells corresponding to each memory structure are not simultaneously connected to the same bit line and the same word line. Thus, when each gate structure is activated, one bit line can only read the data of one memory cell, namely, the operation mode of the 1T1MTJ is realized. Thus, the read and write operations of the bit lines are distinguishable, namely: only the data in one storage element may be operated on. Meanwhile, the plurality of storage structures 10 are arranged in a staggered manner, so that the area of a chip can be further reduced, and the integration level is improved.

In some embodiments of the present disclosure, a plurality of storage structures are arranged in a staggered manner, forming an array of N rows and M columns; wherein each column of storage structures is arranged along a first direction, and each row of storage structures is arranged along a third direction; for each column of memory structures, memory elements located on the same side of the source structure and connected to the same layer of semiconductor channels are connected to the same bit line.

In the embodiment of the present disclosure, referring to fig. 4, 11 and 12, the first semiconductor channels 121 of several memory structures 10 are located in the same semiconductor channel layer. The first gate structure 111 and the second gate structure 112 are located on both sides of the source structure 130, respectively, for each memory structure 10. The two memory elements 140 corresponding to the first gate structure 111 are respectively connected to the two bit lines 30, and the two memory elements 140 corresponding to the second gate structure 112 are respectively connected to the other two bit lines 30.

In the embodiment of the disclosure, referring to fig. 4, 11 and 12, for the column 1 memory structure 10, all the first semiconductor channels 121 are located in the same layer, and all the second semiconductor channels 122 are located in the same layer. The memory elements 140 connected to the first semiconductor channel 121 are correspondingly connected to two bit lines 30, wherein the memory element 140 corresponding to the first gate structure 111 is connected to one bit line 30, and the memory element 140 corresponding to the second gate structure 112 is connected to the other bit line 30.

Accordingly, in fig. 9, 11 and 12, the memory elements 140 of the 2 nd to M th column of the memory structure 10 are correspondingly connected to 4 bit lines 30. That is, for each column of memory structures 10, the memory elements 140 located on the same side of the source structure 130 and connected to the same layer of semiconductor channels 120 are connected to the same bit line 30.

In some embodiments of the present disclosure, the number of bit lines is twice the number of semiconductor channel layers per column of memory structure.

In the embodiment of the disclosure, referring to fig. 9, 11 and 12, for each column of memory structures 10, the number of semiconductor channels 120 of each memory structure 10 is 2, and in order to ensure that the memory elements 140 corresponding to each gate structure 110 are connected to the bit lines 30 in a one-to-one correspondence, the number of corresponding bit lines 30 is 4. That is, the number of bit lines 30 is twice the number of layers of the semiconductor channel 120 for each column of memory structures 10.

In some embodiments of the present disclosure, two gate structures included in each memory structure are correspondingly connected to two adjacent word lines; each word line is connected to one gate structure on the memory structure that intersects it.

Fig. 15 illustrates the connection relationship between the memory structure 10 and the word line 20 in fig. 9, fig. 15 illustrates only the memory structures 10 of columns 1 to 3 in fig. 9, and the connection relationship between the remaining memory structures 10 and the word line 20 in the array in fig. 9 can be understood with reference to fig. 15. The substrate and bit lines are not illustrated in fig. 15.

In the embodiment of the present disclosure, referring to fig. 9 and 15, two gate structures 110 included in each memory structure 10 are a first gate structure 111 and a second gate structure 112, respectively. The memory structures 10 located in row 1 and column 1 intersect the 2 nd word line 20 and the second gate structure 112 thereof is connected to the 2 nd word line. The memory structures 10 located in row 1 and column 1 intersect the 1 st word line 20, and the first gate structure 111 thereof is connected to the 1 st word line.

Accordingly, referring to fig. 9 and 15, each memory structure 10 includes two gate structures 110 correspondingly connected to two adjacent word lines 20; each word line 20 is connected to one gate structure 110 on the memory structure 10 that intersects it.

In some embodiments of the present disclosure, each memory structure includes two gate structures, a first gate structure and a second gate structure, respectively; for each column of storage structures, the first grid structure of the n-1 storage structure and the second grid structure of the n storage structure are connected to the same word line; the second grid structure of the n-1 storage structure and the first grid structure of the n-2 storage structure are connected to the same word line; n is 2 or more.

In the presently disclosed embodiments, referring to fig. 9 and 15, for a1 st column of memory structures 10, the 1 st memory structure 10 intersects a1 st word line 20 and a2 nd word line 20; the 1 st memory structure 10 has a first gate structure 111 connected to the 1 st word line 20, and the 1 st memory structure 10 has a second gate structure 112 connected to the 2 nd word line 20.

Accordingly, for the 1 st column of memory structures 10, the 2 nd memory structure 10 intersects the 2 nd and 3 rd word lines, and the first gate structure 111 of the 2 nd memory structure 10 is connected to the 2 nd word line 20, and the second gate structure 112 of the 2 nd memory structure 10 is connected to the 3 rd word line 20. The 3 rd memory structure 10 crosses the 3 rd word line and the 4 th word line, and the first gate structure 111 of the 3 rd memory structure 10 is connected to the 3 rd word line 20, and the second gate structure 112 of the 3 rd memory structure 10 is connected to the 4 th word line 20.

That is, for the 1st column of memory structures 10, the first gate structure 111 of the 2 nd memory structure 10 and the second gate structure 112 of the 1st memory structure 10 are connected to the 2 nd word line 20. The second gate structure 112 of the 2 nd memory structure 10 and the first gate structure 111 of the 3 rd memory structure 10 are connected to the 3 rd word line 20.

Accordingly, the gate structures 110 included in the 2 nd to M th column memory structures 10 are connected to the corresponding word lines 20. That is, for each column of memory structures 10, the first gate structure 111 of the n-1 th memory structure 10 is connected to the same word line 20 as the second gate structure 112 of the n-th memory structure 10; the second gate structure 112 of the n-1 th memory structure 10 is connected to the same word line 20 as the first gate structure 111 of the n-2 th memory structure 10.

In some embodiments of the present disclosure, every two bit lines are alternately disposed at a first height or a second height along a first direction; wherein the bit line at the first level is disposed directly above the bit line at the second level.

In the embodiment of the disclosure, in combination with fig. 9 and 10, the plurality of memory structures 10 are arranged in a staggered manner, so that the memory element 140 corresponding to each first gate structure 111 of the column 2 memory structure 10 is disposed between every two second gate structures 112 of the column 1 memory structure 10. In the fourth direction U, the memory elements 140 corresponding to the first gate structures 111 of the 2 nd column of memory structures 10 are on the same extension line in one-to-one correspondence with the memory elements 140 corresponding to the second gate structures 112 of the 1 st column of memory structures 10.

Accordingly, the memory elements 140 included in the 3 rd to M th column memory structures 10 are also arranged in the 1 st and 2 nd column memory structures 10. Thus, the semiconductor structure 100 includes memory elements 140 arranged in a hexagonal pattern.

Fig. 13 and 14 illustrate a connection structure of the memory element 10 and the bit line 30 in fig. 10, wherein fig. 13 illustrates a first bit line 301, a second bit line 302, and fig. 14 illustrates a second bit line 302 and a third bit line 303.

It should be noted that fig. 13 and 14 only illustrate connection structures of the bit lines 30 and the partial memory elements 140 of the 1 st column memory structure 10 to the 3 rd column memory structure 10. The remaining portion of memory elements 140 of column 1 memory structure 10 through column 3 memory structure 10, and column 4 through column M memory structure 10, may be understood with reference to fig. 13 and 14.

In the embodiment of the disclosure, referring to fig. 10, fig. 12, and fig. 13, for the 1 st column of memory structures 10, the memory element 140 corresponding to the second gate structure 112 is connected to two bit lines 30; the memory element 140 connected to the second semiconductor channel 122 is connected to the first bit line 301, and the first bit line 301 is located at the second height. For the 2 nd column of memory structures 10, the memory elements 140 corresponding to the first gate structures 111 are connected to two bit lines 30; the memory element 140 connected to the first semiconductor channel 121 is connected to the second bit line 302, and the second bit line 302 is located at the second height. That is, the memory elements 140 to which the first bit lines 301 and the second bit lines 302 are connected are located on the same extension line, and the first bit lines 301 and the second bit lines 302 are located at the same height.

In the embodiment of the disclosure, referring to fig. 10, 11 and 14, for the 1 st column of memory structures 10, the memory element 140 corresponding to the second gate structure 112 is connected to two bit lines 30; the memory element 140 connected to the first semiconductor channel 122 is connected to the third bit line 303, and the third bit line 303 is located at the first height. For the 2 nd column of memory structures 10, the memory elements 140 corresponding to the first gate structures 111 are connected to two bit lines 30; the memory element 140 connected to the second semiconductor channel 122 is connected to the fourth bit line 302, and the fourth bit line 304 is located at the second height. That is, the memory elements 140 to which the third bit line 303 and the fourth bit line 304 are connected are located on the same extension line, and the third bit line 303 and the fourth bit line 304 are located at the same height.

In the embodiment of the disclosure, the first bit line 301, the second bit line 302, the third bit line 303 and the fourth bit line 304 are sequentially arranged in the first direction X, and the first bit line 301 and the second bit line 302 are located at the same height, and the third bit line 303 and the second bit line 304 are located at the same height. That is, every two bit lines 30 are alternately arranged at the first height or the second height along the first direction X.

In the embodiment of the disclosure, referring to fig. 10 and 13, for the memory structure 10 of the 2 nd column, the memory element 140 corresponding to the first gate structure 111 is connected to the second bit line 302 and connected to the first semiconductor channel 121. Referring to fig. 10 and 14, for the 1 st column of memory structures 10, the memory element 140 corresponding to the second gate structure 112 is connected to the first semiconductor channel 121 and the third bit line 303. And, the third bit line 303 at the first level is disposed directly above the second bit line 302 at the second level.

That is, every two bit lines 30 are alternately arranged at the first height or the second height along the first direction X; wherein the bit line 30 at the first level is disposed directly above the bit line 30 at the second level.

It is understood that each two bit lines are alternately arranged at the first height or the second height along the first direction; wherein the bit line at the first level is disposed directly above the bit line at the second level. Therefore, the bit lines are respectively arranged on the plurality of wire layers, the spacing between the bit lines is increased under the condition of not increasing the area of the chip, and the leakage risk of the semiconductor structure is reduced.

Fig. 16 is a schematic structural diagram of a memory according to an embodiment of the present disclosure, and as shown in fig. 16, a memory 200 includes a semiconductor structure 100.

In some embodiments of the present disclosure, as shown in fig. 16, memory 200 is a magnetic random access memory.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (16)

1. A semiconductor structure, comprising: a plurality of memory structures, a plurality of word lines, and a plurality of bit lines; each storage structure comprises a plurality of grid structures, a plurality of storage elements and a plurality of semiconductor channels;

Each gate structure at least partially surrounds a side of a corresponding semiconductor channel; each word line is correspondingly connected with each grid structure;

a first end of each storage element is correspondingly connected with the bit line; the second end of each storage element is correspondingly connected with the end part of the semiconductor channel;

Each word line and each bit line extend in different directions respectively, and the number of the bit lines is greater than or equal to the number of the word lines;

wherein each of the memory structures is connected to a plurality of the bit lines.

2. The semiconductor structure of claim 1, wherein in each of the memory structures, each of the gate structures extends in a vertical direction, and a plurality of the semiconductor channels are stacked in a stepped shape at intervals in the vertical direction.

3. The semiconductor structure of claim 1, wherein each of the memory structures further comprises: a source structure; the number of the gate structures included in each storage structure is two; the source electrode structure extends along the vertical direction; the source electrode structure is positioned between the two gate electrode structures.

4. The semiconductor structure of claim 3, each semiconductor channel extending in a first direction; the bit lines extend along the first direction, and the word lines extend along the second direction; the second direction intersects the first direction.

5. The semiconductor structure of claim 4, wherein a plurality of said memory structures form an array of P rows and Q columns, P and Q each being 2 or more; wherein each row of the storage structures is arranged along the second direction, and each column of the storage structures is arranged along the first direction;

For each row of the memory structures, the memory elements corresponding to the semiconductor channels located in the same layer are connected to the same bit line.

6. The semiconductor structure of claim 5, wherein a plurality of bit lines are alternately disposed at a first height or a second height along the second direction; the bit lines at the first height are linear, and the bit lines at the second height are zigzag.

7. The semiconductor structure of claim 5, wherein a plurality of bit lines are all disposed at a same height and are all meandering.

8. The semiconductor structure of claim 5, wherein the number of bit lines and the number of semiconductor channel layers are the same for each row of the memory structure.

9. The semiconductor structure of claim 3, wherein each of the semiconductor channels extends along the first direction; a plurality of bit lines extend along a third direction, and a plurality of word lines extend along a fourth direction; the third direction and the fourth direction both intersect in the first direction.

10. The semiconductor structure of claim 9, wherein a plurality of said memory structures are arranged in a staggered manner to form an array of N rows and M columns, N and M being equal to or greater than 2; wherein each column of the storage structures is arranged along the first direction, and each row of the storage structures is arranged along the third direction;

For each column of the memory structures, the memory elements located on the same side of the source structure and connected to the same layer of the semiconductor channels are connected to the same bit line.

11. The semiconductor structure of claim 10, wherein every two bit lines are alternately disposed at a first height or a second height along the first direction; wherein the bit line at the first height is disposed directly above the bit line at the second height.

12. The semiconductor structure of claim 10, wherein the number of bit lines is twice the number of semiconductor channel layers per column of the memory structure.

13. The semiconductor structure of claim 10, wherein two of said gate structures included in each of said memory structures are correspondingly connected to adjacent two of said word lines; each of the word lines is connected to one of the gate structures on the memory structure that intersects it.

14. The semiconductor structure of claim 13, wherein the two gate structures included in each of the memory structures are a first gate structure and a second gate structure, respectively;

For each column of the memory structures, the first gate structure of the n-1 th memory structure and the second gate structure of the n-th memory structure are connected to the same word line; the second gate structure of the n-1 th memory structure and the first gate structure of the n-2 th memory structure are connected to the same word line; n is 2 or more.

15. A memory comprising the semiconductor structure of any of claims 1-14.

16. The memory of claim 15 wherein the memory is a magnetic random access memory MRAM.