TWI832707B - Semiconductor device - Google Patents

Abstract

One embodiment of the present invention provides a semiconductor memory device capable of suppressing an increase in chip area. According to the embodiment, the semiconductor memory device includes a first memory cell array 11_1 and a second memory cell array 11_2. The first memory cell array includes: the first semiconductor 123, which is connected to the first memory cell MC and the first selection transistor ST1; the first word line WL; the first selection gate line SGD; and the first bit line BL, It is connected to the first semiconductor. The second memory cell array includes: a second semiconductor 123 extending in the first direction and connecting the second memory cell MC and the second selection transistor ST1; the second word line WL; the second selection gate line SGD; and 2 bit lines BL connected to the second semiconductor. The first character line and the second character line are electrically connected. The first selection gate line and the second selection gate line are not electrically connected.

Description

Semiconductor device

An embodiment of the present invention relates to a semiconductor memory device.

As a semiconductor memory device, a NAND (Not-AND: NAND) type flash memory is known.

One embodiment of the present invention provides a semiconductor memory device capable of suppressing an increase in chip area.

The semiconductor memory device of the embodiment includes a first memory cell array and a second memory cell array arranged above the first memory cell array in the first direction. The first memory cell array includes: a first semiconductor extending in the first direction and connecting the first memory cell and the first selection transistor; a first word line connected to the gate of the first memory cell; the first selection a gate line connected to the gate of the first selection transistor; and a first bit line connected to the first semiconductor. The second memory cell array includes: a second semiconductor extending in the first direction and connecting the second memory cell and the second selection transistor; a second word line connected to the gate of the second memory cell; the second selection transistor. a gate line connected to the gate of the second selection transistor; and a second bit line connected to the second semiconductor. The first character line and the second character line are electrically connected. The first selection gate line and the second selection gate line are not electrically connected.

Hereinafter, embodiments will be described with reference to the drawings. In addition, in the following description, the same symbols are attached to the components having substantially the same function and structure. It may be omitted when repeated explanation is not necessary. In addition, each embodiment shown below exemplifies a device or method for embodying the technical idea of the embodiment. The technical idea of the embodiment does not specify the materials, shapes, structures, arrangements, etc. of the constituent parts as described below. Various changes can be made to the technical ideas of the embodiments within the scope that does not deviate from the gist of the invention. These embodiments or variations thereof are included in the scope of the invention described in the patent application and their equivalents.

1. First embodiment The semiconductor memory device according to the first embodiment will be described.

1.1 Overall composition of semiconductor memory device First, an example of the overall structure of the semiconductor memory device 1 will be described with reference to FIG. 1 . FIG. 1 is an example of a block diagram showing the overall structure of the semiconductor memory device 1 . In addition, in FIG. 1 , although a part of the connection of each block is shown by an arrow line, the connection between blocks is not limited to this.

The semiconductor memory device 1 is, for example, a three-dimensional stacked NAND flash memory. Three-dimensional stacked NAND flash memory includes a plurality of non-volatile memory cell transistors three-dimensionally arranged on a semiconductor substrate.

As shown in FIG. 1 , the semiconductor memory device 1 includes a plurality of array chips 10 and a circuit chip 20 . The array chip 10 is a chip provided with an array of non-volatile memory cell transistors. The circuit chip 20 is a chip provided with a circuit that controls the array chip 10 . The semiconductor memory device 1 of this embodiment is formed by laminating a plurality of array chips 10 and a circuit chip 20 . Hereinafter, when neither the array chip 10 nor the circuit chip 20 is limited, it is simply referred to as "chip".

In the example of FIG. 1 , the semiconductor memory device 1 includes two array chips 10_1 and 10_2. In addition, the number of array chips 10 may also be three or more.

The array chip 10 includes a memory cell array 11 . The memory cell array 11 is an area in which non-volatile memory cell transistors are three-dimensionally arranged. In the following, when the memory cell array 11 of the array chip 10_1 is limited, it is expressed as the memory cell array 11_1. When defining the memory cell array 11 of the array chip 10_2, it is expressed as a memory cell array 11_2.

The memory cell array 11 includes a plurality of blocks BLK. A block BLK is, for example, a collection of a plurality of memory cells whose data is deleted together. A plurality of memory cell transistors in the block BLK are corresponding to columns and rows. In the example of FIG. 1 , the memory cell array 11 includes BLK0, BLK1, and BLK2. In the following, when the blocks BLK of the memory cell array 11_1 are limited, they are expressed as blocks BLK0_1, BLK1_1, and BLK2_1. When the block BLK of the memory cell array 11_2 is limited, it is expressed as blocks BLK0_2, BLK1_2, and BLK2_2.

The block BLK contains a plurality of string units SU. The string unit SU is, for example, a set of a plurality of NAND strings NS selected together during a writing operation or a reading operation. In the example of FIG. 1 , the block BLK includes four string units SU0, SU1, SU2, and SU3.

The string unit SU contains a plurality of NAND strings NS. A NAND string NS includes a collection of multiple memory cell transistors connected in series.

In addition, the number of blocks BLK in the memory cell array 11 and the number of string units SU in the block BLK are arbitrary. The circuit configuration of the memory cell array 11 will be described later.

Next, the circuit chip 20 will be described. The circuit chip 20 includes a sequencer 21, a voltage generating circuit 22, a column driver 23, a column decoder 24, and a sense amplifier 25.

The sequencer 21 is a circuit that controls the semiconductor memory device 1 . The sequencer 21 is connected to the voltage generation circuit 22 , the column driver 23 , the column decoder 24 , and the sense amplifier 25 . Furthermore, the sequencer 21 controls the voltage generation circuit 22, the column driver 23, the column decoder 24, and the sense amplifier 25. In addition, the sequencer 21 controls the overall operation of the semiconductor memory device 1 based on the control of the external controller. More specifically, the sequencer 21 performs writing operations, reading operations, erasing operations, and the like.

The voltage generating circuit 22 is a circuit that generates voltages used in writing operations, reading operations, erasing operations, and the like. The circuit generation circuit 22 is connected to the column driver 23, the sense amplifier 25, and the like. The voltage generation circuit 22 supplies voltage to the column driver 23, the sense amplifier 25, and the like.

The column driver 23 is a driver that supplies voltage to the column decoder 24 . The column driver 23 is connected to the column decoder 24 . The column driver 23 supplies the voltage applied from the voltage generation circuit 22 to the column decoder 24 based on, for example, a column address (page address, etc.). The column address is an address signal specifying the wiring in the column direction of the memory cell array 11 . The page address is an address signal specifying a page to be described later. Address signal supplied from external controller.

The column decoder 24 is a circuit for decoding column addresses. The column decoder 24 selects any block BLK in the memory cell array 11 based on the decoding result of the column address (block address, etc.). The block address is the address signal of the designated block BLK.

More specifically, the column decoder 24 is connected to the memory cell array 11 via a plurality of word lines WL and a plurality of select gate lines SGD and SGS. The word line WL is a wiring used to control the memory cell transistor. The select gate lines SGD and SGS are used for wiring of the selected string unit SU. The column decoder 24 applies the voltage supplied from the column driver 23 to the word line WL corresponding to the selected block BLK and the select gate lines SGD and SGS.

In this embodiment, the word line WL of the memory cell array 11_1 and the word line WL of the memory cell array 11_2 are commonly connected to the column decoder 24 . Similarly, the selection gate line SGS of the memory cell array 11_1 and the selection gate line SGS of the memory cell array 11_2 are commonly connected to the column decoder 24 . In addition, the selection gate line SGD of the memory cell array 11_1 and the selection gate line SGD of the memory cell array 11_2 are respectively independent and connected to the column decoder 24 . That is, the selection gate line SGD of the memory cell array 11_1 and the selection gate line SGD of the memory cell array 11_2 are not electrically connected. In other words, the memory cell array 11_1 and the memory cell array 11_2 share the word line WL and the select gate line SGS. Moreover, the memory cell array 11_1 and the memory cell array 11_2 do not share the select gate line SGD.

The sense amplifier 25 is a circuit for writing and reading data. During the reading operation, the sense amplifier 25 senses the data read from any string unit SU in any block BLK. In addition, the sense amplifier 25 supplies a voltage corresponding to the written data to the memory cell array 11 during the writing operation.

The sense amplifier 25 is connected to the memory cell array 11 via a plurality of bit lines BL. The bit line BL is commonly connected to one NAND string NS of each string unit SU in the memory cell array 11 . In this embodiment, the bit lines BL of the memory cell arrays 11_1 and 11_2 are commonly connected to the sense amplifier 25 . That is, the memory cell array 11_1 and the memory cell array 11_2 share the bit line BL.

1.2 Circuit composition of memory cell array Next, an example of the circuit configuration of the memory cell arrays 11_1 and 11_2 will be described with reference to FIG. 2 .

As shown in FIG. 2 , each string unit SU of the memory cell arrays 11_1 and 11_2 includes a plurality of NAND strings NS.

The NAND string NS includes a plurality of memory cell transistors MC and selection transistors ST1 and ST2. In the example of Figure 2, the NAND string NS includes five memory cell transistors MC0˜MC4. In addition, the number of memory cell transistors MC is arbitrary.

Memory cell transistor MC holds data non-volatilely. The memory cell transistor MC includes a control gate and a charge accumulation layer. The memory cell transistor MC can be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon: metal-oxide-nitride-oxide-silicon) type or a FG (Floating Gate: floating gate) type. The MONOS type uses an insulating layer for the charge accumulation layer. The FG type uses a conductive layer as the charge accumulation layer. Next, the case where the memory cell transistor MC is of the MONOS type will be described.

The selection transistors ST1 and ST2 are used to select the string unit SU during various operations. The number of transistors ST1 and ST2 can be selected as desired. The NAND string NS only needs to include more than one selection transistor ST1 and ST2 respectively.

The memory cell transistor MC and the current paths of the selection transistors ST1 and ST2 in each NAND string NS are connected in series. In the example of Figure 2, from the bottom side of the paper to the top, the current paths of the selection transistor ST2, the memory cell transistors MC0, MC1, MC2, MC3, and MC4, and the selection transistor ST1 are connected in series in this order. . The drain of the selection transistor ST1 is connected to any bit line BL. The source of the selection transistor ST2 is connected to the source line SL.

The drains of the plurality of selection transistors ST1 in the string unit SU are respectively connected to different bit lines BL. In the example of FIG. 2 , the drains of n+1 (n is an integer above 0) selection transistors ST1 in the string unit SU are respectively connected to n+1 bit lines BL0˜BLn. Moreover, the drain electrode of one selection transistor ST1 in each string unit SU of the memory cell arrays 11_1 and 11_2 is commonly connected to one bit line BL. That is, the memory cell arrays 11_1 and 11_2 share the bit line BL.

The control gates of a plurality of memory cell transistors MC0 ~ MC4 included in one block BLK of the memory cell array 11_1 and one block BLK of the memory cell array 11_2 are respectively commonly connected to the word lines WL0 ~ WL4. More specifically, the block BLK0_1 of the memory cell array 11_1 includes a plurality of memory cell transistors MC0. Similarly, the block BLK0_2 of the memory cell array 11_2 includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in blocks BLK0_1 and BLK0_2 are commonly connected to a word line WL0. Memory cell transistors MC1 ~ MC4 are also connected to word lines WL1 ~ WL4 respectively. That is, blocks BLK0_1 and BLK0_2 share the word line WL. Similarly, blocks BLK1_1 and BLK1_2 share the word line WL. Blocks BLK2_1 and BLK2_2 share the word line WL.

The gates of a plurality of selection transistors ST2 included in one block BLK of the memory cell array 11_1 and one block BLK of the memory cell array 11_2 are commonly connected to one selection gate line SGS. More specifically, for example, blocks BLK0_1 and BLK0_2 respectively include a plurality of selection transistors ST2. The gates of the plurality of selection transistors ST2 in blocks BLK0_1 and BLK0_2 are commonly connected to one selection gate line SGS. That is, blocks BLK0_1 and BLK0_2 share the selection gate line SGS. Similarly, blocks BLK1_1 and BLK1_2 share the select gate line SGS. Blocks BLK2_1 and BLK2_2 share the selection gate line SGS. In addition, the blocks BLK0_1~BLK2_1 and BLK0_2~BLK2_2 can also share the selection gate line SGS.

The gates of the plurality of selection transistors ST1 in the string unit SU are commonly connected to one selection gate line SGD. More specifically, the string units SU0 in the block BLK0_1 of the memory cell array 11_1 respectively include a plurality of selection transistors ST1. The gates of the plurality of selection transistors ST1 in the string unit SU0 are commonly connected to the selection gate line SGD0_1. Similarly, the gates of the plurality of selection transistors ST1 in the string unit SU1 are commonly connected to the selection gate line SGD1_1. The gates of the plurality of selection transistors ST1 in the string unit SU2 are commonly connected to the selection gate line SGD2_1. The same goes for blocks BLK1_1 and BLK2_1.

The string units SU0 in the block BLK0_2 of the memory cell array 11_2 respectively include a plurality of selection transistors ST1. The gates of the plurality of selection transistors ST1 in the string unit SU0 are commonly connected to the selection gate line SGD0_2. Similarly, the gates of the plurality of selection transistors ST1 in the string unit SU1 are commonly connected to the selection gate line SGD1_2. The gates of the plurality of selection transistors ST1 in the string unit SU2 are commonly connected to the selection gate line SGD2_2. The same goes for blocks BLK1_2 and BLK2_2.

The word lines WL0˜WL4, the select gate lines SGS, and the select gate lines SGD0_1˜SGD2_1 and SGD0_2˜2_2 are respectively connected to the column decoder 24.

Bit line BL is connected to sense amplifier 25 .

The source line SL is shared among a plurality of blocks BLK, such as the memory cell arrays 11_1 and 11_2.

Hereinafter, within one string unit SU, a set of a plurality of memory cell transistors MC connected to one word line WL is described as a "cell unit CU". For example, when the memory cell transistor MC stores 1-bit data, the memory capacity of the cell unit CU is defined as "1 page of data." Based on the number of bits of data stored in the memory cell transistor MC, the cell unit CU can have a memory capacity of more than 2 pages of data.

1.3 Connection of various wirings between chips Next, the connection of various wirings between chips will be described with reference to FIG. 3 . FIG. 3 is a conceptual diagram showing the configuration of the memory cell arrays 11_1 and 11_2 and the circuit chip 20.

As shown in FIG. 3 , a memory cell array 11_1 is disposed on the circuit chip 20 . Furthermore, a memory cell array 11_2 is arranged above the memory cell array 11_1. In other words, array chips 10_1 and 10_2 are stacked on the circuit chip 20 .

The memory cell arrays 11_1 and 11_2 include cell parts and plug connection parts. The cell part is the area where the memory cell transistor is arranged. The plug connection portion is provided with a plurality of contact plug areas respectively connected to the word line WL and the select gate lines SGD and SGS.

The bit lines BL arranged in the cell portions of the memory cell arrays 11_1 and 11_2 are commonly connected to the sense amplifier 25 of the circuit chip 20 .

The word lines WL and the select gate lines SGS of the memory cell arrays 11_1 and 11_2 are commonly connected to the column decoder 24 of the circuit chip 20 .

The select gate line SGD of the memory cell array 11_1 is connected to the column decoder 24 of the circuit chip 20 . The select gate line SGD of the memory cell array 11_2 is connected to the column decoder 24 of the circuit chip 20 . The select gate line SGD of the memory cell array 11_1 and the select gate line SGD of the memory cell array 11_2 are not electrically connected.

1.4 Planar composition of memory cell array Next, the structure of the memory cell array 11 will be described with reference to FIGS. 4 and 5 . Figure 4 is a top view of the memory cell array 11_2. Figure 5 is a top view of the memory cell array 11_1. In addition, in the examples of FIG. 4 and FIG. 5 , in order to simplify the description, the case where each memory cell array 11 includes four blocks BLK0 to BLK3 and each block BLK includes one string unit SU will be described. In addition, in the examples of FIGS. 4 and 5 , the insulating layer is omitted.

In the following description, the X direction corresponds to the extending direction of the word line WL. The Y direction intersects the X direction. The Y direction corresponds to the extending direction of the bit line BL. The Z direction corresponds to the direction crossing the X direction and the Y direction.

First, the planar structure of the memory cell array 11_2 will be described.

As shown in FIG. 4 , four blocks BLK0 to BLK3 are arranged in the Y direction from the upper side to the lower side of the paper. In each block BLK, a plurality of wiring layers 102 are stacked apart in the Z direction. For example, there are seven wiring layers 102 that function as select gate lines SGS, word lines WL0 to WL4, and select gate lines SGD respectively. Slits SLT are respectively provided on two side surfaces of each wiring layer 102 facing the Y direction. The gap SLT extends in the X direction and the Z direction. The gap SLT separates the wiring layer 102 from each block BLK.

The block BLK includes a cell part and a plug connection part.

A plurality of memory conductive pillars MP are provided at the cell portion. The memory guide post MP is a guide post corresponding to the NAND string NS. The details of the structure of the memory guide pillar MP will be described later. The memory guide pillar MP extends in the Z direction. The memory conductive pillar MP penetrates (passes through) a plurality of wiring layers 102 stacked in the Z direction.

In the example of FIG. 4 , a plurality of memory guide pillars MP in the block BLK are staggeredly arranged into four rows in the X direction. In addition, the arrangement of the memory guide pillars MP can be designed arbitrarily. The memory guide pillars MP may also be arranged in a staggered arrangement of 8 rows, for example. In addition, the arrangement of the memory conductive pillars MP may not be a staggered arrangement.

Above the memory conductive pillar MP, a plurality of bit lines BL are arranged in the X direction. The bit line BL extends in the Y direction. The memory conductor MP is electrically connected to any bit line BL.

The plug connection portion of the memory cell array 11_2 includes the CP1 region.

The CP1 area is an area where a plurality of contact plugs CP1 are provided. The contact plug CP1 extends in the Z direction. The contact plug CP1 is connected to any one of the wiring layers 102 . Moreover, the contact plug CP1 is not electrically connected to other wiring layers 102 . In the example of FIG. 4 , seven contact plugs CP1 are provided in one CP1 area. The seven contact plugs CP1 are respectively connected to the seven wiring layers 102 . Hereinafter, when limiting the case of the contact plugs CP1 respectively connected to the word lines WL0, WL1, WL2, WL3, and WL4, they are expressed as contact plugs CP1_w0, CP1_w1, CP1_w2, CP1_w3, and CP1_w4. When limiting the case of contact plugs CP1 respectively connected to the selection gate lines SGD and SGS, they are expressed as contact plugs CP1_d and CP1_s. In the example of FIG. 4 , the contact plugs CP1_s, CP1_w0, CP1_w1, CP1_w2, CP1_w3, CP1_w4, and CP1_d are sequentially arranged in a row from the end of the memory cell array 11_2 in the X direction toward the cell. In addition, the arrangement of the contact plug CP1 is arbitrary. For example, the contact plugs CP1 may be arranged in two rows staggered along the X direction.

On the contact plug CP1, a wiring layer 111 is provided. The wiring layer 111 extends along the Y direction from the position connected to the contact plug CP1 to above the adjacent block BLK. More specifically, the wiring layer 111 provided on the contact plug CP1 of the block BLK0 extends above the block BLK1. The wiring layer 111 provided on the contact plug CP1 of the block BLK1 extends above the block BLK0. The wiring layer 111 provided on the contact plug CP1 of the block BLK2 extends to the top of the block BLK3. The wiring layer 111 provided on the contact plug CP1 of the block BLK3 extends to the top of the block BLK2.

An electrode pad PD is provided on the wiring layer 111 . The electrode pad PD is used for electrical connection with other chips.

Next, the planar structure of the memory cell array 11_1 will be described. The following description will focus on points different from the planar configuration of the memory cell array 11_2.

As shown in Figure 5, the structure of the cell part is the same as that of the memory cell array 11_2.

The plug connection part of the memory cell array 11_1 includes a CP1 area and a CP2 area.

The structure of the CP1 region is the same as that of the memory cell array 11_2.

The CP2 area is an area where a plurality of contact plugs CP2 are provided. Contact plug CP2 extends in the Z direction. The contact plug CP2 penetrates the memory cell array 11_1. The contact plug CP2 is not electrically connected to the wiring layer 102 of the memory cell array 11_1. The contact plug CP2 is electrically connected to the contact plug CP1 of the memory cell array 11_2 through the electrode pad PD and the wiring layer 111 of the array chip 10_2 illustrated in FIG. 4 .

More specifically, for example, the contact plug CP2 of the block BLK0 is electrically connected to the contact plug CP1 of the block BLK1 of the memory cell array 11_2. The contact plug CP2 of the block BLK1 is electrically connected to the contact plug CP1 of the block BLK0 of the memory cell array 11_2. The contact plug CP2 of the block BLK2 is electrically connected to the contact plug CP1 of the block BLK3 of the memory cell array 11_2. The contact plug CP2 of the block BLK3 is electrically connected to the contact plug CP1 of the block BLK2 of the memory cell array 11_2.

In the example of FIG. 5 , seven contact plugs CP2 are provided in one CP2 area. The seven contact plugs CP2 correspond to the seven contact plugs CP1 of the memory cell array 11_2 respectively. Hereinafter, when limiting the case of the contact plugs CP2 respectively connected to the contact plugs CP1_w0, CP1_w1, CP1_w2, CP1_w3, and CP1_w4 of the memory cell array 11_2, it is expressed as the contact plugs CP2_w0, CP2_w1, CP2_w2, CP2_w3, and CP2_w4. When limiting the situation of the contact plugs CP2 respectively connected to the contact plugs CP1_d and CP1_s of the memory cell array 11_2, it is expressed as the contact plugs CP2_d and CP2_s.

A wiring layer 111 is provided above the contact plugs CP1 and CP2. The contact plugs CP1_w0˜CP1_w4 and CP1_s are respectively connected to the contact plugs CP2_w0˜CP2_w4 and CP2_s of the adjacent block BLK via the wiring layer 111. In addition, the contact plug CP1_d is not connected to the contact plug CP2_d of the adjacent block BLK. That is, different wiring layers 111 are respectively provided on the contact plugs CP1_d and CP2_d.

More specifically, for example, the contact plug CP1_s of the block BLK0 is electrically connected to the contact plug CP2_s of the block BLK1. The contact plug CP1_w0 of the block BLK0 is electrically connected to the contact plug CP2_w0 of the block BLK1. The contact plug CP1_w1 of the block BLK0 is electrically connected to the contact plug CP2_w1 of the block BLK1. The contact plug CP1_w2 of the block BLK0 is electrically connected to the contact plug CP2_w2 of the block BLK1. The contact plug CP1_w3 of the block BLK0 is electrically connected to the contact plug CP2_w3 of the block BLK1. The contact plug CP1_w4 of the block BLK0 is electrically connected to the contact plug CP2_w4 of the block BLK1. The contact plug CP1_d of the block BLK0 is not electrically connected to the contact plug CP2_d of the block BLK1. The same goes for other blocks BLK.

That is, the word lines WL0˜WL4 and the selection gate line SGS of the block BLK0 of the memory cell array 11_1 are electrically connected to the word lines WL0˜WL4 and the selection gate line SGS of the block BLK0 of the memory cell array 11_2 respectively. Moreover, the select gate line SGD of the block BLK0 of the memory cell array 11_1 is not electrically connected to the select gate line SGDS of the block BLK0 of the memory cell array 11_2. The same goes for other blocks BLK.

An electrode pad PD is provided on the wiring layer 111 . Different wiring layers 111 are respectively provided on the contact plugs CP1_d and CP2_d. Furthermore, electrode pads PD are provided on each wiring layer 111 .

1.5 Cross-sectional structure of semiconductor memory device Next, the cross-sectional structure of the semiconductor memory device 1 will be described.

1.5.1 Composition of A1-A2 section First, an example of the structure of the A1-A2 cross section of the semiconductor memory device 1 will be described with reference to FIG. 6 . Figure 6 is a cross-sectional view along line A1-A2 of Figures 4 and 5. In the following description, when the Z direction from the array chip 10 to the circuit chip 20 is limited, it is expressed as the Z1 direction. When the Z direction from the circuit chip 20 to the array chip 10 is limited, it is expressed as the Z2 direction.

As shown in FIG. 6 , the semiconductor memory device 1 has a structure in which array wafers 10_1 and 10_2 are bonded to a circuit chip 20 . The respective chips are electrically connected to each other through the electrode pads PD provided on the respective chips.

First, the internal structure of the array wafer 10_1 will be described.

The array chip 10_1 includes various wiring layers for connecting it to the memory cell array 11_1, the array chip 10_2 and the circuit chip 20.

The array wafer 10_1 includes insulating layers 101, 105, 107, 110, 112, and 114, wiring layers 102, 103, 104, and 111, and conductors 106, 108, 109, 113, and 115.

In the memory cell array 11_1, a plurality of insulation layers 101 and a plurality of wiring layers 102 are alternately stacked layer by layer. In the example of FIG. 6 , seven wiring layers 102 functioning as select gate lines SGS, word lines WL0 to WL4, and select gate lines SGD are sequentially stacked in the Z1 direction. Hereinafter, when limiting the wiring layer 102 that functions as word lines WL0, WL1, WL2, WL3, and WL4 respectively, they are described as wiring layers 102_w0, 102_w1, 102_w2, 102_w3, and 102_w4. When limiting the wiring layer 102 functioning as the select gate lines SGD and SGS respectively, they are expressed as wiring layers 102_d and 102_s.

For the insulating layer 101, for example, silicon oxide (SiO) containing silicon and oxygen is used. The wiring layer 102 contains conductive material. As the conductive material, for example, metal materials, n-type semiconductors, or p-type semiconductors are used. As the conductive material of the wiring layer 102, for example, a multilayer structure of titanium nitride (TiN)/tungsten (W) is used. In this case, TiN is formed to cover W. In addition, the wiring layer 102 may include a high dielectric constant material such as aluminum oxide (AlO) containing oxygen and aluminum. In this case, a high dielectric constant material is formed to cover the conductive material.

The plurality of wiring layers 102 are separated in each block BLK by gaps SLT extending in the X direction. The insulating layer 105 is embedded in the gap SLT. For the insulating layer 105, SiO, for example, is used.

In the Z2 direction, a wiring layer 103 is provided above the wiring layer 102_s. An insulating layer 101 is provided between the wiring layer 102 and the wiring layer 103 . The wiring layer 103 functions as the source line SL. In the Z2 direction, a wiring layer 104 is provided on the wiring layer 103 . The wiring layer 104 is used as a wiring layer for electrically connecting the wiring layer 103 and the circuit chip 20 . Wiring layers 103 and 104 include conductive materials. As the conductive material, for example, a metal material, an n-type semiconductor, or a p-type semiconductor is used.

In the Z1 direction, contact plugs CP1 are provided on each wiring layer 102 . Contact plug CP1 has, for example, a cylindrical shape. Contact plug CP1 includes a conductor 106 and an insulating layer 107 . The electrical conductor 106 has, for example, a cylindrical shape. One end of the conductor 106 is in contact with the wiring layer 102 . The insulating layer 107 is provided to cover the side surface (outer periphery) of the conductor 106 . The insulating layer 107 has, for example, a cylindrical shape. Due to the insulating layer 107, the side surface of the conductor 106 is not electrically connected to the wiring layer 102. For the conductor 106, a metal material including Cu (copper), Al (aluminum), or the like is used, for example. For the insulating layer 107, SiO, for example, is used.

In the example of FIG. 6 , contact plug CP1_w4 is provided. Contact plug CP1_w4 penetrates wiring layer 102_d. Moreover, the contact plug CP1_w4 is electrically connected to the wiring layer 102_w4.

Contact plugs CP2 penetrating the plurality of wiring layers 102 are provided. Contact plug CP2 has, for example, a cylindrical shape. Contact plug CP2 includes a conductor 109 and an insulating layer 110 . The conductor 109 has, for example, a cylindrical shape. The insulating layer 110 is provided to cover the side surface (outer periphery) of the conductor 109 . The insulating layer 110 has, for example, a cylindrical shape. Due to the insulating layer 110, the conductor 109 is not electrically connected to the wiring layer 102.

In the CP2 area where the contact plug CP2 is provided, the wiring layer 103 and the wiring layer 104 are not provided. Moreover, the conductor 108 is provided above the wiring layer 102_s in the Z2 direction. An insulating layer 101 is provided between the wiring layer 102 and the conductor 108 . The conductor 108 is connected to one end of the contact plug CP2.

In the Z1 direction, a wiring layer 111 is provided above the wiring layer 102_d. The wiring layer 111 extends in the Y direction. An insulating layer 101 is provided between the wiring layer 102 and the wiring layer 111 . The wiring layer 111 contains conductive material. As the conductive material, for example, a metal material containing Cu, Al, or the like is used.

The wiring layer 111 is connected to the other end of the contact plug CP1 and the other end of the contact plug CP2 provided in the adjacent block BLK in the Y direction. The contact plugs CP1 and CP2 connected to the wiring layer 111 are arranged in an array along the Y direction. In the example of FIG. 6 , the contact plug CP1_w4 of the block BLK0 and the contact plug CP2_w4 of the block BLK1 are connected to the wiring layer 111 arranged to span the blocks BLK0 and BLK1. Furthermore, the contact plug CP1_w4 of the block BLK2 and the contact plug CP2_w4 of the block BLK3 are connected to the wiring layer 111 disposed across the blocks BLK2 and BLK3.

In the Z1 direction, an insulating layer 112 is provided on the wiring layer 111 and the insulating layer 101 . For the insulating layer 112, SiO, for example, is used.

A plurality of conductors 113 are provided in the insulating layer 112 . The conductor 113 functions as an electrode pad PD. For example, one conductor 113 is provided on one wiring layer 111 . For the conductor 113, a metal material including Cu, for example, is used.

In the Z2 direction, an insulating layer 114 is provided on the wiring layer 104, the insulating layer 101, and the conductor 108. For the insulating layer 114, SiO, for example, is used.

A plurality of conductors 115 are provided in the insulating layer 114 . The conductor 115 functions as an electrode pad PD. For example, one conductor 115 is provided on one conductor 108 . For the conductor 115, a metal material including Cu, for example, is used.

Next, the internal structure of the array wafer 10_2 will be described. The following description will focus on the differences from the array wafer 10_1.

In the array chip 10_2, the contact plug CP2, the conductor 108, the insulating layer 114, and the conductor 115 are omitted from the description of the structure of the array chip 10_1. Other configurations are the same as the array wafer 10_1. The conductor 113 of the array chip 10_2 is connected to the conductor 115 of the array chip 10_1.

For example, the wiring layer 102 of the array chip 10_2 passes through the contact plug CP1 of the array chip 10_2, the wiring layer 111 of the array chip 10_2, the conductor 113 of the array chip 10_2, the conductor 115 of the array chip 10_1, and the conductor 108 of the array chip 10_1. , the contact plug CP2 of the array chip 10_1, the wiring layer 111 of the array chip 10_1, and the contact plug CP1 of the array chip 10_1 are electrically connected to the wiring layer 102 of the array chip 10_1.

In the example of FIG. 6 , the wiring layer 102_w4 of the block BLK0 of the array chip 10_2 is electrically connected to the wiring layer 102_w4 of the block BLK0 of the array chip 10_1. In other words, the word line WL4 of the memory cell array 11_2 is electrically connected to the word line WL4 of the memory cell array 11_1 arranged above in the Z1 direction. At this time, the contact plug CP1_w4 of the memory cell array 11_2 is electrically connected to the contact plug CP1_w4 of the memory cell array 11_1 arranged above in the Z1 direction. The same applies to other word lines WL. In addition, contact plugs CP2 and conductors 108 may also be provided in the memory cell array 11_2.

Next, the circuit chip 20 will be described.

The circuit chip 20 includes a plurality of transistors Tr and various wiring layers. A plurality of transistors Tr are used in the sequencer 21, the voltage generation circuit 22, the column driver 23, the column decoder 24, the sense amplifier 25, and the like.

More specifically, the circuit chip 20 includes a semiconductor substrate 200, insulating layers 201, 202, and 209, a gate electrode 203, conductors 204, 206, 208, and 210, and wiring layers 205 and 207.

An element isolation region is provided near the surface of the semiconductor substrate 200 . The device isolation region electrically separates, for example, an n-type well region and a p-type well region provided near the surface of the semiconductor substrate 200 . The element isolation area is embedded with an insulating layer 201 . For the insulating layer 201, SiO, for example, is used.

An insulating layer 202 is provided on the semiconductor substrate 200 . For the insulating layer 202, SiO, for example, is used.

The transistor Tr includes a gate insulating film (not shown) provided on the semiconductor substrate 200 , a gate electrode 203 provided on the gate insulating film, and a source and a drain (not shown) formed on the semiconductor substrate 200 . The source electrode and the drain electrode are respectively electrically connected to the wiring layer 205 via the conductor 204 . The conductor 204 extends in the Z2 direction. The electrical conductor 204 functions as a contact plug. A conductor 206 is provided on the wiring layer 205 . The conductor 206 extends in the Z2 direction. The electrical conductor 206 functions as a contact plug. A wiring layer 207 is provided on the conductor 206 . A conductor 208 is provided on the wiring layer 207 . The conductor 208 extends in the Z2 direction. In addition, the number of wiring layers provided on the circuit chip 20 is arbitrary. The electrical conductor 208 functions as a contact plug. The wiring layers 205 and 207 are made of conductive material. For the conductors 204, 206, and 208 and the wiring layers 205 and 207, for example, a metal material, a p-type semiconductor, or an n-type semiconductor is used.

In the Z2 direction, an insulating layer 209 is provided on the insulating layer 202 . For the insulating layer 209, SiO, for example, is used.

A plurality of conductors 210 are provided in the insulating layer 209 . The conductor 210 functions as an electrode pad PD. For example, one conductor 210 is provided on one conductor 208 . For the conductor 210, a metal material including Cu, for example, is used. The conductor 210 of the circuit chip 20 is connected to the conductor 113 of the array chip 10_1.

1.5.2 Composition of B1-B2 section Next, an example of the structure of the B1-B2 cross section of the semiconductor memory device 1 will be described with reference to FIG. 7 . Figure 7 is a cross-sectional view along line B1-B2 of Figures 4 and 5. Hereinafter, description will be given focusing on the structure of contact plug CP1.

As shown in FIG. 7 , contact plugs CP1_s, CP1_w0˜CP1_w4, and CP1_d are respectively provided on the array chips 10_1 and 10_2. In the example of FIG. 7 , contact plugs CP1_s, CP1_w0 to CP1_w4, and CP1_d are arranged in order from the right side to the left side of the paper. One ends of the contact plugs CP1_s, CP1_w0 to CP1_w4, and CP1_d are respectively connected to the wiring layers 102_s, 102_w0 to 102_w4, and 102_d. In addition, the other ends of the contact plugs CP1_s, CP1_w0 to CP1_w4, and CP1_d are respectively connected to different wiring layers 111. Therefore, the lengths of the contact plugs CP1_s, CP1_w0 to CP1_w4, and CP1_d in the Z direction are different.

More specifically, the contact plug CP1_s penetrates the six wiring layers 102_w0 to 102_w4 and 102_d. The contact plug CP1_s is not electrically connected to the six wiring layers 102_w0 to 102_w4 and 102_d. Moreover, one end of the contact plug CP1_s is electrically connected to the wiring layer 102_s.

Contact plug CP1_w0 penetrates five wiring layers 102_w1 to 102_w4 and 102_d. Contact plug CP1_w0 is not electrically connected to 5-layer wiring layers 102_w1 to 102_w4 and 102_d. Moreover, one end of the contact plug CP1_w0 is electrically connected to the wiring layer 102_w0.

Contact plug CP1_w1 penetrates four wiring layers 102_w2 to 102_w4 and 102_d. Contact plug CP1_w1 is not electrically connected to the four wiring layers 102_w2 to 102_w4 and 102_d. Moreover, one end of the contact plug CP1_w1 is electrically connected to the wiring layer 102_w1.

Contact plug CP1_w2 penetrates three wiring layers 102_w3, 102_w4, and 102_d. Contact plug CP1_w2 is not electrically connected to the three wiring layers 102_w3, 102_w4, and 102_d. Moreover, one end of the contact plug CP1_w2 is electrically connected to the wiring layer 102_w2.

Contact plug CP1_w3 penetrates the two wiring layers 102_w4 and 102_d. Contact plug CP1_w3 is not electrically connected to the two-layer wiring layers 102_w4 and 102_d. Moreover, one end of the contact plug CP1_w3 is electrically connected to the wiring layer 102_w3.

Contact plug CP1_w4 penetrates wiring layer 102_d. The contact plug CP1_w4 is not electrically connected to the wiring layer 102_d. Moreover, one end of the contact plug CP1_w4 is electrically connected to the wiring layer 102_w4.

One end of the contact plug CP1_d is electrically connected to the wiring layer 102_d.

1.5.3 Composition of C1-C2 section Next, an example of the structure of the C1-C2 cross section of the semiconductor memory device 1 will be described with reference to FIG. 8 . Figure 8 is a cross-sectional view along line C1-C2 of Figures 4 and 5. Hereinafter, description will be given focusing on the structure of contact plug CP2.

As shown in FIG. 8 , contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d are provided on the array chip 10_1. In the example of FIG. 8 , contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d are arranged in order from the right side to the left side of the paper. Contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d have substantially the same shape (same length). Contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d penetrate the seven wiring layers 102_s, 102_w0 to 102_w4, and 102_d. Contact plugs CP2_s, CP2_w0~CP2_w4, and CP2_d are not electrically connected to the 7-layer wiring layers 102_s, 102_w0~102_w4, and 102_d. One ends of the contact plugs CP2_s, CP2_w0~CP2_w4, and CP2_d are respectively connected to different conductors 108. The other ends of the contact plugs CP2_s, CP2_w0~CP2_w4, and CP2_d are respectively connected to different wiring layers 111.

1.5.4 Composition of D1-D2 section Next, an example of the structure of the D1-D2 cross section of the semiconductor memory device 1 will be described with reference to FIG. 9 . Figure 9 is a cross-sectional view along line D1-D2 of Figures 4 and 5. In the following, description will be given focusing on the structure of the memory pillar MP and the bit line BL.

As shown in FIG. 9 , memory conductive pillars MP are provided on the array chips 10_1 and 10_2.

The memory pillar MP penetrates a plurality of wiring layers 102 . The memory guide pillar MP extends in the Z direction. One end of the memory conductor MP is connected to the wiring layer 103 . In the Z1 direction, a conductor 126 is provided on the other end of the memory conductive pillar MP. Electric conductor 126 functions as contact plug CP3. The conductor 127 is provided on the conductor 126 . The electrical conductor 127 functions as the contact plug CP4. In the Z1 direction, a plurality of wiring layers 128 are provided above the memory conductive pillars MP. A plurality of wiring layers 128 are arranged in the X direction. The wiring layer 128 extends in the Y direction. The wiring layer 128 functions as the bit line BL. The wiring layer 128 is connected to any memory conductor MP through the contact plugs CP3 and CP4.

In the array chip 10_1, one end of the wiring layer 128 is connected to the conductor 115 via the conductor 130. Furthermore, one end of the wiring layer 128 is connected to the conductor 113 via the conductor 131 . The conductors 130 and 131 extend in the Y direction. Electric conductors 130 and 131 function as contact plugs CP5 and CP6.

In the array chip 10_2, one end of the wiring layer 128 is connected to the conductor 113 via the conductor 131. Therefore, the wiring layer 128 of the memory cell array 11_2 is electrically connected to the wiring layer 128 of the memory cell array 11_1 arranged above in the Z1 direction. In other words, the memory conductive posts MP of the memory cell array 11_2 are electrically connected to the memory conductive posts MP of the memory cell array 11_1 arranged above in the Z1 direction.

For the conductors 126, 127, 130, and 131 and the wiring layer 128, a metal material such as W, Al, or Cu is used.

Next, the internal structure of the memory pillar MP will be described.

The memory pillar MP includes a barrier insulating film 120, a charge accumulation layer 121, a tunnel insulating film 122, a semiconductor layer 123, a core layer 124, and a capping layer 125.

More specifically, holes MH penetrating the plurality of wiring layers 102 are provided. The hole MH corresponds to the memory conductor MP. The end of the hole MH in the Z2 direction reaches the wiring layer 103 . On the side of the hole MH, a barrier insulating film 120, a charge storage layer 121, and a tunnel insulating film 122 are laminated sequentially from the outside. For example, when the hole MH has a cylindrical shape, the barrier insulating film 120, the charge storage layer 121, and the tunnel insulating film 122 each have a cylindrical shape. The semiconductor layer 123 is provided in contact with the side surface of the tunnel insulating film 122 . The end of the semiconductor layer 123 in the Z2 direction is in contact with the wiring layer 103 . The semiconductor layer 123 is a region forming channels of the memory cell transistor MC and the selection transistors ST1 and ST2. Therefore, the semiconductor layer 123 functions as a signal line connecting the current paths of the selection transistor ST2, the memory cell transistors MC0 to MC4, and the selection transistor ST1. The interior of the semiconductor layer 123 is embedded by the core layer 124 . On the ends of the semiconductor layer 123 and the core layer 124 in the Z1 direction, a capping layer 125 is provided whose sides are in contact with the tunnel insulating film 122 . That is, the memory pillar MP includes the semiconductor layer 123 that passes through the interior of the plurality of wiring layers 102 and extends in the Z direction. In addition, the cover layer 125 can also be removed.

For the barrier insulating film 120, the tunnel insulating film 122, and the core layer 124, SiO, for example, is used. For the charge accumulation layer 121, silicon nitride (SiN), for example, is used. For the semiconductor layer 123 and the capping layer 125, for example, polycrystalline silicon is used.

Memory cell transistors MC0 ~ MC4 are respectively formed by combining the memory conductive pillars MP and the wiring layers 102_w0 ~ 102_w4 respectively. Similarly, the selection transistor ST1 is formed by combining the memory conductor MP and the wiring layer 102_d. The selection transistor ST2 is formed by combining the memory conductive pillar MP and the wiring layer 102_s.

1.6 Effects of this embodiment According to the structure of this embodiment, it is possible to provide a semiconductor memory device that can suppress an increase in the chip area. Describe this effect in detail.

For example, in order to highly integrate a semiconductor memory device, a method of stacking a plurality of array wafers is known. If the word lines WL of each array chip are respectively connected to the circuit chip, the number of word lines WL connected to the column decoder increases. Therefore, the circuit scale of the column decoder becomes larger corresponding to the number of array chips. In other words, the area of the circuit chip increases.

On the other hand, according to the structure of this embodiment, word lines WL can be commonly connected in a plurality of array chips. Therefore, even if the number of array chips, that is, the number of word lines WL stacked increases, the number of word lines WL connected to the column decoder can be suppressed from increasing. Thereby, the area of the circuit chip can be suppressed from increasing.

Furthermore, according to the structure of this embodiment, the bit lines BL can be commonly connected to a plurality of array chips. Therefore, even if the number of array chips increases, the number of bit lines BL connected to the sense amplifiers can be suppressed from increasing. Thereby, the area of the circuit chip can be suppressed from increasing.

Furthermore, according to the structure of this embodiment, the selected gate lines SGD can be independently controlled in a plurality of array chips. Therefore, different string units SU of a plurality of array chips can be controlled independently.

2. Second embodiment Next, the second embodiment will be described. In the second embodiment, the connection of the bit line BL and the select gate line SGD, which is different from the first embodiment, will be described. The following description will focus on differences from the first embodiment.

2.1 Overall composition of semiconductor memory device First, an example of the overall structure of the semiconductor memory device 1 will be described with reference to FIG. 10 . FIG. 10 is an example of a block diagram showing the overall structure of the semiconductor memory device 1. In addition, in FIG. 10 , a part of the connection between each block is represented by an arrow line, but the connection between blocks is not limited to this.

As shown in FIG. 10 , the circuit chip 20 includes a sequencer 21 , a voltage generation circuit 22 , a column driver 23 , a column decoder 24 , a sense amplifier 25 , and a BL selection circuit 26 .

The structure of the sequencer 21, the voltage generation circuit 22, the column driver 23, and the sense amplifier 25 is the same as that of the first embodiment.

In this embodiment, the word lines WL and the select gate lines SGD and SGS of the memory cell arrays 11_1 and 11_2 are commonly connected to the column decoder 24 . That is, the memory cell arrays 11_1 and 11_2 share the word line WL and the select gate lines SGD and SGS.

The BL selection circuit 26 is a circuit that selects either the memory cell array 11_1 or the memory cell array 11_2. Hereinafter, the bit line BL connecting the BL selection circuit 26 and the memory cell array 11_1 will be described as the bit line BL_1. The bit line BL connecting the BL selection circuit 26 and the memory cell array 11_2 is expressed as a bit line BL_2.

The BL selection circuit 26 is connected to the sense amplifier 25 via a plurality of bit lines BL. The BL selection circuit 26 is connected to the memory cell array 11_1 via a plurality of bit lines BL_1. The BL selection circuit 26 is connected to the memory cell array 11_2 via a plurality of bit lines BL_2. The BL selection circuit 26 is electrically connected to the bit line BL and any one of the bit lines BL_1 and BL_2. In other words, the BL selection circuit 26 is electrically connected to the sense amplifier 25 and any one of the memory cell arrays 11_1 and 11_2. In addition, the bit line BL_1 and the bit line BL_2 are not electrically connected.

2.2 Circuit structure of memory cell array and BL selection circuit Next, an example of the circuit configuration of the memory cell arrays 11_1 and 11_2 and the BL selection circuit 26 will be described with reference to FIG. 11 .

As shown in FIG. 11 , the circuit configuration of memory cell arrays 11_1 and 11_2 is the same as that in FIG. 2 of the first embodiment.

Similar to FIG. 2 , memory cell arrays 11_1 and 11_2 are commonly connected to one word line WL. In addition, memory cell arrays 11_1 and 11_2 are commonly connected to one selection gate line SGS.

In this embodiment, the gates of the plurality of selection transistors ST1 of the string unit SU0 of the block BLK0_1 of the memory cell array 11_1 and the string unit SU0 of the block BLK0_2 of the memory cell array 11_2 are commonly connected to the selection gate line SGD0. . The gates of the plurality of selection transistors ST1 of the string unit SU1 of the block BLK0_1 of the memory cell array 11_1 and the string unit SU1 of the block BLK0_2 of the memory cell array 11_2 are commonly connected to the selection gate line SGD1. The gates of the plurality of selection transistors ST1 of the string unit SU2 of the block BLK0_1 of the memory cell array 11_1 and the string unit SU2 of the block BLK0_2 of the memory cell array 11_2 are commonly connected to the selection gate line SGD2. That is, the memory cell arrays 11_1 and 11_2 are commonly connected to one select gate line SGD. The same goes for blocks BLK1_1 and BLK1_2, and blocks BLK2_1 and BLK2_2.

In the example of FIG. 11 , the drains of the n+1 selection transistors ST1 in the string unit SU of the memory cell array 11_1 are respectively connected to the n+1 bit lines BL0_1˜BLn_1. In addition, the drains of the n+1 selection transistors ST1 in the string unit SU of the memory cell array 11_2 are respectively connected to the n+1 bit lines BL0_2˜BLn_2.

The BL selection circuit 26 includes a plurality of selectors SEL. One selector SEL is provided for each bit line BL. Bit lines BL, BL_1, and BL_2 are connected to the selector SEL. The selector SEL is electrically connected to any one of the bit line BL, the bit line BL_1 and the bit line BL_2 based on the control signals BS1 and BS2. In other words, the selector SEL is electrically connected to any one of the sense amplifier 25 and the memory cell arrays 11_1 and 11_2 based on the control signals BS1 and BS2. Control signals BS1 and BS2 are supplied from, for example, the sequencer 21.

The internal structure of the selector SEL is explained. In the following description, either the source or the drain of the transistor is expressed as one end of the transistor. Also, the other one of the source or drain of the transistor is expressed as the other end of the transistor.

Selector SEL includes transistors T1 and T2. One end of the transistor T1 and one end of the transistor T2 are commonly connected to the bit line BL. The other end of the transistor T1 is connected to the bit line BL_1. The control signal BS1 is input to the gate of the transistor T1. The other end of the transistor T2 is connected to the bit line BL_2. The control signal BS2 is input to the gate of the transistor T2. For example, when the control signal BS1 is at a high ("H") level, the transistor T1 is set to a conductive state. Furthermore, for example, when the control signal BS2 is at the "H" level, the transistor T2 is set to a conductive state.

More specifically, in the case of the selector SEL corresponding to the bit line BL0, for example, one end of the transistor T1 and one end of the transistor T2 are connected to the bit line BL0. The other end of the transistor T1 is connected to the bit line BL0_1. The other end of the transistor T2 is connected to the bit line BL0_2. The same applies to the selectors SEL corresponding to the other bit lines BL1 to BLn. In this state, for example, when the control signal BS1 is at the "H" level and the control signal BS2 is at the low (Low) ("L") level, the bit lines BL0 to BLn are electrically connected respectively through the selector SEL. Connected to bit lines BL0_1~BLn_1. Furthermore, for example, when the control signal BS1 is at the "L" level and the control signal BS2 is at the "H" level, the bit lines BL0 - BLn are electrically connected to the bit lines BL0_2 - BLn_2 respectively through the selector SEL.

2.3 Connection of various wirings between chips Next, the connection of various wirings between chips will be described with reference to FIG. 12 . FIG. 12 is a conceptual diagram showing the configuration of the memory cell arrays 11_1 and 11_2 and the circuit chip 20.

As shown in FIG. 12 , the bit line BL_1 of the memory cell array 11_1 and the bit line BL_2 of the memory cell array 11_2 are respectively connected to the BL selection circuit 26 of the circuit chip 20 .

The word lines WL and the select gate lines SGD and SGS of the memory cell arrays 11_1 and 11_2 are commonly connected to the column decoder 24 of the circuit chip 20 .

2.4 Effects of this embodiment According to the structure of this embodiment, the same effect as that of the first embodiment is obtained.

Furthermore, according to the configuration of this embodiment, the semiconductor memory device 1 includes the BL selection circuit 26 . By using the BL selection circuit 26 to select the bit lines BL, that is, the array chips, even if the number of array chips increases, the number of bit lines BL connected to the sense amplifiers can be suppressed from increasing. Thereby, the area of the circuit chip can be suppressed from increasing.

Furthermore, according to the structure of this embodiment, the select gate line SGD can be shared among a plurality of array chips. Therefore, even if the number of array chips, that is, the number of string units SU, increases, the number of select gate lines SGD connected to the column decoder can be suppressed from increasing. Thereby, the area of the circuit chip can be suppressed from increasing.

3. Third embodiment Next, the third embodiment will be described. In the third embodiment, the connection of the bit line BL and the selection gate line SGD, which is different from the first and second embodiments, will be explained. The following description will focus on differences from the first and second embodiments.

3.1 Overall composition of semiconductor memory device First, an example of the overall structure of the semiconductor memory device 1 will be described with reference to FIG. 13 . FIG. 13 is an example of a block diagram showing the overall structure of the semiconductor memory device 1. In addition, in FIG. 13 , although a part of the connection between each block is shown by an arrow line, the connection between the blocks is not limited to this.

As shown in FIG. 13 , similar to FIG. 2 of the first embodiment, the word lines WL and the select gate lines SGS of the memory cell arrays 11_1 and 11_2 are commonly connected to the column decoder 24 . In other words, the word line WL and the selection gate line SGS of the memory cell arrays 11_1 and 11_2 share the word line WL and the selection gate line SGS. Moreover, the selection gate line SGD of the memory cell array 11_1 and the selection gate line SGD of the memory cell array 11_2 are respectively independent and connected to the column decoder 24 .

Moreover, similarly to FIG. 10 of the second embodiment, the circuit chip 20 is provided with a BL selection circuit 26 . The BL selection circuit 26 is electrically connected to the sense amplifier 25 and any one of the memory cell arrays 11_1 and 11_2.

3.2 Circuit structure of memory cell array and BL selection circuit Next, referring to FIG. 14 , an example of the circuit configuration of the memory cell arrays 11_1 and 11_2 and the BL selection circuit 26 will be described.

As shown in FIG. 14 , similarly to FIG. 2 of the first embodiment, the gates of a plurality of selection transistors ST1 in the string unit SU are commonly connected to one selection gate line SGD. More specifically, the gates of the plurality of selection transistors ST1 in the string unit SU0 of the memory cell array 11_1 are commonly connected to the selection gate line SGD0_1. The same applies to other string units SU.

The configurations of the bit lines BL, BL_1, and BL_2 and the BL selection circuit 26 are the same as those of the second embodiment shown in FIG. 11 .

3.3 Connection of various wirings between chips Next, the connection of various wirings between chips will be described with reference to FIG. 15 . FIG. 15 is a conceptual diagram showing the configuration of the memory cell arrays 11_1 and 11_2 and the circuit chip 20.

As shown in FIG. 15 , the bit line BL_1 of the memory cell array 11_1 and the bit line BL_2 of the memory cell array 11_2 are respectively connected to the BL selection circuit 26 of the circuit chip 20 .

The word lines WL and the select gate lines SGS of the memory cell arrays 11_1 and 11_2 are commonly connected to the column decoder 24 of the circuit chip 20 .

The select gate line SGD of the memory cell array 11_1 is connected to the column decoder 24 of the circuit chip 20 . The select gate line SGD of the memory cell array 11_2 is connected to the column decoder 24 of the circuit chip 20 . The select gate line SGD of the memory cell array 11_1 and the select gate line SGD of the memory cell array 11_2 are not electrically connected.

3.4 Effects of this implementation form According to the structure of this embodiment, the same effects as those of the first and second embodiments are obtained.

4. Fourth embodiment Next, the fourth embodiment will be described. In the fourth embodiment, an example of the layout of four bit lines BL will be described. The following description will focus on differences from the first to third embodiments. In addition, in the following description, in order to simplify the explanation, when expressed as a bit line BL, the bit line BL includes the wiring layer 128 and various wiring layers connecting the wiring layer 128 and the sense amplifier 25 or the BL selection circuit 26 , contact plugs, and electrode pads, etc.

4.1 Example 1 First, the first example will be described with reference to FIGS. 16 and 17 . In the first example, the layout of the bit lines BL applicable to the second and third embodiments will be described. FIG. 16 is a conceptual diagram of the three-dimensional display circuit chip 20, the core part of the memory cell array 11_1, and the core part of the memory cell array 11_2. FIG. 17 is a conceptual diagram of the flat display circuit chip 20, the core part of the memory cell array 11_1, and the core part of the memory cell array 11_2. In the examples of FIG. 16 and FIG. 17 , except for the bit line BL and the BL selection circuit 26, they are omitted. In the following, in the memory cell arrays 11_1 and 11_2 and the circuit chip 20, one end in the Y direction is referred to as the end YL. The other end in the Y direction is expressed as end YR. The end portion YL and the end portion YR are opposite to each other in the Y direction.

As shown in FIG. 16 , the bit line BL_1 of the memory cell array 11_1 and the bit line BL_2 of the memory cell array 11_2 are not electrically connected. That is, the memory cell array 11_1 and the memory cell array 11_2 do not share the bit line BL. Each of the plurality of bit lines BL_1 of the memory cell array 11_1 is alternately led out to the end YL side and the end YR side. The same applies to the plurality of bit lines BL_2 of the memory cell array 11_2. In the circuit chip 20, BL selection circuits 26 are respectively arranged at both ends in the Y direction, that is, near the end YL and the end YR. Furthermore, the bit line BL_1 of the memory cell array 11_1 and the bit line BL_2 of the memory cell array 11_2 are connected to the selector SEL in the BL selection circuit 26 . Preferably, the selector SEL is disposed below the corresponding bit lines BL_1 and BL_2. Thereby, the lengths of the bit lines BL_1 can be made approximately equal. Similarly, the lengths of the bit lines BL_2 can be made approximately equal.

More specifically, as shown in FIG. 17 , for example, in the memory cell array 11_1, the even-numbered bit lines BL0_1, BL2_1, BL4_1, and BL6_1 are led out to the end YL side (left side of the paper) of the memory cell array 11_1. Also, for example, the odd-numbered bit lines BL1_1, BL3_1, BL5_1, and BL7_1 are led out to the end YR side (right side of the paper) of the memory cell array 11_1.

Similarly, in the memory cell array 11_2, the even-numbered bit lines BL0_2, BL2_2, BL4_2, and BL6_2 are led out to the end YL side of the memory cell array 11_2. Also, for example, the odd-numbered bit lines BL1_2, BL3_2, BL5_2, and BL7_2 are led out to the end YR of the memory cell array 11_2.

In the circuit chip 20 , the BL selection circuit 26 corresponding to the even-numbered bit line BL is arranged on the end YL side of the circuit chip 20 . Furthermore, the BL selection circuit 26 corresponding to the odd-numbered bit line BL is arranged on the end YR side of the circuit chip 20 .

The selector SEL connected to the bit line BL0 on the end YL side is connected to the bit lines BL0_1 and BL0_2. In the selector SEL connected to the bit line BL2, the bit lines BL2_1 and BL2_2 are connected. In the selector SEL connected to the bit line BL4, the bit lines BL4_1 and BL4_2 are connected. In the selector SEL connected to the bit line BL6, the bit lines BL6_1 and BL6_2 are connected.

The selector SEL connected to the bit line BL1 on the end YR side is connected to the bit lines BL1_1 and BL1_2. In the selector SEL connected to the bit line BL3, the bit lines BL3_1 and BL3_2 are connected. In the selector SEL connected to the bit line BL5, the bit lines BL5_1 and BL5_2 are connected. In the selector SEL connected to the bit line BL7, the bit lines BL7_1 and BL7_2 are connected.

In addition, in this example, although the case where each of the plurality of bit lines BL_1 is alternately led to the end YL side and the end YR side is described, the invention is not limited to this. For example, a plurality of bit lines BL_1 may be drawn out alternately every two or more. The same goes for bit line BL_2.

4.2 Case 2 Next, a second example will be described with reference to FIGS. 18 and 19 . In the second example, the layout of the bit lines BL applicable to the first embodiment will be described. FIG. 18 is a conceptual diagram of the three-dimensional display circuit chip 20, the core part of the memory cell array 11_1, and the core part of the memory cell array 11_2. FIG. 19 is a conceptual diagram of the flat display circuit chip 20, the core part of the memory cell array 11_1, and the core part of the memory cell array 11_2. In the examples of FIG. 18 and FIG. 19 , except for the bit line BL and the sense amplifier 25, they are omitted.

As shown in FIG. 18 , the memory cell array 11_1 and the memory cell array 11_2 share the bit line BL. That is, the bit line BL of the memory cell array 11_1 is electrically connected to the bit line BL of the memory cell array 11_2. In the memory cell arrays 11_1 and 11_2, the bit line BL is led out to the end YL side. Moreover, on the end YL side, the bit line BL of the memory cell array 11_2 is electrically connected to the bit line BL of the memory cell array 11_1.

In addition, in this example, although in the memory cell arrays 11_1 and 11_2, all the bit lines BL are drawn to the end YL side, it is not limited to this. For example, each bit line BL may be alternately led out to the ends YL side and YR side.

In the circuit chip 20 , a sense amplifier 25 is independently configured for each bit line BL. The configuration of each sense amplifier 25 of the circuit chip 20 can be designed arbitrarily. In addition, in order to minimize the wiring length of the bit line BL, the sense amplifier 25 is preferably arranged below the corresponding bit line BL in the Z direction. The bit lines BL arranged in the memory cell array 11_1 are connected to the corresponding sense amplifiers 25 . At this time, the wiring length of the bit line BL connecting the memory cell array 11_1 and the sense amplifier 25 can also be minimized. In the memory cell array 11_1, the sense amplifier and bit line BL can be arranged in the middle part of the memory cell array 11_1. 25 connection part.

More specifically, as shown in FIG. 19 , for example, in the memory cell arrays 11_1 and 11_2 , the bit lines BL0 to BL7 are respectively led to the end portion YL side. Furthermore, on the end YL side, the bit lines BL0 to BL7 of the memory cell array 11_1 and the bit lines BL0 to BL7 of the memory cell array 11_2 are respectively connected. In the circuit chip 20 , eight sense amplifiers 25 are arranged, for example, near the center of the circuit chip 20 . The eight sense amplifiers 25 respectively correspond to the bit lines BL0 to BL7. The eight sense amplifiers 25 are arranged below the corresponding bit lines BL in the Z direction. In the memory cell array 11_1, a connection part with the sense amplifier 25 is provided in the middle part of the bit line BL.

4.3 Example 3 Next, a third example will be described with reference to FIGS. 20 and 21 . In the third example, the layout of the bit line BL applicable to the second and third embodiments is explained. FIG. 20 is a conceptual diagram of the three-dimensional display circuit chip 20, the core part of the memory cell array 11_1, and the core part of the memory cell array 11_2. FIG. 21 is a conceptual diagram of the flat display circuit chip 20, the core part of the memory cell array 11_1, and the core part of the memory cell array 11_2. In the examples of FIG. 20 and FIG. 21 , except for the bit line BL and the BL selection circuit 26, they are omitted.

As shown in FIG. 20 , in the memory cell arrays 11_1 and 11_2 , each bit line BL is divided into two in the Y direction. Hereinafter, when limiting the case of the bit line BL led to the end portion YL side, it is expressed as bit line BLa. When limiting the bit line BL drawn to the end YR side, it is expressed as bit line BLb. Each string unit SU in the memory cell array 11 is connected to any one of the bit lines BLa and BLb. In addition, the combination of the connection between the bit lines BLa and BLb and the string unit SU can be designed arbitrarily. Memory cell arrays 11_1 and 11_2 share bit lines BLa and BLb.

In the circuit chip 20, a BL selection circuit 26 is arranged near the center in the Y direction. Bit lines BLa and BLb corresponding to one bit line BL are connected to one selector SEL. Therefore, the selector SEL in this example functions as a circuit for selecting the bit line BLa or the bit line BLb.

The bit lines BLa and BLb are led out toward the circuit chip 20 near the center of the memory cell array 11_1 in the Y direction. In order to make the wiring length of the bit line BLa and the bit line BLb the same, it is preferable to arrange the selector SEL below the corresponding bit lines BLa and BLb.

More specifically, as shown in FIG. 21 , in the memory cell arrays 11_1 and 11_2 , for example, the bit line BL0 is divided into the bit lines BLa0 and BLb0. Bit line BL1 is divided into bit lines BLa1 and BLb1. Bit line BL2 is divided into bit lines BLa2 and BLb2. Bit line BL3 is divided into bit lines BLa3 and BLb3. Bit line BL4 is divided into bit lines BLa4 and BLb4. Bit line BL5 is divided into bit lines BLa5 and BLb5. Bit line BL6 is divided into bit lines BLa6 and BLb6. Bit line BL7 is divided into bit lines BLa7 and BLb7.

The bit line BLa0 of the memory cell array 11_1 and the bit line BLa0 of the memory cell array 11_2 are connected on the end YL side. The same applies to the other bit lines BLa1 to BLa7.

The bit line BLb0 of the memory cell array 11_1 and the bit line BLb0 of the memory cell array 11_2 are connected on the end YR side. The same applies to other bit lines BLb1 to BLb7.

Let the length of the bit line BLa0 and the length of the bit line BLb0 of the memory cell array 11_1 be La_1 and Lb_1 respectively. Similarly, the length of the bit line BLa0 and the length of the bit line BLb of the memory cell array 11_2 are set to La_2 and Lb_2. In this example, the length La_1, the length La_2, the length Lb_1, and the length Lb_2 are approximately equal. Therefore, the length of bit line BLa0 is approximately equal to the length of bit line BLb0. The same goes for other bit lines BLa and BLb. That is, the lengths of the bit lines BLa0 to BLa7 and the bit lines BLb0 to BLb7 are substantially equal.

Near the center of the memory cell array 11_1 in the Y direction, the bit lines BLa0 to BLa7 and BLb0 to BLb7 are led out to the circuit chip 20 .

In the circuit chip 20, the BL selection circuit 26 is arranged near the center in the Y direction. Furthermore, for example, a plurality of selectors SEL are arranged in the X direction. The selector SEL is arranged below the corresponding bit lines BLa and BLb. The selector SEL is connected to the bit lines BLa and BLb derived from the memory cell array 11_1.

More specifically, the selector SEL connected to the bit line BL0 is connected to the bit lines BLa0 and BLb0. To the selector SEL connected to the bit line BL1, the bit lines BLa1 and BLb1 are connected. The selector SEL connected to the bit line BL2 is connected to the bit lines BLa2 and BLb2. To the selector SEL connected to the bit line BL3, the bit lines BLa3 and BLb3 are connected. To the selector SEL connected to the bit line BL4, the bit lines BLa4 and BLb4 are connected. To the selector SEL connected to the bit line BL5, the bit lines BLa5 and BLb5 are connected. To the selector SEL connected to the bit line BL6, the bit lines BLa6 and BLb6 are connected. To the selector SEL connected to the bit line BL7, the bit lines BLa7 and BLb7 are connected.

The overall lengths of the bit lines BLa0 to BLa7 and BLb0 to BLb7 from one end near the center of the memory cell array 11_2 to the other end connected to the selector SEL are approximately equal.

4.4 Case 4 Next, the fourth example will be described with reference to FIGS. 22 and 23 . In the fourth example, the layout of the bit line BL applicable to the second and third embodiments is explained. FIG. 22 is a conceptual diagram of the three-dimensional display circuit chip 20, the core part of the memory cell array 11_1, and the core part of the memory cell array 11_2. FIG. 23 is a conceptual diagram of the flat display circuit chip 20, the core part of the memory cell array 11_1, and the core part of the memory cell array 11_2. In the examples of FIG. 22 and FIG. 23 , except for the bit line BL and the BL selection circuit 26, they are omitted.

As shown in FIG. 22 , similar to the third example, in the memory cell arrays 11_1 and 11_2 , each bit line BL is divided into two bit lines BLa and BLb in the Y direction.

In the circuit chip 20, a BL selection circuit 26, that is, a selector SEL, is independently configured for each bit line BL. In addition, the configuration of the selector SEL of the circuit chip 20 can be designed arbitrarily. Preferably, the selector SEL is disposed below the corresponding bit lines BLa and BLb. The selector SEL is respectively connected to the ends of the bit lines BLa and BLb drawn from the memory cell array 11_1.

In this example, the division positions of the bit lines BLa and BLb in the memory cell array 11 are different for each bit line BL. In other words, in one memory cell array, the lengths of the plurality of bit lines BLa are different respectively. Similarly, in one memory cell array, the lengths of the plurality of bit lines BLb are respectively different. Among them, the division positions of the memory cell arrays 11_1 and 11_2 are determined in such a way that the overall lengths of the bit lines BLa and BLb become the same. In other words, the lengths of the bit lines BLa and BLb from one end of the memory cell array 11_2 to the other end connected to the selector SEL are approximately equal. Therefore, based on the configuration of the selector SEL, the dividing position of the bit line BLa and the bit line BLb is determined.

More specifically, as shown in FIG. 23 , for example, the length of the bit line BLa0 and the length of the bit line BLb0 of the memory cell array 11_1 are set to La0_1 and Lb0_1 respectively. Similarly, the lengths of the bit lines BLa1 to BLa3 and the lengths of the bit lines BLb1 to BLb3 of the memory cell array 11_1 are respectively set to La1_1 to La3_1 and Lb1_1 to Lb3_1. In addition, the lengths of the bit lines BLa0 to BLa3 and the lengths of the bit lines BLb0 to BLb3 of the memory cell array 11_2 are respectively set to Lba0_2 to La3_2, Lb0_2 and Lb3_2.

For example, the lengths La0_1 to La3_1 are respectively different. The lengths La0_2 to La3_2 are respectively different. The lengths Lb0_1 to Lb3_1 are respectively different. The lengths Lb0_2 to Lb3_2 are different respectively. Even in the case of this relationship, length (La0_1+La0_2), length (La1_1+La1_2), length (La2_1+La2_2), length (La3_1+La3_2), length (Lb0_1+Lb0_2), length (Lb1_1+Lb1_2) , length (Lb2_1+Lb2_2), and length (Lb3_1+Lb3_2) are approximately equal.

4.5 Effects of this implementation form The structure of this embodiment can be applied to the first to third embodiments.

According to the structure of this embodiment, the wiring lengths of the bit lines BL can be made substantially equal. Therefore, the uneven wiring resistance of the bit line BL can be reduced.

Furthermore, according to the structures of the second and fourth examples, the sense amplifier 25 or the BL selection circuit 26 can be arranged at any position. Therefore, the layout of other circuits including the column decoder 24 can be easily optimized in the circuit chip 20 .

5. Examples of changes, etc. The semiconductor memory device of the above embodiment includes a first memory cell array (11_1) and a second memory cell array (11_2) arranged above the first memory cell array in the first direction (Z direction). The first memory cell array includes: a first semiconductor (123) extending in the first direction and connecting the first memory cell (MC) and the first selection transistor (ST1); a first word line (WL) connecting the gate of the first memory cell; the first selection gate line (SGD), which is connected to the gate of the first selection transistor; and the first bit line (BL), which is connected to the first semiconductor. The second memory cell array includes: a second semiconductor (123) extending in the first direction and connecting the second memory cell (MC) and the second selection transistor (ST1); a second word line (WL) connecting the gate of the second memory cell; the second selection gate line (SGD), which is connected to the gate of the second selection transistor; and the second bit line (BL), which is connected to the second semiconductor. The first character line and the second character line are electrically connected. The first selection gate line and the second selection gate line are not electrically connected.

It is possible to provide a semiconductor memory device in which processing capability can be improved by applying the above-mentioned embodiment.

In addition, the embodiment is not limited to the above-described form, and various modifications are possible.

For example, the above embodiments may be combined as much as possible.

For example, in the above-mentioned embodiment, the case where the circuit chip 20 and the two array wafers 10_1 and 10_2 are bonded together has been described, but these structures may also be formed on one semiconductor substrate.

For example, in the first example, the third example, and the fourth example of the second embodiment, the third embodiment, and the fourth embodiment, the BL selection circuit may be omitted. In this case, the bit lines BL provided in the memory cell arrays 11_1 and 11_2 are connected to the sense amplifier 25 .

For example, in the above embodiment, the plurality of wiring layers 102 may also be led out in a stepped manner from the plug connection part. In this case, the contact plug CP1 is connected to the stepped portion of the wiring layer 102 .

Furthermore, “substantially equal” in the above-mentioned embodiments may include errors due to manufacturing unevenness, for example.

Furthermore, the "connection" in the above embodiment may also include a state of indirect connection through other components such as transistors or resistors.

The embodiments are examples, and the scope of the invention is not limited to these. [Related applications]

This application enjoys the priority of the application based on Japanese Patent Application No. 2021-99966 (filing date: June 16, 2021). This application incorporates the entire contents of the basic application by reference to the basic application.

1: Semiconductor memory device 10_1:Array chip 10_2:Array chip 11_1: Memory cell array 11_2: Memory cell array 20:Circuit chip 21: Sequencer 22: Voltage generation circuit 23: Column driver 24: Column decoder 25: Sense amplifier 26:BL selection circuit 101:Insulation layer 102: Wiring layer 102_d: Wiring layer 102_s: Wiring layer 102_w0～102_w4: Wiring layer 103: Wiring layer 104: Wiring layer 105:Insulation layer 106: Electrical conductor 107:Insulation layer 108: Electrical conductor 109: Electrical conductor 110: Insulation layer 111: Wiring layer 112:Insulation layer 113: Electrical conductor 114:Insulation layer 115: Electrical conductor 120: Barrier insulation film 121: Charge accumulation layer 122: Tunnel insulation film 123: Semiconductor layer 124:Core layer 125:Cover 126: Electrical conductor 127: Electrical conductor 128:Wiring layer 130: Electrical conductor 131: Electrical conductor 200:Semiconductor substrate 201:Insulation layer 202:Insulation layer 203: Gate electrode 204: Electrical conductor 205: Wiring layer 206: Electrical conductor 207:Wiring layer 208: Electrical conductor 209:Insulation layer 210: Electrical conductor BL: bit line BL_1: bit line BL_2: bit line BL0～BLn: bit lines BL0_1～BLn_1: bit lines BL0_2～BLn_2: bit lines BLa: bit line BLa0～BLa7: bit lines BLb: bit line BLb0～BLb7: bit lines BLK0～BLK3: block BLK0_1～BLK2_1: block BLK0_2～BLK2_2: block BS1: control signal BS2: Control signal CP1～CP6: Contact plug CP1_d: Contact plug CP1_s: Contact plug CP1_w0～CP1_w4: Contact plug CP2_d: Contact plug CP2_s: Contact plug CP2_w0～CP2_w4: Contact plug CU: cell unit La_1:Length La_2:Length La0_1～La3_1: length La0_2～La3_2: length Lb_1: length Lb_2:Length Lb0_1～Lb3_1: length Lb0_2～Lb3_2: length MC: memory cell transistor MC0～MC4: memory cell transistor MH:hole MP: memory guide pillar NS:NAND string PD: electrode pad SEL: selector SGD: select gate line SGD0～SGD2: select gate line SGD0_1～SGD2_1: Select gate line SGD0_2～SGD2_2: Select gate line SGS: select gate line SL: source line SLT: gap ST1: Select transistor ST2: Select transistor SU0~SU3: string unit T1: transistor T2: transistor Tr: transistor WL: word line WL0～WL4: character lines YL: end YR:end

FIG. 1 is a block diagram showing the semiconductor memory device of the first embodiment. FIG. 2 is a circuit diagram of the memory cell array of the first embodiment. FIG. 3 is a conceptual diagram showing the arrangement of the memory cell array and the circuit chip in the first embodiment. FIG. 4 is a top view of the memory cell array 11_2 of the first embodiment. FIG. 5 is a top view of the memory cell array 11_1 of the first embodiment. Figure 6 is a cross-sectional view along line A1-A2 of Figures 4 and 5. Figure 7 is a cross-sectional view along line B1-B2 of Figures 4 and 5. Figure 8 is a cross-sectional view along line C1-C2 of Figures 4 and 5. Figure 9 is a cross-sectional view along line D1-D2 of Figures 4 and 5. FIG. 10 is a block diagram showing the semiconductor memory device of the second embodiment. Figure 11 is a circuit diagram of the memory cell array of the second embodiment. FIG. 12 is a conceptual diagram showing the arrangement of the memory cell array and the circuit chip in the second embodiment. FIG. 13 is a block diagram showing the semiconductor memory device of the third embodiment. Figure 14 is a circuit diagram of the memory cell array and BL selection circuit of the third embodiment. FIG. 15 is a conceptual diagram showing the arrangement of the memory cell array and the circuit chip in the third embodiment. FIG. 16 is a conceptual diagram showing a core part of a circuit chip and a memory cell array in a first example of the fourth embodiment in a three-dimensional manner. FIG. 17 is a conceptual diagram showing a plan view of the circuit chip and the core portion of the memory cell array of the first example of the fourth embodiment. FIG. 18 is a conceptual diagram showing a core part of a circuit chip and a memory cell array in a second example of the fourth embodiment in a three-dimensional manner. FIG. 19 is a conceptual diagram showing a plan view of the circuit chip and the core portion of the memory cell array of the second example of the fourth embodiment. FIG. 20 is a conceptual diagram showing a plan view of the circuit chip and the core portion of the memory cell array of the third example of the fourth embodiment. FIG. 21 is a conceptual diagram showing a plan view of the circuit chip and the core portion of the memory cell array of the third example of the fourth embodiment. FIG. 22 is a conceptual diagram showing a plan view of a circuit chip and a core portion of a memory cell array according to the fourth example of the fourth embodiment. FIG. 23 is a conceptual diagram showing a plan view of a circuit chip and a core portion of a memory cell array according to the fourth example of the fourth embodiment.

10_1:Array chip

10_2:Array chip

11_1: Memory cell array

11_2: Memory cell array

20:Circuit chip

24: Column decoder

25: Sense amplifier

BL: bit line

SGD: select gate line

SGS: select gate line

WL: word line

Claims (10)

A semiconductor device comprising: a first control circuit; a first memory cell array arranged on the first direction side of the first control circuit and controlled by the first control circuit; and a second memory cell array arranged on It is further to the first direction side than the above-mentioned first memory cell array and is controlled by the above-mentioned first control circuit; the above-mentioned first memory cell array includes: a first word cell line; a first memory conductor pillar, which penetrates the above-mentioned first word The bit line extends in the above-mentioned first direction; the first bit line is disposed on the first control circuit side of the above-mentioned first memory conductive pillar and is connected to the above-mentioned first memory conductive pillar along the above-mentioned first direction. The vertical direction is the second direction extending; the second memory cell array includes: a second word line; a second memory conductive pillar, which penetrates the second word line and extends in the first direction; a second bit cell Line, which is disposed on the side of the first memory cell array of the above-mentioned second memory conductive pillar, is connected to the above-mentioned second memory conductive pillar, and extends along the above-mentioned second direction; the above-mentioned first character line and the above-mentioned second character element Line electrical connection. The semiconductor device of claim 1 further includes: a first contact that is electrically connected to the second word line and extends toward the opposite direction to the first direction; and The first wiring is electrically connected to the first contact and extends in a second direction that is perpendicular to the first direction. The semiconductor device of claim 2 includes: a first electrode electrically connected to the first wiring; and a second electrode physically connected to the first electrode. A semiconductor device according to claim 3, further comprising: a second contact electrically connected to the second electrode and extending in a direction opposite to the first direction. The semiconductor device of claim 4, wherein the second contact is electrically connected to the first transistor included in the control circuit. The semiconductor device of claim 5 is provided with: a third contact electrically connected to the first word line and extending toward the opposite direction to the first direction. The semiconductor device according to claim 6 is provided with: a second wiring electrically connecting the second contact and the third contact and extending along the second direction. The semiconductor device of claim 6, wherein the third contact is electrically connected to the first transistor. The semiconductor device of claim 4, wherein the second contact penetrates the first memory cell array. The semiconductor device of claim 9, wherein the first word line is provided around the second contact.