CN116845110A - 一种具有低续流损耗的功率半导体器件及其制造方法 - Google Patents
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Abstract
一种具有低续流损耗的功率半导体器件及其制造方法。器件包括金属、重掺杂第一导电类型衬底及外延层、第二导电类型体区、第一导电类型增强源区和重掺杂第二导电类型体接触区,第一导电类型半导体区,增强源区之下且贯穿体区的第一导电类型半导体层、介质层一、栅电极、介质层二、金属。方法:在重掺杂衬底上制得第一导电类型外延层;在外延层上形成第二导电类型体区;在体区上形成增强源区;在增强源区下方形成第一导电类型半导体层且贯穿体区;在体区上形成体接触区;在体区中形成第一导电类型半导体区;退火激活杂质;器件上表面生长介质层一、多晶硅、介质层二、栅电极;在增强源区和接触区生成金属,背面淀积金属。
Description
技术领域
本发明属于功率半导体器件结构设计及制造技术领域,具体而言是一种具有低续流损耗的功率半导体器件及其制造方法。
背景技术
功率半导体器件是实现电能转换的核心器件,主要用途包括逆变、变频等。应用在电动设备(电动车、高铁、电机)、光伏逆变器、家电(空调、冰箱)。在桥式电路中,为了避免上下管同时导通而烧毁,常常设置死区时间,而死区时间采用MOSFET体二极管进行续流,因此续流损耗是功率半导体器件功率损耗的重要因素。
随着业界对新一代电力电子系统在功率密度和效率等方面的更高要求,功率半导体器件不仅需要具有出色的正向导通特性,反向导通特性的优化也需特别关注。作为开关器件,当电路中产生很大的瞬间电流时,MOSFET需要一个反向的续流二极管,避免击穿器件。目前对于续流二极管的选择主要有如下几种方案:1、采用外接二极管的方式,但是这会给系统带来额外的寄生电容及电感,增加系统的损耗,不利于功率器件高频性能的提升;2、采用二极管与开关器件集成封装的形式,但这种方法会额外增加芯片的面积,从而增加器件的成本,也会造成器件电容的显著增加,增大器件开关过程中的功耗;3、利用MOSFET器件自身的寄生体二极管作为反向工作时的续流管。但对于传统的碳化硅MOSFET来讲,体二极管的导通还会带来三个问题:一是碳化硅MOSFET体二极管接近4V的开启电压会造成系统额外的功率损耗;二是体二极管双极载流子续流,存在反向恢复电流尖峰,且开关震荡严重,其在高温情况下尤为严重;三是体二极管的导通会诱发双极退化现象,这是由于电子空穴对的复合所释放出的能量导致堆垛层错在基底面位错处蔓延,被扩大的堆垛层错覆盖的区域无法导电,因此芯片的有效有源区域缩小,最终导致器件导通电阻的退化。
为解决上述问题,通常在碳化硅MOSFET中集成肖特基二极管,这可以极大地缩小功率模块的总面积,从而降低成本和封装复杂度。但是,在碳化硅MOSFET元胞中集成肖特基二极管,需要关注反向阻断电压下肖特基接触处的电场过大问题,以及高温及镜像力引起的势垒降低促进肖特基二极管热电子发射,导致高温时反向漏电流增加的问题,因此不利于集成芯片的高温、可靠性的提升。
发明内容
本发明针对上述问题,提出了一种与现有功率器件制造工艺兼容、既可以降低器件续流损耗又不影响器件正向导通及反向阻断特性的具有低续流损耗的功率半导体器件及其制造方法。
本发明采用的技术方案如下:
本发明所述的一种具有低续流损耗的功率半导体器件,包括,金属、重掺杂第一导电类型衬底、第一导电类型外延层、第二导电类型体区、位于第二导电类型体区上方的第一导电类型增强源区和重掺杂第二导电类型体接触区,位于第二导电类型体区之间的第一导电类型半导体区,位于第一导电类型增强源区之下且贯穿第二导电类型体区的第一导电类型半导体层、介质层一、栅电极、介质层二、金属。
本发明所述的一种具有低续流损耗的功率半导体器件的制造方法:
第一步:采用外延工艺,在重掺杂第一导电类型衬底上表面制得第一导电类型外延层;
第二步:采用光刻和离子注入工艺,在所述第一导电类型外延层上层的两端注入第二导电类型半导体杂质形成第二导电类型体区;
第三步:采用沟道自对准工艺,在第二导电类型体区上层注入第一导电类型半导体杂质形成第一导电类型增强源区;
第四步:采用第一导电类型半导体层自对准工艺,在第一导电类型增强源区下方注入第一导电类型半导体杂质形成第一导电类型半导体层,且贯穿第二导电类型体区;
第五步:采用光刻和离子注入工艺,在第二导电类型体区上层注入第二导电类型半导体杂质形成重掺杂第二导电类型体接触区;
第六步:采用光刻和离子注入工艺,在第二导电类型体区中间多步注入第一导电类型半导体杂质形成第一导电类型半导体区;
第七步:通过高温退火激活注入的杂质;
第八步:在器件上表面生长介质层一,在介质层一上淀积多晶硅,然后淀积介质层二,淀积金属形成栅电极;
第九步:采用金属淀积和刻蚀工艺,在部分第一导电类型增强源区和重掺杂第二导电类型体接触区上表面生成金属,将器件背面减薄淀积金属。
与现有器件结构及制造技术相比,本发明具有如下优点:
(1)如图2所示,区域一为本发明新增加的第一导电类型半导体层8与被分开的第二导电类型体区4形成的结构。以第一导电类型是N型半导体为例,其工作原理可用图4a-图4c的能带图阐述。能带图从左至右的N+、N-、N型区域分别对应图3所示的第一导电类型增强源区5、第一导电类型半导体层8、第一导电类型外延层3。当器件不施加电压时,能带图如图4a所示;当金属电极12加正向电压时,电压由第一导电类型半导体层8与第一导电类型外延层3形成的耗尽层承担,其能带图如图4b所示,势垒高度降低,电子可以从金属电极1经过第一导电类型外延层3-第一导电类型半导体层8-第一导电类型增强源区5流向金属电极12,形成第三象限电流通路。综上所述,该发明结构利用第一导电类型半导体势垒差导电,其低于PN结势垒,因此,器件的第三象限导通压降降低,因此器件续流损耗降低。
(2)该结构引入的第一导电类型半导体层8与第一导电类型增强源区5和第一导电类型外延层3形成第三象限电流通路,导通电流为单极电流,避免了由第一导电类型外延层3和第二导电类型体区4组成的体二极管在双极载流子导电时引起的外延层的堆垛失效而导致的器件导通电阻的退化问题。
(3)该结构引入的第一导电类型半导体层8与第一导电类型增强源区5和第一导电类型外延层3形成第三象限电流通路,导通电流为单极电流,避免了由第一导电类型外延层3和第二导电类型体区4组成的体二极管双极载流子续流存在的反向恢复尖峰,很好地抑制开关震荡。
(4)该发明在正向导通与反向阻断工作条件下,当金属电极1加正向电压、金属电极12不加电压时,电压同样由第一导电类型半导体层8与第一导电类型外延层3形成的耗尽层承担,能带图如图4c所示,势垒高度增高,电子无法越过势垒,即第二导电类型体区4将第一导电类型半导体层8夹断,因此第一导电类型半导体层8的引入不影响器件正向导通和反向阻断能力。
(5)与集成肖特基二极管的结构相比,该发明不占用器件元胞面积,即没有降低沟道密度,从而在没有改变器件的比导通电阻的情况下提高了器件的续流能力。
附图说明
图1是传统的平栅功率半导体器件元胞结构剖面图。
图2是本发明实施例的具有低续流损耗的功率半导体器件元胞结构剖面图。
图3a~图3c是本发明实施例的能带图。
图4a~图4k是本发明实施例的制备过程示意图。
图5是传统的平栅功率半导体器件与本发明器件的续流电压仿真曲线图。
图6是传统的平栅功率半导体器件与本发明器件的反向阻塞电压仿真曲线图。
具体实施方式:
实施例1
一种具有低续流损耗的功率半导体器件,包括,金属1、重掺杂第一导电类型衬底2、第一导电类型外延层3、第二导电类型体区4、位于第二导电类型体区4上方的第一导电类型增强源区5和重掺杂第二导电类型体接触区6,位于第二导电类型体区4之间的第一导电类型半导体区7,位于第一导电类型增强源区5之下且贯穿第二导电类型体区4的第一导电类型半导体层8、介质层一9、栅电极10、介质层二11、金属12。
在本实施例中,
所述第二导电类型体区4内设有第一导电类型半导体层8,其在第一导电类型增强源区5下方的任何位置,且贯穿第二导电类型体区4,即第一导电类型半导体层8上边与第一导电类型增强源区5衔接,下边与第一导电类型外延层3衔接。所述半导体材料为碳化硅材料。所述介质层一9和介质层二11为SiO2介质材料。所述器件中各掺杂类型相应变为相反的掺杂,即第二导电类型掺杂变为第一导电类型掺杂的同时第一导电类型掺杂变为第二导电类型掺杂。
实施例2
一种具有低续流损耗的功率半导体器件的制造方法,
第一步:如图4a所示,采用外延工艺,在重掺杂第一导电类型衬底2上表面制得第一导电类型外延层3;
第二步:如图4b所示,采用光刻和离子注入工艺,在所述第一导电类型外延层3上层的两端注入第二导电类型半导体杂质形成第二导电类型体区4,该步骤采用不同能量、不同剂量的多步离子注入;
第三步:如图4c所示,采用沟道自对准工艺,在第二导电类型体区4上层注入第一导电类型半导体杂质形成第一导电类型增强源区5;
第四步:采用第一导电类型半导体层8自对准工艺,在第一导电类型增强源区5下方注入第一导电类型半导体杂质形成第一导电类型半导体层8,且贯穿第二导电类型体区4;
第五步:如图4h所示,采用光刻和离子注入工艺,在第二导电类型体区4上层注入第二导电类型半导体杂质形成重掺杂第二导电类型体接触区6;
第六步:如图4i所示,采用光刻和离子注入工艺,在第二导电类型体区4中间多步注入第一导电类型半导体杂质形成第一导电类型半导体区7;
第七步:通过高温退火激活注入的杂质;
第八步:如图4j所示,在器件上表面生长介质层一9,在介质层一9上淀积多晶硅,然后淀积介质层二11,淀积金属形成栅电极10;
第九步:如图4k所示,采用金属淀积和刻蚀工艺,在部分第一导电类型增强源区5和重掺杂第二导电类型体接触区6上表面生成金属12,将器件背面减薄,淀积金属1。所述第四步的详细具体步骤如下:①如图4d所示,保留第一导电类型增强源区5的掩膜版,淀积SiO2;②如图4e所示,刻蚀表面SiO2;③如图4f所示,采用不同能量、不同剂量的多步离子注入;④如图4g所示,刻蚀半导体表面掩膜版及氧化物。
Claims (7)
1.一种具有低续流损耗的功率半导体器件,其特征在于,包括,金属(1)、重掺杂第一导电类型衬底(2)、第一导电类型外延层(3)、第二导电类型体区(4)、位于第二导电类型体区(4)上方的第一导电类型增强源区(5)和重掺杂第二导电类型体接触区(6),位于第二导电类型体区(4)之间的第一导电类型半导体区(7),位于第一导电类型增强源区(5)之下且贯穿第二导电类型体区(4)的第一导电类型半导体层(8)、介质层一(9)、栅电极(10)、介质层二(11)、金属(12)。
2.根据权利要求1所述的具有低续流损耗的功率半导体器件,其特征在于:所述第二导电类型体区(4)内设有第一导电类型半导体层(8),其在第一导电类型增强源区(5)下方的任何位置,且贯穿第二导电类型体区(4)。
3.根据权利要求1所述的具有低续流损耗的功率半导体器件,其特征在于:所述半导体材料为碳化硅材料。
4.根据权利要求1所述的具有低续流损耗的功率半导体器件,其特征在于:所述介质层一(9)和介质层二(11)为SiO2介质材料。
5.根据权利要求1~4任意一项所述的具有低续流损耗的功率半导体器件,其特征在于:所述器件中各掺杂类型相应变为相反的掺杂。
6.一种权利要求1所述的具有低续流损耗的功率半导体器件的制造方法,其特征在于,
第一步:采用外延工艺,在重掺杂第一导电类型衬底(2)上表面制得第一导电类型外延层(3);
第二步:采用光刻和离子注入工艺,在所述第一导电类型外延层(3)上层的两端注入第二导电类型半导体杂质形成第二导电类型体区(4);
第三步:采用沟道自对准工艺,在第二导电类型体区(4)上层注入第一导电类型半导体杂质形成第一导电类型增强源区(5);
第四步:采用第一导电类型半导体层(8)自对准工艺,在第一导电类型增强源区(5)下方注入第一导电类型半导体杂质形成第一导电类型半导体层(8),且贯穿第二导电类型体区(4);
第五步:采用光刻和离子注入工艺,在第二导电类型体区(4)上层注入第二导电类型半导体杂质形成重掺杂第二导电类型体接触区(6);
第六步:采用光刻和离子注入工艺,在第二导电类型体区(4)中间多步注入第一导电类型半导体杂质形成第一导电类型半导体区(7);
第七步:通过高温退火激活注入的杂质;
第八步:在器件上表面生长介质层一(9),在介质层一(9)上淀积多晶硅,然后淀积介质层二(11),淀积金属形成栅电极(10);
第九步:采用金属淀积和刻蚀工艺,在部分第一导电类型增强源区(5)和重掺杂第二导电类型体接触区(6)上表面生成金属(12),将器件背面减薄淀积金属(1)。
7.根据权利要求6所述的具有低续流损耗的功率半导体器件,其特征在于:第四步的详细具体步骤如下:①保留第一导电类型增强源区(5)的掩膜版,淀积SiO2;②刻蚀表面SiO2;③采用不同能量、不同剂量的多步离子注入;④刻蚀半导体表面掩膜版及氧化物。
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