CN116845089A - Terminal voltage-resistant structure of high-voltage integrated power device - Google Patents

Terminal voltage-resistant structure of high-voltage integrated power device Download PDF

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Publication number
CN116845089A
CN116845089A CN202310944398.3A CN202310944398A CN116845089A CN 116845089 A CN116845089 A CN 116845089A CN 202310944398 A CN202310944398 A CN 202310944398A CN 116845089 A CN116845089 A CN 116845089A
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region
source
terminal
drain
contact region
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章文通
赵泉钰
吴奇益
刘腾
乔明
李肇基
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures

Abstract

The invention provides a terminal voltage-resistant structure of a high-voltage integrated power device, which comprises a cellular region, a drain center terminal structure and a source center terminal structure. The terminal region structure comprises a drain electrode N+ contact region, an Nwell region, an N-type drift region, a P-type substrate region, gate polysilicon, a gate oxide layer, a Pwell region, a source electrode P+ contact region, a source electrode N+ contact region, a field oxide layer, a polysilicon electrode and a longitudinal field plate array formed by a slot medium. The invention provides a novel terminal voltage-resistant structure aiming at high-concentration devices of a longitudinal field plate MIS structure periodically arranged in a drift region, wherein a part of the high-concentration drift region is removed at a terminal, the voltage-resistant distance is ensured by changing the length of a substrate, and the voltage resistance is borne by the substrate and a unilateral abrupt junction, so that the voltage resistance of the terminal region is relatively independent of the concentration of the drift region, and the radius of a curvature junction of the terminal is increased under the condition that the enough voltage resistance of the terminal is ensured, thereby avoiding the advanced breakdown of the device.

Description

Terminal voltage-resistant structure of high-voltage integrated power device
Technical Field
The invention belongs to the field of power semiconductors, and mainly provides a terminal voltage-resistant structure of a high-voltage integrated power device.
Background
The power semiconductor device has the characteristics of high input impedance, high switching speed, low loss, wide safe working area and the like, and is widely applied to various aspects of consumer electronics, network communication, electronic special equipment, automobile electronics and the like. The development of high voltage power integrated circuits is not separated from the development of integratable lateral high voltage power semiconductor devices. In lateral device designs, the devices are required to have high breakdown voltages, low specific on-resistance. Higher breakdown voltages require longer drift region lengths and lower drift region doping concentrations for the device, but this also results in an increase in the specific on-resistance of the device. Conventional lateral high voltage power semiconductor devices are typically closed structures, including circular, racetrack, and interdigitated structures. For the conventional closed racetrack structure and the interdigital structure, small curvature junctions occur at the curve part and the fingertip part of the terminal, and the electric field lines are easily concentrated at the small curvature, so that the device breaks down in advance, and therefore, the optimal design is needed.
In order to alleviate the contradiction between breakdown voltage and specific on-resistance, a device with a longitudinal field plate and a manufacturing method (CN 201910819933.6) thereof are proposed, and the invention improves the device withstand voltage by introducing a global MIS depletion mechanism into a device drift region, and can greatly improve the doping concentration of the device drift region to reduce the specific on-resistance. However, the structure depends on the interval between the transverse direction and the longitudinal direction, and the cell region can well deplete the high concentration region through the periodic longitudinal field plate structure, but the drift region with high concentration cannot be completely depleted in the terminal region due to the non-uniform ring formed by each longitudinal field plate structure, so that the periodic depletion cannot be completely ensured, the terminal partial electric field can be influenced, and the terminal region becomes a breakdown weak point. Therefore, we propose a novel junction terminal, by removing a part of the high-concentration drift region at the terminal, by changing the length of the substrate to ensure the withstand voltage distance, the withstand voltage of the terminal region is borne by the substrate and the unilateral abrupt junction, so that the withstand voltage of the terminal region is relatively independent of the concentration of the drift region, the radius of curvature junction of the terminal is also increased under the condition that the sufficient withstand voltage of the terminal is ensured, and the advanced breakdown of the device is avoided.
Disclosure of Invention
Aiming at a special depletion mechanism-MIS depleted high-concentration device, the invention removes a part of high-concentration doped drift region at the terminal, relies on the substrate and a unilateral abrupt junction to bear voltage resistance, increases the radius of curvature junction of the source terminal under the condition of ensuring enough voltage resistance of the terminal, improves the voltage resistance of the drain center terminal and the source center terminal, and avoids the advanced breakdown of the device in the terminal region.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
the terminal voltage-resistant structure of the high-voltage integrated power device comprises a cellular region, a drain center terminal structure and a source center terminal structure:
the cellular region includes: the drain electrode N+ contact region 1, the Nwell region 2, the N type drift region 3, the P-type substrate 4, the grid polysilicon 5, the grid oxide layer 6, the Pwell region 7, the source electrode P+ contact region 8, the source electrode N+ contact region 9, the field oxide layer 10, the slot medium 11, the polycrystalline electrode 12, the metal strip 13, the source metal 14 and the drain metal 15; the N-type drift region 3 and the Pwell region 7 are positioned above the P-type substrate 4; the Pwell region 7 is contacted with the side surface of the N-type drift region 3; the Nwell region 2 is positioned in the N-type drift region 3; the drain electrode N+ contact region 1 is positioned in the Nwell region 2, the source electrode P+ contact region 8 and the source electrode N+ contact region 9 are positioned in the Pwell region 7, and the source electrode P+ contact region 8 and the source electrode N+ contact region 9 are contacted; the gate oxide layer 6 is arranged above the Pwell region 7, the N-type drift region 3 and the source N+ contact region 9; the gate polysilicon 5 is above the gate oxide 6 and partially above the field oxide 10, the metal strip 13 is above the field oxide 10, the source metal 14 is above the source p+ contact region 8, the source n+ contact region 9, and the drain metal 15 is above the drain n+ contact region 1;
the groove medium 11 and the polycrystalline electrode 12 form a longitudinal field plate structure extending longitudinally, the number N of the longitudinal field plates is more than or equal to 0, and the longitudinal field plates are periodically distributed in the whole N-type drift region 3 to form a pressure-resistant layer with a plurality of equipotential floating grooves; the longitudinal spacing and the transverse spacing of adjacent longitudinal field plates distributed in the whole N-type drift region 3 are equal, the transverse direction is the source-drain direction, the longitudinal direction is perpendicular to the source-drain direction, and the adjacent longitudinal field plates in the source-drain direction are staggered;
the drain center terminal structure is connected with the cell area to form a closed annular structure, and is divided into a rectangular area and a semicircular area, and the drain center terminal structure comprises: the device comprises a drain electrode N+ contact region 1, an Nwell region 2, an N-type drift region 3, a P-type substrate 4, gate polysilicon 5, a gate oxide layer 6, a Pwell region 7, a source electrode P+ contact region 8, a source electrode N+ contact region 9, a field oxide layer 10, a slot medium 11, a polycrystalline electrode 12, a metal strip 13, source metal 14 and drain metal 15; the grid polysilicon 5 is above the grid oxide layer 6, part of the vertical floating field plates are periodically distributed in the N-type drift region 3 and are distributed at equal intervals with the cell regions, and the grid polysilicon is distributed in a triangular mode only in a rectangular region of the terminal part; the gate polysilicon 5, the Pwell region 7, the source P+ contact region 8, the source N+ contact region 9, the metal strip 13 and the source metal 14 of the drain center terminal structure are connected with the gate polysilicon 5, the Pwell region 7, the source P+ contact region 8, the source N+ contact region 9, the metal strip 13 and the source metal 14 in the cell region to form an annular structure, the drain N+ contact region 1, the Nwell region 2 and the drain metal 15 of the drain center terminal structure are connected with the drain N+ contact region 1, the Nwell region 2 and the drain metal 15 of the cell region to form a rectangular and arc-shaped connected structure, wherein the P-well region 7 is not connected with the N-type drift region 3, the distance between the P-well region 7 and the N-type drift region 3 in the right middle position perpendicular to the source-drain direction is L1, and the P-type substrate 4 is arranged between the N-type drift region 3 and the Pwell region 7;
the source center terminal structure is also connected with the cell area to form a closed structure, and is divided into a rectangular area and a semicircular area, and the source center terminal structure comprises: the device comprises a drain electrode N+ contact region 1, an Nwell region 2, an N-type drift region 3, a P-type substrate 4, gate polysilicon 5, a gate oxide layer 6, a Pwell region 7, a source electrode P+ contact region 8, a source electrode N+ contact region 9, a field oxide layer 10, a slot medium 11, a polycrystalline electrode 12, a metal strip 13, source metal 14 and drain metal 15; the grid polysilicon 5 is above the grid oxide layer 6, part of the vertical floating field plates are periodically distributed in the N-type drift region 3 and are distributed at equal intervals with the cell regions, and the grid polysilicon is distributed in a triangular mode only in a rectangular region of the terminal part; the drain electrode N+ contact region 1, the Nwell region 2, the grid electrode polycrystalline silicon 5, the source electrode N+ contact region 9, the metal strip 13 and the drain metal 15 of the source center terminal are connected with the drain electrode N+ contact region 1, the Nwell region 2, the grid electrode polycrystalline silicon 5, the source electrode N+ contact region 9, the metal strip 13 and the drain metal 15 in the cell region to form an annular structure, the Pwell region 7, the source electrode P+ contact region 8, the source metal 14 of the source center terminal are connected with the Pwell region 7 of the cell region, the source electrode P+ contact region 8 and the source metal 14 to form a rectangular and arc-shaped connected structure, wherein the P-well region 7 is not connected with the N type drift region 3, the interval between the P-well region 7 and the N type drift region 3 in the right middle position perpendicular to the source electrode and the drain direction is L2, and the P type substrate 4 is arranged between the N type drift region 3 and the Pwell region 7.
Preferably, the distance L1> Ld, L2> Ls;
and/or the cell area, the drain center terminal structure and the metal strip 13 of the source center terminal structure form a closed equipotential ring structure.
Preferably, the terminal N-type drift region 3 can ensure the required withstand voltage capability without full depletion.
Preferably, the N-type drift region 3 and the P-type substrate 4 form an NP junction as a junction voltage-withstanding region.
As a preferred mode, the longitudinal field plates are periodically distributed in the N-type drift region 3 at equal intervals with the cell regions, and are distributed in a triangular manner only in a rectangular region of the terminal part, and the semicircular region is free of the longitudinal field plate structure;
or the terminal area of the terminal structure is not provided with a longitudinal field plate and is a terminal voltage-resistant structure of a pure pn junction;
or the termination region of the termination structure is a discrete annular longitudinal field plate structure.
Preferably, the longitudinal spacing and the transverse spacing of adjacent longitudinal field plates distributed in the N-type drift region 3 are equal; and the cross-sectional shape of the longitudinal field plates is rectangular, or circular, or elliptical, or hexagonal.
Preferably, the termination voltage structure is suitable for drift region with a dose higher than 6E12cm -2 To improve the terminal voltage withstand capability.
Preferably, the junction termination structure is one of a single RESURF structure, a double RESURF structure, and a triple RESURF structure.
Preferably, the terminal ends are semicircular or square structures with rounded corners.
Preferably, the device is provided with a P-type doping layer 16, and a part of the P-type doping layer 16 in a cellular region is connected with the Pwell region 7 to ensure that the potentials of the P-type doping layer 16 and the Pwell region are the same; the P-well region 7 is disconnected with the P-type doped layer 16 in the terminal region and is tangential to the N-type drift region 3;
and/or wherein the P-doped layer 16 is at the surface of the device, or within the body of the device.
The beneficial effects of the invention are as follows: the vertical field plates introduce a global MIS depletion mechanism in the off-device state, depleting the N-type drift region 3. The field plates in the N-type drift region 3 are connected with the metal strips above to form an in-vivo equipotential ring so as to modulate an electric field, so that the electric field inside the device is uniformly distributed, and the device has enough voltage endurance under the condition of high concentration of the drift region. The terminal area ensures the withstand voltage distance by changing the length of the substrate, and the withstand voltage is borne by the substrate and the unilateral abrupt junction, so that the withstand voltage of the terminal area is relatively independent of the concentration of the drift area, the radius of the curvature junction of the source terminal is increased under the condition that the sufficient withstand voltage of the terminal is ensured, the withstand voltage capability of the source center terminal and the drain center terminal is improved, and the advanced breakdown of the device in the terminal area is avoided.
Drawings
Fig. 1 is a schematic view of a drain center termination structure of a termination voltage-resistant structure of a high-voltage integrated power device in embodiment 1, wherein fig. 1 (a) is a top view, fig. 1 (b) is a front view, fig. 1 (c) is a cross-sectional view at AA 'in the top view, and fig. 1 (d) is a cross-sectional view at BB' in the top view; wherein AA' is from the drain end to the source end of the rectangular area; BB 'is perpendicular to AA' and passes through the direction of the central axis of the semicircular area;
fig. 2 is a schematic view of a source center termination structure of a termination voltage-resistant structure of a high-voltage integrated power device in embodiment 1, wherein fig. 2 (a) is a top view, fig. 2 (b) is a front view, fig. 2 (c) is a cross-sectional view at CC 'in the top view, and fig. 2 (d) is a cross-sectional view at DD' in the top view; wherein CC' is from the source end to the drain end of the rectangular region; DD 'is perpendicular to CC' and passes through the direction of the central axis of the semicircular area;
FIG. 3 is a diagram showing a cell structure of embodiment 1;
fig. 4 is a schematic diagram of a terminal voltage-withstanding structure of a high-voltage integrated power device in embodiment 2, wherein fig. 4 (a) is a drain-center terminal structure and fig. 4 (b) is a source-center terminal structure;
fig. 5 is a schematic diagram of a terminal voltage-withstanding structure of a high-voltage integrated power device according to embodiment 3, wherein fig. 5 (a) is a cell structure, fig. 5 (b) is a drain-center terminal structure, and fig. 5 (c) is a source-center terminal structure;
fig. 6 is a terminal voltage-withstanding structure of a high-voltage integrated power device of embodiment 4, wherein fig. 6 (a) is a drain-center terminal structure and fig. 6 (b) is a source-center terminal structure;
fig. 7 is a terminal voltage-withstanding structure of a high-voltage integrated power device of embodiment 5, wherein fig. 7 (a) is a drain-center terminal structure and fig. 7 (b) is a source-center terminal structure;
FIG. 8 is a graph showing the equipotential line distribution of the terminal structure of the present invention at the cylindrical coordinates, FIG. 8 (a) is a drain-center terminal structure, the curvature is added to the drain end during simulation, and the dose is 9e12cm in the drift region -2 Under the condition of high concentration, the drift region is not completely exhausted, the withstand voltage is still more than 700V, and the withstand voltage design of the device 600V is met; FIG. 8 (b) is a source center termination structure with curvature applied to the source end during simulation, which is at a drift region dose of 9e12cm -2 And the withstand voltage is sufficient under the condition that the drift region is not fully depleted;
1 is a drain electrode N+ contact region, 2 is an Nwell region, 3 is an N-type drift region, 4 is a P-type substrate, 5 is gate polysilicon, 6 is a gate oxide layer, 7 is a Pwell region, 8 is a source electrode P+ contact region, 9 is a source electrode N+ contact region, 10 is a field oxide layer, 11 is a slot medium, 12 is a polycrystalline electrode, 13 is a metal strip, 14 is source metal, 15 is drain metal, and 16 is a P-doped layer.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1
The terminal voltage-resistant structure of a high-voltage integrated power device according to embodiment 1, as shown in fig. 1 to 3, includes a cell region, a drain center terminal structure and a source center terminal structure:
the cellular region includes: the drain electrode N+ contact region 1, the Nwell region 2, the N type drift region 3, the P-type substrate 4, the grid polysilicon 5, the grid oxide layer 6, the Pwell region 7, the source electrode P+ contact region 8, the source electrode N+ contact region 9, the field oxide layer 10, the slot medium 11, the polycrystalline electrode 12, the metal strip 13, the source metal 14 and the drain metal 15; the N-type drift region 3 and the Pwell region 7 are positioned above the P-type substrate 4; the Pwell region 7 is contacted with the side surface of the N-type drift region 3; the Nwell region 2 is positioned in the N-type drift region 3; the drain electrode N+ contact region 1 is positioned in the Nwell region 2, the source electrode P+ contact region 8 and the source electrode N+ contact region 9 are positioned in the Pwell region 7, and the source electrode P+ contact region 8 and the source electrode N+ contact region 9 are contacted; the gate oxide layer 6 is arranged above the Pwell region 7, the N-type drift region 3 and the source N+ contact region 9; the gate polysilicon 5 is above the gate oxide 6 and partially above the field oxide 10, the metal strip 13 is above the field oxide 10, the source metal 14 is above the source p+ contact region 8, the source n+ contact region 9, and the drain metal 15 is above the drain n+ contact region 1;
the groove medium 11 and the polycrystalline electrode 12 form a longitudinal field plate structure extending longitudinally, the number N of the longitudinal field plates is more than or equal to 0, and the longitudinal field plates are periodically distributed in the whole N-type drift region 3 to form a pressure-resistant layer with a plurality of equipotential floating grooves; the longitudinal spacing and the transverse spacing of adjacent longitudinal field plates distributed in the whole N-type drift region 3 are equal, the transverse direction is the source-drain direction, the longitudinal direction is perpendicular to the source-drain direction, and the adjacent longitudinal field plates in the source-drain direction are staggered;
the drain center terminal structure is connected with the cell area to form a closed annular structure, and is divided into a rectangular area and a semicircular area, and the drain center terminal structure comprises: the device comprises a drain electrode N+ contact region 1, an Nwell region 2, an N-type drift region 3, a P-type substrate 4, gate polysilicon 5, a gate oxide layer 6, a Pwell region 7, a source electrode P+ contact region 8, a source electrode N+ contact region 9, a field oxide layer 10, a slot medium 11, a polycrystalline electrode 12, a metal strip 13, source metal 14 and drain metal 15; the grid polysilicon 5 is above the grid oxide layer 6, part of the vertical floating field plates are periodically distributed in the N-type drift region 3 and are distributed at equal intervals with the cell regions, and the grid polysilicon is distributed in a triangular mode only in a rectangular region of the terminal part; the gate polysilicon 5, the Pwell region 7, the source P+ contact region 8, the source N+ contact region 9, the metal strip 13 and the source metal 14 of the drain center terminal structure are connected with the gate polysilicon 5, the Pwell region 7, the source P+ contact region 8, the source N+ contact region 9, the metal strip 13 and the source metal 14 in the cell region to form an annular structure, the drain N+ contact region 1, the Nwell region 2 and the drain metal 15 of the drain center terminal structure are connected with the drain N+ contact region 1, the Nwell region 2 and the drain metal 15 of the cell region to form a rectangular and arc-shaped connected structure, wherein the P-well region 7 is not connected with the N-type drift region 3, the distance between the P-well region 7 and the N-type drift region 3 in the right middle position perpendicular to the source-drain direction is L1, and the P-type substrate 4 is arranged between the N-type drift region 3 and the Pwell region 7;
the source center terminal structure is also connected with the cell area to form a closed structure, and is divided into a rectangular area and a semicircular area, and the source center terminal structure comprises: the device comprises a drain electrode N+ contact region 1, an Nwell region 2, an N-type drift region 3, a P-type substrate 4, gate polysilicon 5, a gate oxide layer 6, a Pwell region 7, a source electrode P+ contact region 8, a source electrode N+ contact region 9, a field oxide layer 10, a slot medium 11, a polycrystalline electrode 12, a metal strip 13, source metal 14 and drain metal 15; the grid polysilicon 5 is above the grid oxide layer 6, part of the vertical floating field plates are periodically distributed in the N-type drift region 3 and are distributed at equal intervals with the cell regions, and the grid polysilicon is distributed in a triangular mode only in a rectangular region of the terminal part; the drain electrode N+ contact region 1, the Nwell region 2, the grid electrode polycrystalline silicon 5, the source electrode N+ contact region 9, the metal strip 13 and the drain metal 15 of the source center terminal are connected with the drain electrode N+ contact region 1, the Nwell region 2, the grid electrode polycrystalline silicon 5, the source electrode N+ contact region 9, the metal strip 13 and the drain metal 15 in the cell region to form an annular structure, the Pwell region 7, the source electrode P+ contact region 8, the source metal 14 of the source center terminal are connected with the Pwell region 7 of the cell region, the source electrode P+ contact region 8 and the source metal 14 to form a rectangular and arc-shaped connected structure, wherein the P-well region 7 is not connected with the N type drift region 3, the interval between the P-well region 7 and the N type drift region 3 in the right middle position perpendicular to the source electrode and the drain direction is L2, and the P type substrate 4 is arranged between the N type drift region 3 and the Pwell region 7.
Preferably, the spacing L1 is greater than Ld, L2 is greater than Ls, and the lengths of L1, ls, L2 and Ld are determined according to actual needs;
the terminal N-type drift region 3 can ensure the required withstand voltage capability without full depletion.
The N-type drift region 3 and the P-type substrate 4 form an NP-junction as a junction voltage-resistant region;
the longitudinal field plates are periodically distributed in the N-type drift region 3 at equal intervals with the cell regions, and are distributed in a triangular manner only in a rectangular region of the terminal part, and the semicircular region is free of the longitudinal field plate structure;
the longitudinal spacing and the transverse spacing of adjacent longitudinal field plates distributed in the N-type drift region 3 are equal; and the cross-sectional shape of the longitudinal field plate is rectangular, or circular, or elliptical, or hexagonal;
the cell region, the drain center terminal structure and the metal strip 13 of the source center terminal structure form a closed equipotential ring structure.
The basic working principle is as follows:
when the device is in a reverse bias condition, the longitudinal field plates are introduced into a global MIS depletion mechanism, and are connected through the metal strips 13 to form an in-vivo equipotential ring to modulate an electric field, so that the electric field inside the device is uniformly distributed, and the high voltage-withstanding capability of a drift region is ensured. For the terminal structure, a part of the high-concentration doped drift region is removed at the terminal, the withstand voltage distance is ensured by changing the length of the substrate, and the withstand voltage is borne by the substrate and the unilateral abrupt junction, so that the withstand voltage of the terminal region is relatively independent of the concentration of the drift region, the radius of the curvature junction of the source terminal is increased under the condition that the sufficient withstand voltage of the terminal is ensured, the withstand voltage capability of the source center terminal and the drain center terminal is improved, and the advanced breakdown of the device in the terminal region is avoided.
Example 2
As shown in fig. 4, a schematic diagram of a terminal voltage withstanding structure of a high voltage integrated power device in embodiment 2 is shown, and the difference between the structure of this embodiment and that of embodiment 1 is that: the terminal end of the device is of a round-angle square structure, the occupied area of the chip can be reduced by changing the shape of a metal equipotential ring, and the working principle is basically the same as that of the embodiment 1.
Example 3
Referring to fig. 5, a schematic diagram of a terminal voltage-withstanding structure of a high-voltage integrated power device in embodiment 3 is shown, which is different from that in embodiment 1 in that the device is provided with a P-type doped layer 16, and a part of the P-type doped layer 16 in a cell region is connected with a Pwell region 7 to ensure that the potentials of the P-type doped layer and the Pwell region are the same; . The introduction of the P-doped layer 16 brings about double charge self-balance, the MIS electrode high potential assists in depleting the P-type impurity, the MIS electrode low potential assists in depleting the N-type impurity, and meanwhile the P-type impurity and the N-type impurity can mutually deplete, so that the concentration of the drift region can be greatly increased, and the specific on-resistance is reduced. At the same time, the P-doped layer 16 ensures the continuity of the depletion. Likewise, where the P-well region 7 is not connected to the P-doped layer 16 in the termination region, it is tangential to the N-drift region 3 to deplete the termination of N-type impurities. The P-type doped layer 16 may be on the surface of the device or in the body of the device.
Example 4
As shown in fig. 6, a schematic diagram of a terminal voltage-withstanding structure of a high-voltage integrated power device in embodiment 4 is shown, and the difference between the structure of this embodiment and that of embodiment 1 is that the rectangular terminal area of the device has no longitudinal field plate structure, is a terminal structure of a pure pn junction, and has better reliability, and the working principle is basically the same as that of embodiment 1.
Example 5
As shown in fig. 7, a schematic diagram of a terminal voltage withstanding structure of a high voltage integrated power device in embodiment 5 is shown, and the difference between the structure of this embodiment and that of embodiment 1 is that: the termination region of the device is a discrete longitudinal field plate structure, can be fully depleted for a high concentration drift region, and has the same working principle as that of the embodiment 1.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.

Claims (10)

1. The terminal voltage-resistant structure of the high-voltage integrated power device is characterized by comprising a cellular region, a drain center terminal structure and a source center terminal structure:
the cellular region includes: the device comprises a drain electrode N+ contact region (1), an Nwell region (2), an N-type drift region (3), a P-type substrate (4), gate polysilicon (5), a gate oxide layer (6), a Pwell region (7), a source electrode P+ contact region (8), a source electrode N+ contact region (9), a field oxide layer (10), a slot medium (11), a polycrystalline electrode (12), a metal strip (13), source metal (14) and drain metal (15); the N-type drift region (3) and the Pwell region (7) are positioned above the P-type substrate (4); the Pwell region (7) is contacted with the side surface of the N-type drift region (3); the Nwell region (2) is positioned in the N-type drift region (3); the drain electrode N+ contact region (1) is positioned in the Nwell region (2), the source electrode P+ contact region (8) and the source electrode N+ contact region (9) are positioned in the Pwell region (7), and the source electrode P+ contact region (8) and the source electrode N+ contact region (9) are contacted; the gate oxide layer (6) is arranged above the Pwell region (7), the N-type drift region (3) and the source N+ contact region (9); the gate polysilicon (5) is above the gate oxide layer (6) and partially above the field oxide layer (10), the metal strip (13) is above the field oxide layer (10), the source metal (14) is above the source P+ contact region (8) and the source N+ contact region (9), and the drain metal (15) is above the drain N+ contact region (1);
the groove medium (11) and the polycrystalline electrode (12) form a longitudinal field plate structure extending longitudinally, the number N of the longitudinal field plates is more than or equal to 0, and the longitudinal field plates are periodically distributed in the whole N-type drift region (3) to form a pressure-resistant layer with a plurality of equipotential floating grooves; the longitudinal spacing and the transverse spacing of adjacent longitudinal field plates distributed in the whole N-type drift region (3) are equal, the transverse direction is the source-drain direction, the longitudinal direction is perpendicular to the source-drain direction, and the adjacent longitudinal field plates in the source-drain direction are staggered;
the drain center terminal structure is connected with the cell area to form a closed annular structure, and is divided into a rectangular area and a semicircular area, and the drain center terminal structure comprises: the device comprises a drain electrode N+ contact region (1), an Nwell region (2), an N-type drift region (3), a P-type substrate (4), gate polysilicon (5), a gate oxide layer (6), a Pwell region (7), a source electrode P+ contact region (8), a source electrode N+ contact region (9), a field oxide layer (10), a slot medium (11), a polycrystalline electrode (12), a metal strip (13), source metal (14) and drain metal (15); the grid polysilicon (5) is arranged above the grid oxide layer (6), part of the vertical floating field plates are periodically distributed in the N-type drift region (3) and are distributed at equal intervals with the cell region, and the grid polysilicon is distributed in a triangular mode only in a rectangular region of the terminal part; the drain center terminal structure comprises grid polycrystalline silicon (5), a Pwell region (7), a source P+ contact region (8), a source N+ contact region (9), a metal strip (13), source metal (14) and grid polycrystalline silicon (5), the Pwell region (7), the source P+ contact region (8), the source N+ contact region (9), the metal strip (13) and the source metal (14) in the cell region, which are connected to form an annular structure, the drain N+ contact region (1), the Nwell region (2) and the drain metal (15) in the drain center terminal structure are connected to the drain N+ contact region (1), the Nwell region (2) and the drain metal (15) in the cell region to form a rectangular and arc-shaped connected structure, wherein the P-well region (7) is not connected with the N-type drift region (3), the interval between the P-well region (7) and the N-type drift region (3) in the positive middle position perpendicular to the source drain direction is L1, and the P-type drift region (7) is between the N-type drift region (3) and the Pwell region (7) is a P-type substrate (4);
the source center terminal structure is also connected with the cell area to form a closed structure, and is divided into a rectangular area and a semicircular area, and the source center terminal structure comprises: the device comprises a drain electrode N+ contact region (1), an Nwell region (2), an N-type drift region (3), a P-type substrate (4), gate polysilicon (5), a gate oxide layer (6), a Pwell region (7), a source electrode P+ contact region (8), a source electrode N+ contact region (9), a field oxide layer (10), a slot medium (11), a polycrystalline electrode (12), a metal strip (13), source metal (14) and drain metal (15); the grid polysilicon (5) is arranged above the grid oxide layer (6), part of the vertical floating field plates are periodically distributed in the N-type drift region (3) and are distributed at equal intervals with the cell region, and the grid polysilicon is distributed in a triangular mode only in a rectangular region of the terminal part; the drain electrode N+ contact region (1), the Nwell region (2), the grid electrode polycrystalline silicon (5), the source electrode N+ contact region (9), the metal strip (13), the drain metal (15) are connected with the drain electrode N+ contact region (1), the Nwell region (2), the grid electrode polycrystalline silicon (5), the source electrode N+ contact region (9), the metal strip (13) and the drain metal (15) in the cell region to form a ring-shaped structure, the Pwell region (7), the source electrode P+ contact region (8) and the source metal (14) of the source electrode center terminal are connected with the Pwell region (7), the source electrode P+ contact region (8) and the source metal (14) of the cell region to form a rectangular and arc-shaped connected structure, wherein the P-well region (7) is not connected with the N-type drift region (3), the interval between the P-well region (7) and the N-type drift region (3) in the right middle position perpendicular to the source electrode drain direction is L2, and the P-well region (7) is a P-type substrate (4) between the N-type drift region (3) and the P-type drift region (7).
2. The terminal voltage withstanding structure of a high voltage integrated power device according to claim 1, wherein: the spacing L1> Ld, L2> Ls;
and/or the cell area, the drain center terminal structure and the metal strip (13) of the source center terminal structure form a closed equipotential ring structure.
3. The terminal voltage withstanding structure of a high voltage integrated power device according to claim 1, wherein: the terminal N-type drift region 3 can ensure the required withstand voltage capability without full depletion.
4. The terminal voltage withstanding structure of a high voltage integrated power device according to claim 1, wherein: the N-type drift region (3) and the P-type substrate (4) form an NP-junction as a junction voltage-resistant region.
5. The terminal voltage withstanding structure of a high voltage integrated power device according to claim 1, wherein: the longitudinal field plates are periodically distributed in the N-type drift region (3) at equal intervals with the cell regions, and are distributed in a triangular manner only in a rectangular region of the terminal part, and the semicircular region is free of the longitudinal field plate structure;
or the terminal area of the terminal structure is not provided with a longitudinal field plate and is a terminal voltage-resistant structure of a pure pn junction;
or the termination region of the termination structure is a discrete annular longitudinal field plate structure.
6. The terminal voltage withstanding structure of a high voltage integrated power device according to claim 1, wherein: the longitudinal spacing and the transverse spacing of adjacent longitudinal field plates distributed in the N-type drift region (3) are equal; and the cross-sectional shape of the longitudinal field plates is rectangular, or circular, or elliptical, or hexagonal.
7. The terminal voltage withstanding structure of a high voltage integrated power device according to claim 1, wherein: the terminal voltage-resistant structure is suitable for drift region with the dose higher than 6E12cm -2 To improve the terminal voltage withstand capability.
8. The terminal voltage withstanding structure of a high voltage integrated power device according to claim 1, wherein: the junction terminal structure is one of a single RESURF structure, a double RESURF structure and a triple RESURF structure.
9. The terminal voltage withstanding structure of a high voltage integrated power device according to claim 1, wherein: the terminal end is semicircular or square with rounded corners.
10. The terminal voltage withstanding structure of a high voltage integrated power device according to claim 1, wherein: the device is provided with a P-type doping layer (16), and one part of the P-type doping layer (16) in a cellular region is connected with a Pwell region (7) to ensure that the potentials of the P-type doping layer and the Pwell region are the same; the P-well region (7) is disconnected with the P-type doped layer (16) in the terminal region and is tangential to the N-type drift region (3);
and/or wherein the P-doped layer (16) is at the device surface, or within the device body.
CN202310944398.3A 2023-07-28 2023-07-28 Terminal voltage-resistant structure of high-voltage integrated power device Pending CN116845089A (en)

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CN202310944398.3A CN116845089A (en) 2023-07-28 2023-07-28 Terminal voltage-resistant structure of high-voltage integrated power device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310944398.3A CN116845089A (en) 2023-07-28 2023-07-28 Terminal voltage-resistant structure of high-voltage integrated power device

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CN116845089A true CN116845089A (en) 2023-10-03

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