CN116844604A - Memory cell pair, array, memory circuit, electronic device and method - Google Patents

Memory cell pair, array, memory circuit, electronic device and method Download PDF

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Publication number
CN116844604A
CN116844604A CN202210298988.9A CN202210298988A CN116844604A CN 116844604 A CN116844604 A CN 116844604A CN 202210298988 A CN202210298988 A CN 202210298988A CN 116844604 A CN116844604 A CN 116844604A
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China
Prior art keywords
memory
transistor
coupled
pole
independent
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CN202210298988.9A
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Chinese (zh)
Inventor
王朝
王昭昊
冯家高
赵巍胜
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Beihang University
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Beihang University
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Priority to CN202210298988.9A priority Critical patent/CN116844604A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

The embodiment of the application provides a memory cell pair, an array, a memory circuit, electronic equipment and a method, wherein the memory cell pair comprises: a pair of memory sub-cells and a common transistor; each memory subunit includes a separate transistor and a memory element; the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element. The application achieves the aim of reducing the driving resistance by the serial connection and parallel connection of the common transistor and the independent transistor, and simultaneously the introduced common transistor is reasonably distributed at the interval between the two storage sub-units, and the driving capability of the storage unit is improved by reducing the driving resistance under the condition of not increasing the area.

Description

Memory cell pair, array, memory circuit, electronic device and method
Technical Field
The present application relates to the field of electronics, and in particular, to a memory cell pair, an array, a memory circuit, an electronic device, and a method.
Background
With the continuous shrinking of semiconductor process dimensions, moore's law slows down, and the increase in leakage current and interconnect delay become bottlenecks in conventional CMOS memories. The search for new generation memory technology solutions has become an important point in integrated circuit research, where new non-volatile memories are receiving extensive attention from the industry due to their near zero static power consumption. The novel nonvolatile memory mainly comprises a resistance change memory, a phase change memory, a magnetic memory and the like, and is mainly characterized in that data are represented through high and low resistance states of a device, and the level of the nonvolatile memory is not the level of the nonvolatile memory, so that negligible leakage current is obtained.
The memory cell of the common novel nonvolatile memory is composed of a selection unit (mainly NMOS transistor) and a nonvolatile memory device, and as the CMOS process size is continuously reduced, the power supply voltage is reduced, and the on resistance of the NMOS transistor with the minimum size is increased, so that the driving pressure of the selection transistor is gradually increased, the single NMOS transistor with the minimum size is difficult to meet the driving requirement, and the size, the voltage or the speed are required to be increased, so that the performance of the novel nonvolatile memory is not beneficial to the improvement.
Disclosure of Invention
In order to solve the problems in the prior art, the application provides a memory cell pair, and a memory cell pair array, a memory circuit and an electronic device which are formed based on the memory cell pair, wherein the memory cell pair comprises: a pair of memory sub-cells and a common transistor; each memory subunit includes a separate transistor and a memory element; the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element. The application achieves the aim of reducing the driving resistance by the serial connection and parallel connection of the common transistor and the independent transistor, and simultaneously the introduced common transistor is reasonably distributed at the interval between the two storage sub-units, and the driving capability of the storage unit is improved by reducing the driving resistance under the condition of not increasing the area.
In one aspect of the present application, there is provided a memory cell pair comprising:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
In a preferred embodiment, the storage element is a storage resistor.
In a preferred embodiment, the common transistor is one of an NMOS transistor and a PMOS transistor.
In a preferred embodiment, each individual transistor is one of an NMOS transistor and a PMOS transistor.
In still another aspect of the present application, there is provided a memory cell pair array including a plurality of memory cell pairs arranged in an array, each memory cell pair including:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
In yet another aspect of the present application, there is provided a memory circuit including at least one memory cell pair array, each memory cell pair array including a plurality of memory cell pairs arranged in an array, each memory cell pair including:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
In yet another aspect of the present application, a memory is provided that includes a memory circuit including at least one array of memory cell pairs, each array of memory cell pairs including a plurality of memory cell pairs arranged in an array, each memory cell pair including:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
In yet another aspect of the present application, an electronic device is provided that includes a memory and a processor for executing data and/or programs stored in the memory, the memory including a memory circuit including at least one array of memory cell pairs, each array of memory cell pairs including a plurality of array-arranged pairs of memory cells, each pair of memory cells including:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
In yet another aspect of the present application, there is provided a writing method of a memory cell pair, including:
accessing a first voltage to a bit line coupled to the other end of the storage element in any storage subunit to be written;
accessing a second voltage to a source line coupled to a first pole of an independent transistor in the memory subunit;
and introducing control voltages to the writing word line and the two word lines to control the storage elements in the storage sub-units to conduct a set-direction current, wherein the set-direction current is determined based on the voltage difference between the first voltage and the second voltage.
In yet another aspect of the present application, a method for reading a pair of memory cells is provided, including:
accessing a third voltage to a bit line coupled to the other end of the memory sub-unit memory element to be read;
accessing a fourth voltage to a source line coupled to a first pole of an independent transistor in the memory subunit;
introducing a control voltage to a word line coupled to a control electrode of an independent transistor in the memory subunit, and acquiring voltage value information and current value information of a memory element of the memory subunit, wherein the voltage value information is determined based on a voltage difference between the third voltage and the fourth voltage;
and determining the storage information in the storage subunit according to the voltage value information and the current value information.
In yet another aspect of the present application, a method for fabricating a memory cell pair is provided, including:
forming a pair of memory sub-cells and a common transistor on a substrate under the same etching process step; each memory subunit includes a separate transistor and a memory element; wherein each transistor includes a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, coupling its control electrode with a word line, coupling its first electrode with one end of the corresponding storage element, coupling its second electrode with a common source line, and coupling the other end of each storage element individually on a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes thereof are each coupled between an independent transistor of a memory subunit and a storage element.
As can be seen from the above technical solutions, the present application provides a memory cell pair, an array, a memory circuit, an electronic device and a method, where the memory cell pair includes: a pair of memory sub-cells and a common transistor; each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole; the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element. The application achieves the aim of reducing the driving resistance by the serial connection and parallel connection of the common transistor and the independent transistor, and simultaneously the introduced common transistor is reasonably distributed at the interval between the two storage sub-units, and the driving capability of the storage unit is improved by reducing the driving resistance under the condition of not increasing the area.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory cell pair according to an embodiment of the present application.
FIG. 2 is a schematic diagram of a memory cell pair writing and reading method according to an embodiment of the present application.
FIG. 3 is a flow chart of a method for writing a memory cell pair according to an embodiment of the application.
FIG. 4 is a flow chart of a method for reading a memory cell pair according to an embodiment of the application.
FIG. 5 is a schematic diagram of a memory cell pair array according to an embodiment of the application.
Fig. 6 is a schematic diagram of a memory cell array according to the prior art in an embodiment of the present application.
FIG. 7 is a flow chart of a method for fabricating a memory cell pair according to an embodiment of the application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
With the continuous shrinking of semiconductor process dimensions, moore's law slows down, and the increase in leakage current and interconnect delay become bottlenecks in conventional CMOS memories. The search for new generation memory technology solutions has become an important point in integrated circuit research, where new non-volatile memories are receiving extensive attention from the industry due to their near zero static power consumption. The novel nonvolatile memory mainly comprises a resistance change memory, a phase change memory, a magnetic memory and the like, and is mainly characterized in that data are represented through high and low resistance states of a device, and the level of the nonvolatile memory is not the level of the nonvolatile memory, so that negligible leakage current is obtained.
The memory cell of the common novel nonvolatile memory is composed of a selection unit (mainly NMOS transistor) and a nonvolatile memory device, and as the CMOS process size is continuously reduced, the power supply voltage is reduced, and the on resistance of the NMOS transistor with the minimum size is increased, so that the driving pressure of the selection transistor is gradually increased, the single NMOS transistor with the minimum size is difficult to meet the driving requirement, and the size, the voltage or the speed are required to be increased, so that the performance of the novel nonvolatile memory is not beneficial to the improvement.
In view of the problems in the prior art, the present application provides a memory cell pair, including: a pair of memory sub-cells and a common transistor; each memory subunit includes a separate transistor and a memory element; the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and the storage element. The aim of reducing the driving resistance is achieved through the serial connection and the parallel connection of the common transistor and the independent transistor, and meanwhile, the introduced common transistor is reasonably distributed at the interval between the two storage sub-units, so that the driving capability of the storage unit is improved through reducing the driving resistance under the condition of not increasing the area.
The present application will be described in detail with reference to the accompanying drawings.
In a first aspect of the present application, a memory cell pair is provided, as in the embodiment shown in fig. 1, comprising a memory subunit (comprising an independent transistor N0 and a memory element R0) and another memory subunit (comprising an independent transistor N1 and a memory element R1) and a common transistor N2. In a specific embodiment, the transistor is one of an NMOS transistor and a PMOS transistor, where the three transistors should be of the same type, for example, if the independent transistor N0 is an NMOS transistor, the independent transistor N1 is also an NMOS transistor, and the common transistor N2 is also an NMOS transistor; if the independent transistor N0 is a PMOS transistor, the independent transistor N1 is also a PMOS transistor, and the common transistor N2 is also a PMOS transistor. In a specific embodiment, the memory element is a nonvolatile memory element, that is, the information in the memory element is not lost when the memory cell is powered off, for example, the memory resistor is made of a nonconductive material, and reversible conversion is realized between a high-resistance state and a low-resistance state under the action of an applied electric field, so that one bit of information is recorded.
In a specific embodiment, each transistor includes a first pole, a second pole, and a control pole controlling the first pole to conduct with the second pole; the first pole and the second pole respectively correspond to the source electrode and the drain electrode of the transistor, for example, if the first pole is the source electrode, the second pole is the drain electrode; the control electrode corresponds to the gate of the transistor. As shown in fig. 1, the control electrode of the independent transistor N0 is coupled to the word line WL2i, the first electrode thereof is coupled to one end of the storage element R0, and the second electrode thereof is coupled to the common source line SLj; the gate of the independent transistor N1 is coupled to the word line WL2i+1, the first electrode thereof is coupled to one end of the storage element R1, and the second electrode thereof is coupled to the common source line SLj. For the common transistor, as shown in fig. 1, the control electrode of the common transistor N2 is coupled to the write word line WWLi, with a first electrode coupled between the independent transistor N0 and the storage element R0, and a second electrode coupled between the independent transistor N1 and the storage element R1.
It can be understood that when the memory cell pair proposed by the present application is used for writing, the driving capability is stronger as the driving resistance is smaller when the driving voltage applied between the bit line and the source line is unchanged. Thus, in a specific embodiment, as shown in (a) of fig. 2, a write operation to memory device R0: the word line WL2i, the write word line WWLi, and the word line WL2i+1 are led with control voltages, the bit lines BL1, j are suspended, the bit line BL0, j is connected with the first voltage, the source line SLj is connected with the second voltage, that is, the voltage is applied to an equivalent element formed by connecting the two ends of the SLj and the BL0, and the N1 and the N2 in series, and the equivalent element is connected in parallel with the N0 and is used as a driving resistor of the storage element R0, and the equivalent driving resistor value is two thirds of the resistance value of a single transistor, so that for R0, if the prior art is adopted, that is, the common transistor N2 is not led, the driving resistor of R0 is the resistance of the independent transistor N0, and after the common transistor N2 is led, the driving resistor is reduced by one third, and the driving capability is further improved. Also, as shown in (b) of fig. 2, a write operation to the memory device R1: the word line WL2i, the write word line WWLi and the word line WL2i+1 are led in a control voltage, the bit lines BL0 and j are suspended, the bit line BL1 and j are connected with a first voltage, the source line SLj is connected with a second voltage, namely, a voltage is applied to an equivalent element formed by connecting the SLj with two ends of the bit line BL1 and the bit line j in series, and the equivalent element is connected with the N1 in parallel and then is used as a driving resistor of the storage element R1, and the equivalent driving resistor value of the equivalent element is two thirds of the resistance value of a single transistor, so that for R1, if the prior art is adopted, namely, the common transistor N2 is not led in, the driving resistor of the R1 is the resistance of the independent transistor N1, and after the common transistor N2 is led in, the driving resistor is reduced by one third.
As can be seen from the above description, the pair of memory cells provided by the present application achieves the purpose of reducing the driving resistance by introducing a common transistor in series and parallel with the independent transistors, thereby improving the driving capability of the memory cells.
In a second aspect of the present application, there is provided a method for writing information to a pair of memory cells provided in the first aspect of the present application, as shown in fig. 3, including:
s1, connecting a first voltage to a bit line coupled with the other end of a storage element in any storage subunit to be written;
s2, connecting a second voltage to a source line coupled to a first pole of an independent transistor in the storage subunit;
and S3, introducing control voltages to the writing word line and the two word lines to control the storage elements in the storage subunit to conduct a set-direction current, wherein the set-direction current is determined based on the voltage difference between the first voltage and the second voltage.
Specifically, as shown in (a) of fig. 2, the write operation to the memory device R0: the word lines WL2i, WWLi, WL2i+1 are supplied with control voltages, the bit lines BL1, j are suspended, the bit lines BL0, j are connected to the first voltage, and the source line SLj is connected to the second voltage. The voltage difference between the first voltage and the second voltage is generated according to the information to be written, if the bit to be written is 1, the corresponding voltage difference is a positive value, all transistors are turned on, so that current flows from a bit line to a source line through a storage element, and the storage element records the bit 1 to be written currently under the action of the current direction; if the bit 0 needs to be written, the corresponding voltage difference is negative, and all transistors are turned on, so that current flows from the source line to the storage element and finally to the bit line, and the storage element records the bit 0 needing to be written currently under the action of the current direction.
In a third aspect of the present application, a method for reading information stored in a memory cell pair according to the first aspect of the present application is provided, as shown in fig. 4, including:
s101, connecting a third voltage to a bit line coupled to the other end of a storage element of any storage subunit to be read;
s102, connecting a fourth voltage to a source line coupled to a first pole of an independent transistor in the storage subunit;
s103, introducing control voltage to a word line coupled with a control electrode of an independent transistor in the storage subunit, and acquiring voltage value information and current value information of a storage element of the storage subunit, wherein the voltage value information is determined based on a voltage difference between the third voltage and the fourth voltage;
and S104, determining the storage information in the storage subunit according to the voltage value information and the current value information.
Specifically, as shown in (c) of fig. 2, a read operation for the memory device R0: the word line WL2i is supplied with a control voltage, the bit line BL1, j is suspended, the bit line BL0, j is supplied with a third voltage, and the source line SLj is supplied with a fourth voltage. If N0 is NMOS, current flows from the bit line BL0, j to the source line SLj, and the voltage difference between the two ends of R0 and the current flowing through R0 are obtained to generate the resistance value of the storage element R0, if the resistance value is high, the bit information stored in the current R0 is 1, and if the resistance value is low, the bit information stored in the current R0 is 0. As shown in (d) of fig. 2, a read operation of the memory device R1: the word line WL2i +1 is supplied with a control voltage, the bit line BL0, j is suspended, the bit line BL1, j is supplied with a third voltage, and the source line SLj is supplied with a fourth voltage. If N1 is NMOS, the read circuit flows from the bit line BL1, j to the source line SLj. Similarly, the voltage difference between the two ends of R1 and the current flowing through R1 are obtained to generate the resistance value of the storage element R1, if the resistance is high, the bit information stored in the current R1 is 1, and if the resistance is low, the bit information stored in the current R1 is 0.
In a fourth aspect of the present application, there is provided a memory cell pair array comprising a plurality of memory cell pairs provided in the first aspect of the present application arranged in an array.
Specifically, the memory array is generally a two-dimensional array, fig. 5 is a schematic diagram of a memory cell array according to the prior art, and fig. 6 is a schematic diagram of a memory cell array according to an embodiment of the present application. As can be seen by comparing fig. 5 and 6, the newly added common transistors are at the intervals of the conventional structure, each sharing the source and drain with the adjacent transistors, and the vertical dimension is not increased. As can be further appreciated by comparing fig. 5 and fig. 6, the memory cell pair array provided by the present application is further increased by one bit line BL compared with the memory cell array provided by the prior art, and the lateral dimension is not increased because the newly increased bit line BL can be disposed above the source line SL.
Therefore, the common transistor is introduced to improve the driving capability of the memory cells in the memory array, but the area is not changed by reasonably utilizing the interval of the traditional structure.
In a fifth aspect of the present application, there is provided a memory circuit comprising at least one memory cell pair array provided in the fourth aspect of the present application, each memory cell pair array comprising a plurality of memory cell pairs provided in the first aspect of the present application arranged in an array. It will be appreciated that the memory circuit includes not only the memory cells for storing information, but also the power supply circuits and associated control circuits for the word lines required to drive the memory cells.
The memory module of the memory circuit comprises the memory cell pair provided by the first aspect of the application, and the memory cell pair is connected with the independent transistor in series and parallel by introducing a common transistor, so that the purpose of reducing the driving resistance is achieved, and the driving capability of the memory cell is improved. But it allows no change in area by reasonably utilizing the spacing of the conventional structure. The memory circuit formed by the memory cell pairs improves the memory driving capability without increasing the memory circuit area.
In a sixth aspect of the present application, there is provided a memory comprising a memory circuit comprising at least one array of memory cell pairs provided in the fourth aspect of the present application, each array of memory cell pairs comprising a plurality of memory cell pairs provided in the first aspect of the present application arranged in an array. It can be understood that the memory may include an address latch module, a timing generation module, a data buffer module, a memory circuit module, and the like, where the memory circuit module stores information by using the memory unit provided in the first aspect of the present application, so that the memory has the advantage of improving the memory driving capability while not increasing the size of the memory.
In a seventh aspect of the present application, there is provided an electronic device comprising a memory and a processor for executing data and/or programs stored in the memory, the memory comprising a memory circuit comprising at least one array of memory cell pairs, each array of memory cell pairs comprising a plurality of array arranged pairs of memory cells. It can be understood that the memory in the electronic device adopts the pair of memory cells provided in the first aspect of the present application to store information, so that the electronic device improves the driving capability of the memory cells in the electronic device without increasing the size of the device.
In an eighth aspect of the present application, a method for manufacturing a memory cell pair, as shown in fig. 7, includes:
s201: forming a pair of memory sub-cells and a common transistor on a substrate under the same etching process step; each memory subunit includes a separate transistor and a memory element; wherein each transistor includes a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
s202: for each independent transistor, coupling its control electrode with a word line, coupling its first electrode with one end of the corresponding storage element, coupling its second electrode with a common source line, and coupling the other end of each storage element individually on a bit line;
s203: the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes thereof are each coupled between an independent transistor of a memory subunit and a storage element.
According to the manufacturing method of the memory cell pair, the common transistor and the independent transistors are manufactured, the control electrode of each independent transistor is coupled with one word line, the first electrode of each independent transistor is coupled with one end of a corresponding memory element, the second electrode of each independent transistor is coupled to a common source line, the other end of each memory element is respectively coupled with one bit line, the control electrode of the common transistor is coupled with one write word line, the first electrode and the second electrode of each common transistor are respectively coupled between the independent transistor and the memory element of one memory subunit, the purpose of reducing the driving resistance is achieved, meanwhile, the introduced common transistor is reasonably distributed at the interval between the two memory subunits, and the driving capability of the memory cell is improved by reducing the driving resistance under the condition of not increasing the area.
The principles and embodiments of the present application have been described in detail with reference to specific examples, which are provided to facilitate understanding of the method and core ideas of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims (11)

1. A pair of memory cells, comprising:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
2. The pair of memory cells of claim 1 wherein said memory element is a memory resistor.
3. The pair of memory cells of claim 1 wherein the common transistor is one of an NMOS transistor and a PMOS transistor.
4. The pair of memory cells of claim 1, wherein each individual transistor is one of an NMOS transistor and a PMOS transistor.
5. A memory cell pair array comprising a plurality of memory cell pairs arranged in an array, each memory cell pair comprising:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
6. A memory circuit comprising at least one array of memory cell pairs, each array of memory cell pairs comprising a plurality of memory cell pairs arranged in an array, each memory cell pair comprising:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
7. A memory comprising a memory circuit, the memory circuit comprising at least one array of memory cell pairs, each array of memory cell pairs comprising a plurality of memory cell pairs arranged in an array, each memory cell pair comprising:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
8. An electronic device comprising a memory and a processor for executing data and/or programs stored in the memory, the memory comprising a memory circuit comprising at least one array of memory cell pairs, each array of memory cell pairs comprising a plurality of array arranged memory cell pairs, each memory cell pair comprising:
a pair of memory sub-cells and a common transistor;
each memory subunit includes a separate transistor and a memory element; wherein each transistor comprises a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, the control electrode of the independent transistor is coupled with a word line, the first electrode of the independent transistor is coupled with one end of a corresponding storage element, the second electrode of the independent transistor is coupled to a common source line, and the other end of each storage element is respectively coupled with a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes are each coupled between an independent transistor of a memory subunit and a storage element.
9. A method of writing to a pair of memory cells, wherein the pair of memory cells is as claimed in any one of claims 1 to 4, comprising:
accessing a first voltage to a bit line coupled to the other end of the storage element in any storage subunit to be written;
accessing a second voltage to a source line coupled to a first pole of an independent transistor in the memory subunit;
and introducing control voltages to the writing word line and the two word lines to control the storage elements in the storage sub-units to conduct a set-direction current, wherein the set-direction current is determined based on the voltage difference between the first voltage and the second voltage.
10. A method of reading a pair of memory cells, wherein the pair of memory cells is as claimed in any one of claims 1 to 4, comprising:
accessing a third voltage to a bit line coupled to the other end of the memory sub-unit memory element to be read;
accessing a fourth voltage to a source line coupled to a first pole of an independent transistor in the memory subunit;
introducing a control voltage to a word line coupled to a control electrode of an independent transistor in the memory subunit, and acquiring voltage value information and current value information of a memory element of the memory subunit, wherein the voltage value information is determined based on a voltage difference between the third voltage and the fourth voltage;
and determining the storage information in the storage subunit according to the voltage value information and the current value information.
11. A method of fabricating a memory cell pair, comprising:
forming a pair of memory sub-cells and a common transistor on a substrate under the same etching process step; each memory subunit includes a separate transistor and a memory element; wherein each transistor includes a first pole, a second pole, and a control pole for controlling the conduction of the first pole and the second pole;
for each independent transistor, coupling its control electrode with a word line, coupling its first electrode with one end of the corresponding storage element, coupling its second electrode with a common source line, and coupling the other end of each storage element individually on a bit line;
the control electrode of the common transistor is coupled to a write word line, and the first and second electrodes thereof are each coupled between an independent transistor of a memory subunit and a storage element.
CN202210298988.9A 2022-03-25 2022-03-25 Memory cell pair, array, memory circuit, electronic device and method Pending CN116844604A (en)

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